Abstract: A shift register including shift register units substantially cascaded is disclosed. Each shift register unit is controlled by first and second clock signals opposite to each other for generating an output signal. Each shift register unit includes first and second switch devices and first and second devices. The first switch device provides the output signal through an output node. The first driving device drives the first switch device according to a first input signal to activate the output signal. The second driving device provides a first voltage signal, according to the first clock signal, to drive the first switch device and de-activate the output signal. When the first switch device de-activates the output signal, the second switch device provides the second voltage signal to the output node according to the second clock signal. A level of the first voltage signal is lower than a level of the second voltage signal.

Abstract: An exemplary shift register (20) includes a plurality of shift register units (200) connected one by one. Each of the shift register units includes a clock signal input terminal (TS), a reverse clock signal input terminal (TSB), a high level signal input terminal (VH), a low level signal input terminal (VL), an output terminal (VOUT), a reverse output terminal (VOUTB), a first input terminal (VIN1), a second input terminal (VIN2), a common node (P), a first switch circuit (31) providing a high level signal to the common node, a second switch circuit (32) providing a low level signal to the common node, a third switch circuit (33) providing a clock signal to the output terminal, a fourth switch circuit (34) providing a low level signal to the output terminal, and an inverter (36) connected between the output terminal and the reverse output terminal.

Abstract: A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer.

Abstract: A shift register includes several stages of shift register units. Each shift register unit includes a first level lifting unit, first level lowering unit, first driving unit and level controller. The first level lifting unit and first level lowering unit control the scan signal to be equal to a first timing signal and first voltage, respectively. The level controller includes an input unit, a charge storage unit, a second level lifting unit and a second level lowering unit. The input unit controls the third control signal to be equal to the first voltage at a node. The charge storage unit stores a voltage of the timing signal at the node. The second level lifting unit and second level lowering unit respectively control the second control signal to be equal to the third control signal and the first voltage to turn on and turn off the first level lowering unit.

Abstract: A shift register is used for outputting an output pulse at output end in response to a delay of an input pulse received at an input end. The shift register includes a controller, a pre-charging switch, a level shifting switch, and an output generator. The controller is used for generating a level switching signal. The pre-charging switch is used for conducting a first supply voltage to a level shifting node in response to the input pulse. The level shifting switch turns on in response to the level switching signal. The output generator is used for generating the output pulse at the output end, when the level shifting switch turns on.

Abstract: A shift register including shift register units controlled by first and second clock signals for generating an output signal. For each unit, in an active period, the first driving device drives the first switch device to activate the output signal, and the second driving device provides a voltage signal according to the first clock signal to drive the first switch device to de-activate the output signal. When the first switch device de-activates the output signal, the second switch device provides the voltage signal to serve as the output signal according to the second clock signal. In the active period, the voltage signal has a low level, and the first and second clock signals are set as alternating-current signals and are opposite to each other. In a blanking period, the voltage signal has a high level, and each of the first and second clock signals is set as a direct-current signal.

Abstract: A shift register circuit comprises a plurality of stages, each stage being for providing an output signal to an output load and comprising a pull up transistor for pulling the output signal up to a high voltage rail and a pull down transistor for pulling the output signal down to a low voltage rail. Each stage comprises a circuit for sampling the threshold voltage of at least one of the pull up and pull down transistors and for adding the sampled threshold voltage to a control voltage offset, to provide a threshold-voltage-compensated signal for controlling the gate of the at least one of the pull up and pull down transistors. This provides threshold voltage sampling, in particular for the thin film transistor whose threshold voltage drift must be compensated (for example the pull-down thin film transistor).

Abstract: A shift register apparatus and a method thereof are provided. The technique manner submitted by the present invention utilizes two NMOS transistors for pulling down the voltage level of the scan signals output by the shift registers within the shift register apparatus to the low level gate voltage, wherein one of the NMOS transistors is controlled by a control unit, and the other NMOS transistor is controlled by a clock signal or the inverted clock signal provided to the shift registers. Therefore, shifting amount of the threshold voltage of those NMOS transistors can trend to be flat, and the reliability of those NMOS transistors can be promoted. In addition, since only one control unit is needed to dispose in each shift register so that the layout area of whole shift register apparatus can be reduced, and the panel with narrow frame size also can be achieved by the present invention.

Abstract: The present invention provides a shift register having simple circuit scheme capable of increasing lifetime of whole circuit and a related Liquid Crystal Display (LCD). The shift register includes a plurality of shift register units connected in cascade, wherein at least one of the plurality of shift register units includes: an output terminal, a first switch element, a second switch element, a third switch element, a fourth switch element, a fifth switch element, and a sixth switch element. In addition, The LCD includes a plurality of gate output signal lines and the shift register mentioned above. The plurality of shift register units connected in cascade are coupled to the plurality of gate output signal lines, respectively.

Abstract: A high-speed shift register circuit is provided. The shift register circuit includes a first transistor supplying a clock signal to a first output terminal, a second transistor discharging the first output terminal, a third transistor supplying the above clock signal to a second output terminal, and a fourth transistor discharging the second output terminal. The gates of the first and third transistors are both connected to a first node, and the gates of the second and fourth transistors are both connected to a second node. The first node is charged by a fifth transistor which is connected between the first node and a first input terminal and which has a gate connected to a second input end.

Abstract: A shift register is disclosed, which can prevent a multi-output caused by a coupling phenomenon, the shift register comprising at least two clock transmission lines which transmit at least two clock pulses provided with the phase difference; and a plurality of stages which are supplied with the clock pulses from the clock transmission lines, and output output-signals in sequence, wherein each of the stages comprises a pull-up switching unit which is supplied with the first clock pulse, and outputs the first clock pulse as the output-signal according to a signal state of an enable node; and a noise eliminating unit which responds to the second clock pulse of which phase is prior to that of the first clock pulse supplied to the pull-up switching unit, and supplies a start pulse externally provided or the output-signal provided from the preceding stage to the enable node.

Abstract: A shift register includes a plurality of stages to output a plurality of output signals, in sequence. Each of the stages includes a driving part and a discharging part. The driving part outputs an output signal of a present stage based on one of a start signal and an output signal of a previous stage, and a clock signal. The discharging part discharges the output signal of the present stage. The discharging part includes a discharge transistor and an auxiliary transistor. The discharge transistor has a gate electrode receiving an output signal of a next stage. The auxiliary transistor has a gate electrode receiving the output signal of the next stage. The auxiliary transistor is electrically connected in series to the discharge transistor. Therefore, the chance of a malfunction is decreased, and image display quality of the display device is improved.

Abstract: A shift register includes several stages of shift register units. Each shift register unit includes a first level lifting unit, first level lowering unit, first driving unit and level controller. The first level lifting unit and first level lowering unit control the scan signal to be equal to a first timing signal and first voltage, respectively. The level controller includes an input unit, a charge storage unit, a second level lifting unit and a second level lowering unit. The input unit controls the third control signal to be equal to the first voltage at a node. The charge storage unit stores a voltage of the timing signal at the node. The second level lifting unit and second level lowering unit respectively control the second control signal to be equal to the third control signal and the first voltage to turn on and turn off the first level lowering unit.

Abstract: A shift register circuit includes plural stages of signal holding circuits which are cascade-connected to hold a signal based on a supplied input signal, to output an output signal based on the held signal, and to supply the output signal as an input signal to a subsequent stage. Each of the plural stages of signal holding circuits includes an output circuit which is supplied with two types of clock signals consisting of a first clock signal and a second clock signal. A timing of the second clock signal is delayed by a predetermined delay time with respect to a timing of applying the input signal, which is supplied with a signal at a timing delayed by the delay time of the second clock signal from the timing of applying the input signal, and which outputs the output signal at a timing responsive to the first clock signal.

Abstract: A pre-charge circuit includes a receiving module, an enabling module, and a reset module. The receiving module receives the received driving signal of the pre-charge circuit and outputs the receiving driving signal according to a control signal. The enabling module outputs a pre-charge signal when receiving the driving signal. The reset module is electrically coupled between the receiving module and the enabling module for receiving a reset signal to reset the pre-charge signal.

Abstract: The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled.

Abstract: A shift register has multiple stages each of which includes a pull-up part to generate a current gate line driving signal having a first state in response to a first control signal and a clock signal, a pull-down part to generate the current gate line driving signal having a second state in response to a second control signal, a pull-up driver to generate the first control signal to control the pull-up part in response to a previous gate line driving signal provided from a previous stage, a following gate line driving signal provided from a following stage, and an input voltage signal externally provided, and a pull-down driver to generate the second control signal to control the pull-down part in response to a third control signal provided from the pull-up driver and the input voltage signal, in which the second control signal swings between first and second voltage levels in association with the input voltage signal that swings between predetermined voltage levels.

Abstract: Malfunction caused by leakage current of the transistor is prevented in the shift register in which the signal can be shifted bi-directionally. The bi-directional unit shift register includes a transistor Q1 between a clock terminal CK and an output terminal OUT, a transistor Q2 for discharging the output terminal OUT, and transistors Q3, Q4 for providing first and second voltage signals Vn, Vr, which are complementary to each other, to the first node or a gate node of the transistor Q1. Furthermore, a transistor Q5, having a gate connected to a second node or a gate node of the transistor Q2, for discharging the first node is arranged.

Abstract: The present invention relates to a shift register and a gate driver therefor.

Abstract: In a shift register circuit, a reduction of a driving capability caused by an increased operating rate is prevented. A shift register circuit includes a first transistor between an output terminal and a clock terminal, a second transistor between the output terminal and a first power-supply terminal, and a third transistor between the gate of the first transistor and a second power-supply terminal. The shift register circuit further includes a fourth transistor that charges the gate node of the third transistor on the basis of a signal inputted to a first input terminal, and a capacitive element that boosts the gate node of the third transistor that has been charged.

Abstract: A shift register and a shift register apparatus are provided. The shift register includes a plurality of shift register apparatus, and each shift register apparatus comprises a pre-charge circuit, a pull-up circuit and a pull-down circuit. The pre-charge circuit is used for sampling an input signal according to a first clock signal and a second clock signal respectively and generate a first charging signal and a second charging signal respectively. The pull-up circuit is coupled to the pre-charge circuit. The pull-up circuit receives the third clock signal and the first charging signal to output an output signal accordingly. The pull-down circuit is coupled to the pre-charge circuit and the pull-up circuit. The pull-down circuit receives the fourth clock signal and the second charging signal to decide whether to couple the output signal to a common potential.

Abstract: A shift register circuit has a plurality of shift registers connected in series, each shift register having a phase-shifting element and a pull-high element, wherein the phase-shifting element receives a first input signal, a first clock signal and a second clock signal, and the first clock signal and the second clock signal are complementary in phase. The pull-high element is used for pulling up an output signal to a high logic level, and includes a logic unit, wherein no current path is established in the pull-high element when the shift register is operated in any type of periods.

Abstract: A shift register includes a plurality of register stages. Each register stage includes an output circuit, a first switching circuit and a second switching circuit. The output circuit is capable of outputting a first driving signal. The first switching circuit is used to pull down the output circuit into a low voltage level when the output circuit is not outputting the first driving signal. The second switching circuit is capable of receiving an input signal. The first switching circuit holds electric charges by the parasitical capacitor resident in the transistor in order to keep the first switching circuit in a turn-on state when the output circuit is not outputting the first driving signal.

Abstract: A shift register is used for outputting an output pulse at output end in response to a delay of an input pulse received at an input end. The shift register includes a controller, a pre-charging switch, a level shifting switch, and an output generator. The controller is used for generating a level switching signal. The pre-charging switch is used for conducting a first supply voltage to a level shifting node in response to the input pulse. The level shifting switch turns on in response to the level switching signal. The output generator is used for generating the output pulse at the output end, when the level shifting switch turns on.

Abstract: A bidirectional shift register in which an operation margin is not lowered when a shift direction of a signal is switched is provided. A unit shift register SRk at one stage of a plurality of stages of shift registers includes a gate line drive unit, a forward shift unit, and backward shift unit each capable of operating as one-stage shift register. The gate line drive unit outputs a gate line drive signal Gk to a gate line GLk in response to a previous-stage forward signal Gnk?1 and a subsequent-stage backward signal Grk+1. The forward shift unit performs only forward shift to output a forward signal Gnk to the subsequent-stage in response to the previous-stage forward signal Gnk?1, and the backward shift unit performs only backward shift to output a backward signal Grk to the previous-stage in response to the subsequent-stage backward signal Grk+1.

Abstract: A shift register having a plurality of stages for shifting a start pulse and outputting a shifted start pulse to a next stage, each of the plurality of stages includes a pull-up transistor controlled by a first node to apply a first clock signal to an output line, a first pull-down transistor controlled by a second node to apply a first driving voltage to the output line, a controller for controlling the first and second nodes, and a compensating capacitor connected between the first node and an input line of a second clock signal, the second clock signal being different from the first clock signal.

Abstract: A shift register includes, in the output stage, a first transistor connected between an output terminal and a first clock terminal and a second transistor connected between the output terminal and a first power terminal. Third and fourth transistors constitute an inverter which inverses the level of the gate of the second transistor and outputs it to the gate of the first transistor. An isolation circuit formed by fifth and sixth transistors is provided between the gate of the first transistor and the gate of the fourth transistor. The fifth transistor is diode-connected. When the gate of the first transistor becomes higher than the gate of the fourth transistor, the first and fourth transistors are electrically isolated from each other.

Abstract: The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit.

Abstract: A shift register includes several stages of shift register units. Each shift register unit includes a first level lifting unit, first level lowering unit, first driving unit and level controller. The first level lifting unit and first level lowering unit control the scan signal to be equal to a first timing signal and first voltage, respectively. The level controller includes an input unit, a charge storage unit, a second level lifting unit and a second level lowering unit. The input unit controls the third control signal to be equal to the first voltage at a node. The charge storage unit stores a voltage of the timing signal at the node. The second level lifting unit and second level lowering unit respectively control the second control signal to be equal to the third control signal and the first voltage to turn on and turn off the first level lowering unit.

Abstract: A disable circuit for using in a dynamic shift register unit comprising: a first input, a second input, an output, a first reference line for receiving a first supply voltage, a second reference line for receiving a second supply voltage, and six transistors. The disable circuit is capable of being coupled with a dynamic shift register unit having an input for receiving an input pulse and an output for outputting a shifted pulse. The disable circuit generates an output signal during an input pulse period or an output pulse period for the dynamic shift register unit, wherein the input pulse period and the output pulse period are responsive to a first input pulsed signal from the first input and a second input pulsed signal from the second input, respectively.

Abstract: A shift register has an output stage formed by a first transistor connected between an output terminal and a first clock terminal and a second transistor connected between the output terminal and a ground. Third and fourth transistors are connected in series between the gate of the first transistor (first node) and the ground. A second node between the third and fourth transistors is connected to a power source via a fifth transistor. The fifth transistor has its gate connected to the first node. Accordingly, when the third and fourth transistors are turned off to raise the first node in level, the fifth transistor is turned on, whereby a predetermined voltage is applied to the second node.

Abstract: A shift register circuit including a first shift register unit, a second shift register unit, a third shift register unit, and a fourth shift register unit connected in serial. The second shift register unit includes an output terminal, and a pull down system pulling the voltage of the output terminal of the second shift register unit according to a pull down signal. The fourth shift register unit includes a third switch and a fourth switch. The fourth switch has a control terminal electrically coupled to the second terminal of the third switch and the pull down unit. The fourth shift register unit generates the pull down signal according to the voltage level of the connecting point between the third switch and the fourth switch.

Abstract: A shift register minimizing bias stress applied to transistors is disclosed.

Abstract: Disclosed is a semiconductor circuit in which a floating node is set to any voltage by utilizing a control signal which is applied to a refresh terminal and has a period shorter than that of a clock signal. The semiconductor circuit includes first and second transistors connected between a first clock terminal and a first power supply terminal, third and fourth transistors connected between the refresh terminal and the first power supply terminal, and fifth and sixth transistors connected between a second power supply terminal and the first power supply. Gates of the fourth and fifth transistors are connected in common to an input terminal, a gate of the third transistor is connected to a second clock terminal, a gate of the first transistor is connected to a connection node between the fifth and sixth transistors, the gate of the second transistor is connected to the gate of the sixth transistor, and a connection node between the first and second transistors is connected to an output terminal.

Abstract: A shift register structure comprising a shift register for sequentially outputting voltages as a clock signal and a start voltage are inputted thereto, and a cleaner means connected to the shift register for removing noise within the start voltage. The cleaner means is a transistor for inputting a clock signal to a gate and for inputting a signal outputted from the shift register to a source.

Abstract: A shift register without a feedback signal of a post-stage shift register utilizing a latch mechanism and a clock signal to control the voltage of an output of the shift register is provided. The shift register reduces the transistor size and the circuit layout area. The shift register also improves the issue the overlapping between two adjacent shift registers to reduce the after-image of a liquid crystal display.

Abstract: A shift register in an amorphous-silicon gate driver comprises a pull-up transistor and two pull-down modules. The pull-up transistor produces a positive pulse when the clock signal is high and the gate of the pull-up transistor is also high. The gate of the pull-up transistor is pulled down to a negative voltage level Vss by two pull-down transistors in the pull-down modules. Each pull-down module also has a further pull-down transistor to keep the output terminal at Vss after the output pulse is produced. The two pull-down modules are operated in a cooperative manner so that each pull-down transistor is conducting approximately 50% of the time. The gates of the pull-down transistors are kept at a positive voltage level approximately 50% of the time and at Vss? approximately 50% of the time with Vss? being more negative than Vss.

Abstract: A shift register having a plurality of stages for shifting a start pulse and outputting a shifted start pulse to a next stage, each of the plurality of stages includes a pull-up transistor controlled by a first node to apply a first clock signal to an output line, a first pull-down transistor controlled by a second node to apply a first driving voltage to the output line, a controller for controlling the first and second nodes, and a compensating capacitor connected between the first node and an input line of a second clock signal, the second clock signal being different from the first clock signal.

Abstract: A shift register circuit with high stability includes a plurality of stages, each including a supplementary unit for supplementing an output node with low voltage level. The present invention utilizes an output signal of the output node to feed back to a shift register circuit unit and act as a control signal. The control signal controls the shift register circuit unit, and further the output node of the shift register circuit unit is continuously supplemented with low voltage level. Thus, the shift register circuit of the present invention has the function of driving signal shift according to the necessity of active matrix liquid crystal panel. Furthermore, when an amorphous silicon thin film transistor is embodied in the shift register circuit, the present invention restrains the shift phenomena of the threshold voltage of the amorphous silicon thin film transistors and thereby increases the lifetime and stability of the shift register circuit.

Abstract: A high-stability shift circuit using amorphous silicon thin film transistors, which utilizes two out-of-phase pulses to control the operating mechanism and the bias-relations among transistors in the shift circuit. This makes the transistors under the driving conditions of positive/negative-alternating biases so as to restrain the voltage shift of the transistors such that the threshold voltage will not excessively increase along with the increasing operating time. This can not only increase the lifetime of the amorphous silicon thin film transistors but also extend the operating time of the shift circuit.

Abstract: The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit.

Abstract: A shift register includes a plurality of pulse generation portions for generating a series of pulse signals in response to a level change of inputted clock signals, and a plurality of shift pulse generation units. The plurality of shift pulse generation units has a predetermined shift pulse generation unit, with the predetermined shift pulse generation unit having a status signal generation circuit for outputting a first status signal to common wiring to which both of an earlier shift pulse generation unit and a later shift pulse generation unit are connected, and a clock supply circuit for supplying a clock signal to the pulse generation portion which belongs to the predetermined shift pulse generation unit. In addition, there is a first period in which the clock supply circuit supplies the clock signal to the pulse generation portion which belongs to the predetermined shift pulse generation unit and a second period in which the clock signal is not supplied.

Abstract: A shift register includes a plurality of pulse generation portions for generating a series of pulse signals in response to a level change of inputted clock signals, and a plurality of shift pulse generation units. The plurality of shift pulse generation units has a predetermined shift pulse generation unit, with the predetermined shift pulse generation unit having a status signal generation circuit for outputting a first status signal to common wiring to which both of an earlier shift pulse generation unit and a later shift pulse generation unit are connected, and a clock supply circuit for supplying a clock signal to the pulse generation portion which belongs to the predetermined shift pulse generation unit. In addition, there is a first period in which the clock supply circuit supplies the clock signal to the pulse generation portion which belongs to the predetermined shift pulse generation unit and a second period in which the clock signal is not supplied.

Abstract: A current register unit. A first transistor of a first type, second to sixth transistors of a second type, and first and second capacitors are provided, and an image current signal is stored in the current register unit when a control signal is at a first logic level, and the image current signal is output by the current register unit when the control signal is at a second logic level. An image display device that utilizes the current register unit is also disclosed.

Abstract: A shift register having a built-in level shifter includes a buffer outputting a shift pulse using a first clock signal and a first supply voltage via voltages at first and second nodes; a first controller controlling the voltage of the first node via the start pulse and the second node; and a second controller controlling the second node voltage using the first and second supply voltage via the start pulse and the second clock signal. The level shifter includes a third controller forming a current path between third supply voltage input line and first supply voltage input line controlling a third node using the first supply voltage and a third supply voltage via the voltage of the second node and two of first to fourth clock signals; and an output part outputting the level-shifted shift pulse using the first and third supply voltage via the voltage at the third node.

Abstract: In a shift register and LCD device having the shift register that may be employed in the liquid crystal display device having a large screen size and a large resolution, the shift register includes stages cascade-connected with each other and each of the stages have a carry buffer for generating a carry signal. The pull-down transistor of each of the stages of the shift register is divided into a first pull-down transistor and a second pull-down transistor. A power voltage Vona larger than the power voltage Von applied to a clock generator is applied to the shift register. A signal delay due to the RC delay of the gate lines may be minimized, the shift register is independent of the variation of the threshold voltage of the TFTs, and image display quality may not be deteriorated.

Abstract: A shift register has m stages which store one of two states, where m is an integer more than 1, each stage including clock input terminals at which n-phase clock signals are input, where n is an integer more than 1, and an input terminal, and an output terminal. The input terminal of one stage receives the signal delivered from an input terminal of the shift register or from the output terminal of the previous stage. The signal output at the output terminal of one stage is passed to the input terminal of the subsequent stage or to an output terminal of the shift register. Each stage receives an initial state level from one of the clock input terminals. The initial state level is used to initialize the state of each stage.

Abstract: Each of stages RS(1), RS(2), . . . of a shift register is constituted by six TFTs. A ratio of a channel width and a channel length (W/L) of each of these TFTs 1 to 6 is set in accordance with a transistor characteristic of each TFT in such a manner that the shift register normally operates for a long time even at a high temperature.

Abstract: A circuit for limiting loss in a second circuit. The circuit may include a first timer, a second timer and one or more logic gates. The first timer may produce a first output in a given state if the duration of a pulse for use with the second circuit reaches a first predetermined amount of time, where the first predetermined amount of time is related to a parameter of the second circuit. The second timer may produce a second output in the given state if the first timer does not produce the first output in the given state when the duration of the pulse reaches a second predetermined amount of time. The one or more logic gates may have an output that is the same as the pulse unless and until the output of the first timer or the second timer is in the given state, at which time, the output of the one or more logic gates is forced to a non-pulsed state.

Abstract: Each of stages RS(1), RS(2), . . . of a shift register is constituted by six TFTs. A ratio of a channel width and a channel length (W/L) of each of these TFTs 1 to 6 is set in accordance with a transistor characteristic of each TFT in such a manner that the shift register normally operates for a long time even at a high temperature.