Particular Output Circuit Patents (Class 377/75)
  • Patent number: 11107380
    Abstract: The present disclosure provides a gate driver-on-array (GOA) unit and a method of driving the same, a GOA circuit, and a display apparatus. The GOA unit includes a pulling-up circuit, a pulling-down circuit and an output holding circuit. The pulling-up circuit is configured to output a gate scanning signal from the output terminal, under the control of a trigger signal, a first control signal and a second control signal. The output holding circuit is configured to hold the gate scanning signal output from the output terminal, under the control of the trigger signal, the first control signal and the second control signal. The pulling-down circuit is configured to reset the gate scanning signal and hold the gate scanning signal in a reset state for a set time period, under the control of the trigger signal, the first control signal and the second control signal.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: August 31, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventor: Bo Wang
  • Patent number: 10872549
    Abstract: The present disclosure provides a gate driving circuit, a shift register, and a driving control method thereof. The shift register includes: a gate signal generation circuit configured to generate a first gate signal for gating transistors, wherein the gating transistors comprise a first gating transistor and a second gating transistor coupled in series; a gate signal output control circuit configured to receive a first level signal, and output a first gate signal from the gate signal generation circuit to the first gating transistor and the second gating transistor under control of the first level signal; and a control circuit configured to receive a second level signal, a first control signal, and a second control signal, and output the first control signal to the first gating transistor and output the second control signal to the second gating transistor under control of the second level signal.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: December 22, 2020
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lei Mi, Yanna Xue, Zhiying Bao, Yong Zhang, Lu Bai, Jingpeng Wang, Gang Hua, Haobo Fang, Lingxiang Yuan
  • Patent number: 10726778
    Abstract: The present disclosure provides an emission driving circuit, which includes: a first node control module configured to provide an input signal or a high level signal to a first node based on a first clock signal and a second clock signal, to control a level at the first node; a second node control module configured to control a level at a second node based on the level at the first node, the first clock signal, the second clock signal, a first low level signal and the high level signal; and an output control module configured to control an output terminal to output high or low level based on level at the first node, level at the second node, the high level signal and a second low level signal. A low level of the first low level signal is different from a low level of the second low level signal.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: July 28, 2020
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventors: Dongxu Xiang, Yue Li, Renyuan Zhu, Yana Gao, Xingyao Zhou, Juan Zhu, Zhonglan Cai, Yilin Xu, Gaojun Huang
  • Patent number: 10347203
    Abstract: Disclosed is a GOA drive circuit, including a plurality of GOA drive units. Each trigger unit in first K GOA drive units includes a first thin film transistor, which has a gate connected to a trigger clock corresponding to the trigger unit. The trigger clock is configured to turn off the trigger unit when a scan clock of an output unit corresponding to the trigger unit is at a high level.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: July 9, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Tuo Feng, Xiangyang Xu
  • Patent number: 10198987
    Abstract: The gate driving circuit includes a shift register including a plurality of stages. An n-th stage among the plurality of stages includes: a pull-up switching element outputting a first clock to an output node in accordance with a voltage in a Q node, a pull-down switching element outputting a gate low voltage VGL to the output node in accordance with a voltage in a QB node, and a logic unit inverting and outputting a voltage in the Q node and a voltage in the QB node.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: February 5, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: WooSung Shim, JunHo Bong
  • Patent number: 9761175
    Abstract: A shift register is proposed, comprising: a first control module connected to an ON voltage access terminal and a first node, for controlling whether to output an ON voltage and a first control signal to the first node; a second control module connected to the ON voltage access terminal, a second node and an output terminal, for controlling whether to output the ON voltage and a voltage of the output terminal to the second node; an output module connected to the first node, the second node, the output terminal, an OFF voltage access terminal, and the ON voltage access terminal, for inputting the ON or OFF voltage to the output terminal according to voltages of the first and second nodes; and an input module connected to an input terminal, for controlling whether to input a signal of the input terminal to the first and second control modules.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: September 12, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhanjie Ma, Tuo Sun
  • Patent number: 9135878
    Abstract: A shift register is provided that outputs a gate driving pulse even if a start pulse provided to a first stage is not synchronized with a clock pulse. The shift register has multiple stages that sequentially output gate driving pulses. At least one stage includes a first switching device turned-on by a first clock signal and applying the start pulse to a first node. A second switching device is turned-on by the first clock signal and applies a first supply voltage to a second node. A third switching device is turned-on by the start pulse applied to the first node and outputs a second clock signal. A fourth switching device is turned-on by the first supply voltage and outputs a second supply voltage. A fifth switching device is turned-on by the start pulse and applies the start pulse to the first node.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: September 15, 2015
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Seong Gyun Kim
  • Publication number: 20150116194
    Abstract: A shift register includes unit circuits connected in a cascade, and each of the unit circuits includes a logic circuit, a first output unit, and a second output unit. The first output unit is a buffer amplifier for outputting a driving signal and includes: a first transistor for outputting a first voltage; and a second transistor for outputting a second voltage lower than the first voltage. The second output unit is a buffer amplifier for outputting a signal to a next unit circuit in the cascade and includes: a third transistor for outputting a third voltage; and a fourth transistor for outputting a fourth voltage lower than the third voltage. The second voltage is set at a potential higher than the fourth voltage.
    Type: Application
    Filed: April 25, 2012
    Publication date: April 30, 2015
    Applicant: PANASONIC CORPORATION
    Inventors: Masafumi Matsui, Hitoshi Tsuge
  • Patent number: 8982033
    Abstract: A display device including various portions, circuits and other arrangements for outputting various pulses and triggers, for controlling forward shift and backward shift operations.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: March 17, 2015
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
  • Patent number: 8949493
    Abstract: Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: February 3, 2015
    Assignee: Altera Corporation
    Inventors: Curt Wortman, Chong H. Lee, Huy Ngo
  • Patent number: 8803783
    Abstract: A plurality of cascaded unit register circuits which comprises a bidirectional shift register include main stages and dummy stages at the top before the main stages and dummy stages at the bottom after the main stages. A k-th stage outputs a pulse Pk in synchronization with a clock signal with a reference point N1 being at H level. The main stages include terminals NSF and NSB for setting N1 to H to which Pk?1 and Pk+1 are input, respectively, and terminals NRB and NRF for setting N1 to L level to which Pk?2 and Pk+2 are input, respectively. The order of generation of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched. Top dummy stages do not have NRB. Bottom dummy stages do not have NRF.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: August 12, 2014
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
  • Patent number: 8803782
    Abstract: A bidirectional shift register outputs pulses from a plurality of cascaded unit register circuits in a shift order which is one of a forward direction and a reverse direction. A ?th stage of unit register circuit (38) has two set terminals connected to respective outputs of (??1)th and (?+1)th stages and two reset terminals connected to respective outputs of (?+2)th and (??2)th stages. The unit register circuit (38) sets, when a pulse is input to any one of the set terminals, a reference point N1 to an H level, and, when a pulse is input to any one of the reset terminals, N1 to an L level. The order of phase change of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: August 12, 2014
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
  • Patent number: 8669896
    Abstract: A method of controlling a successive-comparing-register analog-to-digital convertor (SAR ADC) is provided. Based upon the method, the SAR ADC receives a conversion clock that controls a conversion rate of the SAR ADC.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: March 11, 2014
    Assignee: Mediatek Inc.
    Inventors: Jen-Che Tsai, Chao-Hsin Lu
  • Patent number: 8670520
    Abstract: A shift register has a first latch and a second latch and a first output circuit and a second output circuit. The first latch and the second latch are series-connected. The latches are implemented to take over a signal state applied to their data inputs in a transparent state and to maintain the taken-over signal state in a non-transparent operating state. Clock inputs of the latches are switched such that the second latch is in the transparent operating state when the first latch is in the non-transparent operating state and vice versa. The first output circuit is implemented to provide a predetermined level independent of the signal state existing in the first latch at a first shift register output of the shift register in the transparent operating state and to provide a level depending on the signal state stored in the first latch in the non-transparent operating state of the first latch.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: March 11, 2014
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Matthias Oberst, Johann Hauer
  • Publication number: 20140064439
    Abstract: A shift register unit, shift register and display apparatus, for addressing the issue that the leakage current of the depletion TFT affects the shift register.
    Type: Application
    Filed: December 14, 2012
    Publication date: March 6, 2014
    Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Haigang Qing, Xiaojing Qi
  • Patent number: 8654226
    Abstract: A gated-clock shift register including a series of clocked flip-flops with preceding outputs connected to subsequent inputs as a horizontal digital shift register. Each flip-flop (or other state holding device) includes a clock buffer between the respective flip-flop's clock, and the global clock. Each clock buffer propagates the clock signal when it determines the associated flip-flop will have a state change during that clock cycle (e.g., via an XOR of the flip-flops input and output signals). In the absence of a state change, that buffer does not propagate the clock signal, essentially only clocking the relevant flip-flops. Further, the clock buffer may be implemented with only NMOS devices (or alternatively, only PMOS devices), which offers power savings over an otherwise required CMOS implementation.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: February 18, 2014
    Assignee: Analog Devices, Inc.
    Inventor: Steven Decker
  • Patent number: 8558777
    Abstract: A gate driver, comprises a plurality of shift registers configured to output signals sequentially such that an Nth shift register is reset by an output signal of an (N+2)th shift register, wherein last, second last and third last shift registers are reset by a last output signal of the last shift register.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: October 15, 2013
    Assignee: LG Display Co., Ltd.
    Inventors: Yong Ho Jang, Binn Kim, Hyung Nyuck Cho
  • Patent number: 8553026
    Abstract: A display device includes a plurality of scan lines and a scan driver. The scan driver includes a plurality of stages for transmitting a scan signal having a first voltage to the plurality of scan lines, and each of the stages includes a sequential switching unit, a sequential output unit, a concurrent switching unit, and a concurrent output unit. The concurrent output unit includes a first transistor for transmitting a second control signal to the output terminal according to a first control signal during a concurrent driving period before the scan signal is converted from a first level to a second level according to the second control signal, and a gate voltage of the first transistor is controlled by a voltage that is different from the first voltage according to the first control signal.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: October 8, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventor: Seong-Il Park
  • Patent number: 8552961
    Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a driving unit, an input unit, a driving adjustment unit and a pull-down unit. The driving unit is utilized for outputting a gate signal according to a system clock and a driving control voltage. The input unit is put in use for outputting the driving control voltage according to an input control signal and a first input signal. The driving adjustment unit is employed for adjusting the driving control voltage according to a second input signal and a third input signal. The pull-down unit is used for pulling down the gate signal and the driving control voltage according to a fourth input signal.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: October 8, 2013
    Assignee: AU Optronics Corp.
    Inventors: Yu-Chung Yang, Yung-Chih Chen
  • Patent number: 8553123
    Abstract: An image sensing apparatus includes a pixel array including an optical black region and effective pixel region, and a scanning unit which scans the pixel array. The scanning unit includes a first shift register which scans the optical black region by a shift operation, and a second shift register which scans the effective pixel region by a shift operation. The second shift register starts the shift operation during a first period when the first shift register scans the optical black region, and scans a readout region serving as a partial region of the effective pixel region during a second period following the first period.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: October 8, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tomoyuki Noda, Tetsuya Itano, Koichiro Iwata, Hidekazu Takahashi
  • Publication number: 20130169609
    Abstract: Disclosed are a shift register, and a gate driving circuit including a plurality of shift registers connected in sequence to respectively supply scan signals to a plurality of gate lines of a display device. Each shift register includes: an input unit which outputs a directional input signal having a gate high or low voltage based on an output signal from a previous or subsequent shift register to a first node; an inverter unit which is connected to the first node, generates an inverting signal to a signal at the first node, and outputs the inverting signal to a second node; and an output unit which includes a pull-up unit connected to the first node and activating an output clock signal based on the signal at the first node, and a pull-down unit activating and outputting a pull-down output signal based on a signal at the second node.
    Type: Application
    Filed: December 17, 2012
    Publication date: July 4, 2013
    Applicant: HYDIS TECHNOLOGIES CO., LTD.
    Inventor: Hydis Technologies Co., Ltd.
  • Patent number: 8451260
    Abstract: Each shift register includes a first element controlled by a first potential node to supply a first driving voltage to an output terminal, a second element controlled by a second potential node to supply a second driving voltage lower than the first driving voltage to the output terminal, and a third element for controlling the first potential node and the second potential node so as to have opposite potential levels. Voltages are applied to the third element so that a state of A>B and A>C and a state of A<B and A<C, or a state of A>B and A<C and a state of A<B and A>C, or a state of A<B and A>C and a state of A>B and A<C are switched alternately (A: a gate terminal of the third element, B: a voltage applied to a first terminal thereof, C: a voltage applied to a second terminal thereof).
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: May 28, 2013
    Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Yuki Okada, Mitsuru Goto, Takahiro Ochiai, Naoki Takada, Youzou Nakayasu
  • Patent number: 8427355
    Abstract: An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: April 23, 2013
    Assignee: University of Macau
    Inventors: Sai-Weng Sin, Li Ding, Yan Zhu, He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Seng-Pan U, Rui Paulo da Silva Martins, Franco Maloberti
  • Patent number: 8390611
    Abstract: An image display system includes a gate driving circuit. The gate driving circuit includes several stages of gate drivers each for generating a gate driving signal to drive a row of pixels. Each stage of the gate driver receives a clock signal and a first reset signal. A first stage of the gate driver receives a vertical start pulse as an input signal of the first stage. The remaining stages of the gate drivers respectively receive the gate driving signal generated by a previous stage of the gate driver as the input signal of the remaining stages. Each stage of the gate drivers further receives the gate driving signal generated by a next stage of the gate driver as a second reset signal, and generates the corresponding gate driving signal according to the clock signal, the first reset signal, and the corresponding input signal and second reset signal.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: March 5, 2013
    Assignee: Chimei Innolux Corporation
    Inventors: Fu-Yuan Hsueh, Tzu-Yu Cheng
  • Publication number: 20130034199
    Abstract: To provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit includes a plurality of transistors each including an oxide semiconductor. In accordance with operations of the pulse signal output circuit, the threshold voltage of the transistor including an oxide semiconductor is changed. A shift register including the pulse signal output circuit is formed. A pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
    Type: Application
    Filed: July 30, 2012
    Publication date: February 7, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Kouhei Toyotaka
  • Publication number: 20120293401
    Abstract: Embodiments of the disclosed technical solution provides a shift register unit circuit which operates based on two clock signals and comprises input terminals, a pre-charging circuit, a first level pulling-down circuit, a second level pulling-down circuit and a scan signal output terminal. Embodiments of the disclosed technical solution also provides a shift register having at least two shift register unit circuits connected in cascade, and further provides a liquid crystal display array substrate and a liquid crystal display. Embodiments of the disclosed technical solution settles problems that a threshold voltage of the pulling-down TFT would drift under a direct current bias voltage and a output is unstable due to a clock hopping, increases a reliability of the circuit and reduces power consumption.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 22, 2012
    Applicants: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Tianma LI, Xiaojing QI, Haigang QING
  • Publication number: 20120269316
    Abstract: A shift register is provided in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes stages for sequentially outputting scan pulses. An nth one of the stages includes a node controller for controlling voltages at nodes, and an output unit for outputting any one of a corresponding one of the scan pulses and a first discharging voltage according to the voltages at the nodes. The nodes include set and reset nodes. The node controller of the nth stage includes a first switching device controlled by a voltage supplied to the reset node for supplying a second discharging voltage to the set node, and an inverter circuit controlled by a voltage supplied to the set node for supplying any one of a charging voltage and a third discharging voltage to the reset node.
    Type: Application
    Filed: December 28, 2011
    Publication date: October 25, 2012
    Inventors: Yong-Ho JANG, Seung-Chan CHOI, Jae-Yong YOU, Woo-Seok CHOI
  • Publication number: 20120269315
    Abstract: Discussed herein is a shift register which is capable of stabilizing an output thereof. The shift register includes a plurality of stages for sequentially outputting scan pulses in such a manner that high durations of the scan pulses partially overlap with each other. Each of the stages includes a node controller for controlling a charging duration of a set node, and an output unit for outputting a corresponding one of the scan pulses through an output terminal for the charging duration of the set node.
    Type: Application
    Filed: December 27, 2011
    Publication date: October 25, 2012
    Inventors: Yong-Ho JANG, Seung-Chan CHOI
  • Patent number: 8284150
    Abstract: A shift register is disclosed. In one aspect, the shift register has a plurality of stages dependently coupled to an input line of a start pulse and is driven by first, second and third clock signals respectively input to first, second and third input lines. The shift register includes first and second voltage stabilizer circuits to prevent leakage currents.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: October 9, 2012
    Assignee: Samsung Mobile Display Co., Ltd
    Inventor: Sam-Il Han
  • Publication number: 20120163529
    Abstract: An exemplary shift register is adapted for receiving a preceding-stage output signal to generate a preceding-stage supply signal and outputting an input signal as an extreme value of a current-stage output signal according to the preceding-stage supply signal. The shift register includes an active controller, a voltage boosting circuit and an output circuit. The active controller receives the preceding-stage output signal and thereby produces an active control signal. The voltage boosting circuit receives a first operating voltage, the preceding-stage supply signal and the active control signal, and uses a capacitive coupling effect to change the voltage value of the preceding-stage supply signal and thereby generates an output control signal. The output circuit is electrically coupled to the voltage boosting circuit, the active controller and the input signal and determines the time of outputting the input signal as the extreme value according to the output control signal.
    Type: Application
    Filed: June 15, 2011
    Publication date: June 28, 2012
    Applicant: AU OPTRONICS CORP.
    Inventor: Chung-Chun CHEN
  • Publication number: 20120044133
    Abstract: Each stage (Xi) of a shift register includes a first output transistor (M5), a first capacitor (C1), an input gate (M1), a first switching element (M2), a second switching element (M3), a third switching element (M4), and a fourth switching element (M6).
    Type: Application
    Filed: October 23, 2009
    Publication date: February 23, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masahiko Nakamizo, Masashi Yonemaru, Kenichi Ishii, Yasuaki Iwase
  • Patent number: 8116148
    Abstract: A shift register includes a shift circuit configured to shift an input signal in synchronization with a shift dock to output an output signal of the shift register, and a clock control circuit configured to enable the shift clock in response to the input signal and disable the shift clock in response to the output signal of the shift register.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: February 14, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung-Lo Kim
  • Publication number: 20110228892
    Abstract: A shift register includes a plurality of serially-coupled shift register units each including a first node, a second node, an input circuit, a pull-up circuit and a pull-down circuit. The shift register unit receives an input voltage at an input end, and provides an output voltage at an output end. The input circuit controls the signal transmission path between a first clock signal and the first node according to the input voltage. The pull-up circuit controls the signal transmission path between a second clock signal and the output end according to the voltage level of the first node. The voltage level of the first node or the output end is maintained according to the voltage level of the second node. The voltage level of the second node is maintained according to the first clock signal, the second clock signal and the voltage level of the first node.
    Type: Application
    Filed: June 1, 2011
    Publication date: September 22, 2011
    Inventor: Wei-Jen Lai
  • Publication number: 20110228891
    Abstract: An exemplary shift register includes a plurality of transistors. The transistors are subjected to the control of a start pulse signal, a first clock signal and a second clock signal to generate a gate driving signal. The first clock signal and the second clock signal are phase-inverted with respect to each other. A logic low level of the first clock signal and another logic low level of the second clock signal are different from each other. Moreover, the transistors are negative threshold voltage transistors. A potential at the gate of the each of the transistors is lower than another potential at the source/drain of the transistor at the situation of the transistor being switched-off state.
    Type: Application
    Filed: July 15, 2010
    Publication date: September 22, 2011
    Applicant: AU OPTRONICS CORP.
    Inventors: Yu-Chung YANG, Kuo-Chang Su, Yung-Chih Chen, Chun-Hsin Liu
  • Publication number: 20110216874
    Abstract: An object of the present invention is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. In an embodiment of the pulse signal output circuit, a transistor has a source terminal or a drain terminal connected to a gate electrode of another transistor having a source terminal or a drain terminal forming an output terminal of the pulse signal output circuit, the channel length of the transistor being longer than the channel length of the other transistor. Thereby, the amount of a leakage current modifying the gate potential of the other transistor can be reduced, and a malfunction of the pulse signal output circuit can be prevented.
    Type: Application
    Filed: February 22, 2011
    Publication date: September 8, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Kouhei Toyotaka
  • Publication number: 20110216876
    Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
    Type: Application
    Filed: February 28, 2011
    Publication date: September 8, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Seiko Amano, Kouhei Toyotaka, Hiroyuki Miyake, Aya Miyazaki, Hideaki Shishido, Koji Kusunoki
  • Publication number: 20110216875
    Abstract: A pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit are provided. A clock signal is supplied to one of transistors connected to a first output terminal. A power supply potential is applied to one of transistors connected to a second output terminal. Thus, power consumed by discharge and charge of the transistor included in the second output terminal can be reduced. Further, since a potential is supplied from a power source to the second output terminal, sufficient charge capability can be obtained.
    Type: Application
    Filed: February 24, 2011
    Publication date: September 8, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Hiroyuki Miyake
  • Patent number: 7934031
    Abstract: An asynchronous logic family of circuits which communicate on delay-insensitive flow-controlled channels with 4-phase handshakes and 1 of N encoding, compute output data directly from input data using domino logic, and use the state-holding ability of the domino logic to implement pipelining without additional latches.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: April 26, 2011
    Assignee: California Institute of Technology
    Inventors: Andrew M. Lines, Alain J. Martin, Uri Cummings
  • Publication number: 20110058429
    Abstract: A shift register includes a shift circuit configured to shift an input signal in synchronization with a shift dock to output an output signal of the shift register, and a clock control circuit configured to enable the shift clock in response to the input signal and disable the shift clock in response to the output signal of the shift register.
    Type: Application
    Filed: November 5, 2010
    Publication date: March 10, 2011
    Inventor: Seung-Lo KIM
  • Patent number: 7899148
    Abstract: A shift register includes a plurality of stages, each of the stages generate an output signal, in sequence. Each of the shift register includes a present stage and a first capacitor. The present stage outputs an output signal based on one of a scan start signal and a carry signal of the previous stage. The first capacitor reduces a ripple component of the carry signal of the present stage which activates the next stage. Therefore, a carry signal having a reduced ripple component is supplied to the next stage, so that a transient current is intercepted at a transistor receiving the carry signal, which is arranged in the next stage, thus ensuring reliability of the shift register.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: March 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jae Kang, Seoung-Bum Pyoun
  • Publication number: 20110007040
    Abstract: A shift register includes cascade-connected stages, each of which includes a data latch and an output stage. In at least one embodiment, the latch has a single data input which, in use, receives a date signal from a preceding or succeeding stage. The output stage includes a first switch, which passes a clock signal to the stage output when the output stage is activated by the latch. The output stage also comprises a second switch, which passes the lower supply voltage to the stage output when the output stage is inactive.
    Type: Application
    Filed: March 31, 2009
    Publication date: January 13, 2011
    Inventors: Gareth John, Patrick Zebedee
  • Publication number: 20100290581
    Abstract: A shift register including shift register units controlled by first and second clock signals for generating an output signal. For each unit, in an active period, the first driving device drives the first switch device to activate the output signal, and the second driving device provides a voltage signal according to the first clock signal to drive the first switch device to de-activate the output signal. When the first switch device de-activates the output signal, the second switch device provides the voltage signal to serve as the output signal according to the second clock signal. In the active period, the voltage signal has a low level, and the first and second clock signals are set as alternating-current signals and are opposite to each other. In a blanking period, the voltage signal has a high level, and each of the first and second clock signals is set as a direct-current signal.
    Type: Application
    Filed: July 22, 2010
    Publication date: November 18, 2010
    Applicant: AU OPTRONICS CORP.
    Inventors: Kuo-Hsing Cheng, Yao-Jen Hsieh
  • Patent number: 7800576
    Abstract: A single-channel thin-film transistor buffer includes a first output stage including first and second thin-film transistors connected in series, a seventh thin-film transistor having one main electrode connected to a control electrode of the first thin-film transistor (first control line), the other main electrode connected to a power source of the second thin-film transistor, and a control electrode connected to a second control line, an eighth thin-film transistor having one main electrode connected to a control electrode of the second thin-film transistor (second control line), the other main electrode connected to the power source of the second thin-film transistor, and a control electrode connected to the first control line, and an eleventh thin-film transistor having a control electrode connected to an output terminal of a second output stage connected in parallel with the first output stage and one main electrode connected to the first control line.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: September 21, 2010
    Assignee: Sony Corporation
    Inventor: Seiichiro Jinta
  • Patent number: 7773718
    Abstract: A shift register circuit includes a plurality of bit register units, coupled in series, for transferring an input signal among the plurality of bit register units to sequentially output the input signal to a plurality of data output terminals according to a control signal and a clock signal, wherein the number of the plurality of data output terminals is greater than that of the plurality of bit register units, and a control unit for generating the control signal to control transference of the input signal.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: August 10, 2010
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Tung-Shuan Cheng, Yueh-Hsiu Liu
  • Publication number: 20100172461
    Abstract: A shift register including shift register units substantially cascaded is disclosed. Each shift register unit is controlled by first and second clock signals opposite to each other for generating an output signal. Each shift register unit includes first and second switch devices and first and second devices. The first switch device provides the output signal through an output node. The first driving device drives the first switch device according to a first input signal to activate the output signal. The second driving device provides a first voltage signal, according to the first clock signal, to drive the first switch device and de-activate the output signal. When the first switch device de-activates the output signal, the second switch device provides the second voltage signal to the output node according to the second clock signal. A level of the first voltage signal is lower than a level of the second voltage signal.
    Type: Application
    Filed: March 19, 2009
    Publication date: July 8, 2010
    Applicant: AU OPTRONICS CORP.
    Inventors: Kuo-Hsing Cheng, Wai-Pan Wu, Kuo-Hsien Lee, Chun-Huai Li
  • Publication number: 20100164854
    Abstract: A gate drive circuit includes a shift register having stages connected to each other in series. An (m)-th stage (‘m’ is a natural number) includes an output part, a discharging part, a first holding part and a second holding part. The output part outputs the first clock signal as a gate signal in response to a first clock signal provided from an external device and discharges the gate signal in response to a second input signal. The output part includes a first transistor having a first channel length. The discharging part discharges a signal of the first node to the second voltage level. The first holding part maintains a signal of the first node at a level of the gate signal, and is discharged to the second voltage level. The first holding part includes a second transistor having a second channel length that is longer than the first channel length. The second holding part maintains a signal of the first node at a level of the second voltage level.
    Type: Application
    Filed: October 22, 2009
    Publication date: July 1, 2010
    Inventors: Kyung-Wook Kim, Jong-Hoon Kim
  • Publication number: 20100166136
    Abstract: A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an output terminal. A pull-up driving circuit for driving the first transistor has a second transistor for providing a clock signal to a node connected to the gate of the first transistor and a boosting circuit for the node. When an output signal of a preceding stage is activated, the second transistor turns on. Thereafter, when the clock signal is activated, and the node is charged, the second transistor turns off. The boosting circuit increases the potential at the node when the second transistor turns off. Therefore, the first transistor can operate in non-saturation region and activate the output signal.
    Type: Application
    Filed: December 24, 2009
    Publication date: July 1, 2010
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Youichi TOBITA
  • Patent number: 7698355
    Abstract: A minimal area integrated polyphase interpolation filter uses a symmetry of coefficients for a channel of input data. The filter includes an input interface block for synchronizing the input signal to a first internal clock signal; a memory block for providing multiple delayed output signals; a multiplexer input interface block for outputting a selected plurality of signals for generating mirror image coefficient sets in response to a second set of internal control signals, a coefficient block for generating mirror image and/or symmetric coefficient sets, and to output a plurality of filtered signals, an output multiplexer block for performing selection, gain control and data width control on said plurality of filtered signals, an output register block synchronizing the filtered signals, and a control block generating clock signals for realization of the filter and to delay between two channels to access a coefficient set, thereby minimizing hardware in the filter.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: April 13, 2010
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventors: Aditya Bhuvanagiri, Harvinder Singh, Rakesh Malik, Nitin Chawla
  • Publication number: 20100074391
    Abstract: Disclosed are, inter alia, methods, apparatus, computer-storage media, mechanisms, and means associated with a shift register with a dynamic entry point, which may particularly useful for aligning skewed data. The dynamic entry shift register typically includes a series of storage elements, with multiplexers distributed between the storage elements. Each of the multiplexers is configured to select between: (a) the output signal of a previous storage element, and (b) the input signal. A control is configured to configure the multiplexers for a data signal applied as the input signal to induce an appropriate delay of the data signal as the output signal. The dynamic entry shift register can be scaled to accommodate a longer delay while still using only 2:1 multiplexers between stages in the dynamic entry shift register(s).
    Type: Application
    Filed: September 25, 2008
    Publication date: March 25, 2010
    Applicant: Cisco Technology, Inc., a corporation of California
    Inventors: Kenneth Michael Rose, Matthew Todd Lawson
  • Patent number: RE43850
    Abstract: As multiphase clocks to be supplied to a first gate driver that drives odd-numbered scanning lines in a liquid crystal display region and a second gate driver that drives even-numbered scanning lines, clocks, which are effective within an effective period of the image signal just before an image signal starts to be supplied to display elements for each scanning line of the liquid crystal display region, is generated and the first and second gate drivers drive switching elements in the effective period of the clock.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: December 11, 2012
    Assignee: Onanovich Group AG, LLC
    Inventor: Koji Kikuchi