Abstract: The invention provides a GOA circuit, the forward-and-reverse scan control module of the GOA circuit comprising: a first TFT and a third TFT, the first TFT having the gate connected to the gate scan drive signal of the (n?1)-th GOA unit, the source connected to the first constant voltage, and the drain connected to a first node; and the third TFT having the gate connected to the gate scan drive signal of the (n+1)-th GOA unit, the source connected to the first constant voltage, and the drain connected to the first node. With the two TFTs to control the switching of forward and reverse scanning of the GOA circuit, the present invention eliminates two control signals without increasing the numbers of TFTs and capacitors. As such, the selection for IC is increased, which enables the realization of narrow border LCD.

Abstract: The disclosure discloses a GOA circuit and a liquid crystal display apparatus. The GOA circuit includes a number of GOA unit in cascade connection, wherein the Nth level GOA unit includes a common signal point control module, a gate signal point control module, and a GAS signal operation module; wherein the common signal point control module is used to pull up the electrical level of the common signal point after the period of all gate on; a gate signal point control module is used to pull down the electrical level of a gate signal point after the period of all gate on; the GAS signal operation module is used to achieve the all gate on function by a first GAS signal and a second GAS signal to control the output of the Nth level gate driving signal in the touch panel scanning period.

Abstract: A driving circuit is provided, which includes multiple shift register units, at least one scan control unit and at least one all-gate-on unit. An operation of the driving circuit includes a driving phase and a discharging phase. During the driving phase, the at least one scan control unit controls the shift register units to output multiple driving signals successively in a first direction or in a second direction, the first direction being opposite to the second direction. During the discharging phase, the at least one all-gate-on unit controls the shift register units to output multiple driving signals simultaneously. An array substrate and a display apparatus each including the driving circuit are further provided.

Abstract: Embodiments may provide a scan driver including a plurality of stages for simultaneously outputting first scan signals in a simultaneous driving period and for progressively outputting second scan signals in a progressive driving period, wherein each of the stages includes a first signal processing unit coupled to an input terminal, a first clock terminal, a third clock terminal, an auxiliary terminal, a first power source terminal, and a second power source terminal to output a first output signal and a second output signal, and a second signal processing unit coupled to a second clock terminal and the first power source terminal to receive the first output signal and the second output signal and to output a first scan signal and a second scan signal to an output terminal.

Abstract: A scan driver may include: a first scan driving block, outputting a second clock signal to a first output terminal according to an input signal, in synchronization with a first clock signal; and a second scan driving block, outputting the first clock signal according to the output signal of the first scan driving block to a second output terminal, in synchronization with the second clock signal, wherein the first scan driving block and the second scan driving block simultaneously output an entire clock signal, according to a level of a simultaneous light emission control signal.

Abstract: A method of controlling a successive-comparing-register analog-to-digital convertor (SAR ADC) is provided. Based upon the method, the SAR ADC receives a conversion clock that controls a conversion rate of the SAR ADC.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a driving unit, an input unit, a driving adjustment unit and a pull-down unit. The driving unit is utilized for outputting a gate signal according to a system clock and a driving control voltage. The input unit is put in use for outputting the driving control voltage according to an input control signal and a first input signal. The driving adjustment unit is employed for adjusting the driving control voltage according to a second input signal and a third input signal. The pull-down unit is used for pulling down the gate signal and the driving control voltage according to a fourth input signal.

Abstract: An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.

Abstract: A shift register is disclosed. In one aspect, the shift register has a plurality of stages dependently coupled to an input line of a start pulse and is driven by first, second and third clock signals respectively input to first, second and third input lines. The shift register includes first and second voltage stabilizer circuits to prevent leakage currents.

Abstract: In a semiconductor circuit a floating node is set to any voltage by utilizing a control signal applied to a refresh terminal and has a period shorter than that of a clock signal. The circuit includes first and second transistors connected between a first clock terminal and first power supply terminal, third and fourth transistors connected between the refresh terminal and the first power supply terminal, and fifth and sixth transistors connected between a second power supply terminal and the first power supply. Gates of the fourth and fifth transistors are connected to an input terminal, a gate of the third transistor is connected to a second clock terminal, a gate of the first transistor is connected to a node between the fifth and sixth transistors, gates of the second and sixth transistors are connected, and a node between the first and second transistors is connected to an output terminal.

Abstract: A shift register includes a first flip-flop group composed of a plurality of cascaded first flip-flops, each first flip-flop having a first master latch and a first slave latch and having first and second transmission paths for transmitting a master clock and a slave clock, a second flip-flop group composed of a plurality of cascaded second flip-flops, each second flip-flop having a second master latch and a second slave latch which are each composed of a transistor with a relatively small transistor size and having a third transmission path connected to the first transmission path and a fourth transmission path connected to the second transmission path, and a transfer portion configured to transfer pieces of data held in the second flip-flops to one of the first master latches and the first slave latches of the first flip-flops.

Abstract: A shift register includes a first flip-flop group composed of a plurality of cascaded first flip-flops, each first flip-flop having a first master latch and a first slave latch and having first and second transmission paths for transmitting a master clock and a slave clock, a second flip-flop group composed of a plurality of cascaded second flip-flops, each second flip-flop having a second master latch and a second slave latch which are each composed of a transistor with a relatively small transistor size and having a third transmission path connected to the first transmission path and a fourth transmission path connected to the second transmission path, and a transfer portion configured to transfer pieces of data held in the second flip-flops to one of the first master latches and the first slave latches of the first flip-flops.

Abstract: A shift register unit includes a plurality of register units electrically coupled in cascade. Each register unit outputs an output pulse according to a first clock signal, a second clock signal and an output pulse of a previous register unit. Each register unit includes a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, and a driving unit. The first switch unit is used for conducting the input pulse to a first node when the first switch is turned on. The second switch unit is used for conducting the output pulse of the register unit according to the first clock signal to an output end when the second switch unit is turned on in response to the input pulse. The third switch unit electrically coupled to a supply end is used for conducting a supply voltage to the output end when the second switch unit is turned off.

Abstract: A shift register is disclosed.

Abstract: A shift register is disclosed.

Abstract: A shift register which is capable of simultaneously driving gate lines is disclosed. The shift register includes a plurality of stages for simultaneously supplying all-drive signals to gate lines for an all-drive period and sequentially supplying scan pulses to the gate lines for a scan period.

Abstract: A shift register includes a first flip-flop group composed of a plurality of cascaded first flip-flops, each first flip-flop having a first master latch and a first slave latch and having first and second transmission paths for transmitting a master clock and a slave clock, a second flip-flop group composed of a plurality of cascaded second flip-flops, each second flip-flop having a second master latch and a second slave latch which are each composed of a transistor with a relatively small transistor size and having a third transmission path connected to the first transmission path and a fourth transmission path connected to the second transmission path, and a transfer portion configured to transfer pieces of data held in the second flip-flops to one of the first master latches and the first slave latches of the first flip-flops.

Abstract: Digital signaling processing (DSP) circuitry that supports multiple channel or time division multiplexing (TDM) applications is provided. For example, the DSP circuitry can process one or more channels of data without mixing the data of one channel with data of another channel. DSP circuitry of the invention supports multiple channel or TDM applications by embedding a tap delay line structure within the DSP circuitry. Utilizing this embedded tap delay line structure enables the DSP circuitry to support multi-channel or TDM applications independent of any external circuitry such as logic resources, thereby freeing up those resources for other uses.

Abstract: To provide a variable dividing circuit having a high operational speed. The variable dividing circuit includes a shift register configured by cascade connection of D-type flip-flops (D11, D12, . . . , D1n) with an initializing means by clock synchronization; and a multiplexer 12 for selecting any one of output signals at respective stages of the shift register; wherein the variable dividing circuit initializes each stage of the D-type flip-flops. In this case, in an input terminal 10 of the flip-flop at the first stage, a signal at an H level or at an L level is inputted in accordance with an initializing means.

Abstract: A counter circuit is provided which is particularly suitable for controlling cyclical events. The counter consists of a chain of logic elements 160, 167, 164 which sequentially pass a ‘1’ along the chain in response to a clock signal. Each element is also responsive to a respective select signal and, if selected, behaves like a latch, whereas if unselected it behaves as if it were not there.

Abstract: A semiconductor device according to the invention is composed of a counter which outputs intermediate carry signals (CARRY 0, 1, 2) and the final carry signal (CARRY END) for determining the end of a delay output signal in a period starting from a delay pulse-generating trigger signal (DPT) and continuing for a predetermined time, and a delay circuit which outputs count up signals (COUNT UP) for counting up the counter on the basis of pulse signals generated in accordance with the intermediate carry signals and the DPT. According to the aforementioned semiconductor device, the delay output signal can be outputted without using an external clock signal.

Abstract: A sigma-delta modulator is disclosed for conversion of an analog or digital low frequency signal of high resolution into a quantized analog or digital signal, with an error feedback circuit for suppression of quantization errors. The sigma-delta modulator includes a delay device (Z−1) for delaying the input signal (X) for a plurality of scanning periods to obtain a plurality of delayed input signals (Xi), wherein i=1, 2, . . . , n and the ith one of the delayed input signals (Xi) is delayed for i scanning periods; an adder (2) for addition of the delayed input signals (Xi) each delayed by the i scanning periods to obtain a first sum signal (S1); a quantizing device (Q, Q0, Q1 to Qn) for producing quantized input signals (VZi) each delayed by the ith scanning period; an adder (3) for addition of the delayed quantized input signals (VZi) to obtain a second sum signal (S2); and a subtraction device (1) for subtraction of the sum signals (S1, S2) from an actual value of the input signal (X).

Abstract: The present invention has been made in view of the above mentioned problem, and the present invention provides a sticky signal generator for rapidly generating a sticky signal with a small layout area which uses a shift register of which the size is equal to the size of the inputted operand data.

Abstract: An LSI chip is mounted on an LSI board. Sub-buffer circuit areas where input buffers, output buffers or input/output buffers are to be formed are provided in signal lines extending from the pad to the internal circuit of the LSI chip. Each sub-buffer circuit area has a plurality of basic elements, such as transistors and resistors, connected in parallel to one another so that different combinations of those elements can be selected by switches. A latch controller is incorporated in the LSI chip, and it has latch circuits serially connected to form a shift register structure. This latch controller sends a program signal for determining the buffer circuit characteristic to the sub-buffer circuit areas. This program signal is generated when program data is input to the latch controller. The program data is given serially via input buffers from the pads on the LSI chip. The latch controller transfers the program data to the latch circuits one after another in synchronism with a clock signal.

Abstract: A parallel architecture for implementing a digital sequence generator is provided, which contains taps connected to selected fixed memory cells and the taps of the logic circuitry are switched among the cells. The architecture disclosed and claimed herein generates an identical sequence while consuming substantially less power than a linear feedback shift register implementation. The parallel architecture may also be used to implement a parallel shift register in other applications.

Abstract: A shift register for scanning a liquid crystal display includes cascaded stages. A given stage is formed with an input transistor switch that is responsive to an output pulse of a stage upstream in the chain of the cascaded stages. An output pulse of the given stage is produced in a pull-up transistor of a push-pull amplifier. A third transistor responsive to an output signal of a stage downstream of the given stage applies a control signal to a gate electrode of the pull-down transistor to render the pull-down transistor conductive.

Abstract: In a signal selecting device, a mode determination portion 61 comprises a shift register 11, a clock generating portion 20 and decoder 51. The clock generating portion 20 receives a mode signal M and generates a clock signal CK1 used for decoding the mode signal M from a system clock SYS. The shift register 11 receives the mode signal M and the clock signal CK1 and outputs signals Q.sub.0 to Q.sub.3. The decoder 51 receives the output from the shift register 11 and outputs control signals S.sub.00 to S.sub.03. Therefore, there needs only one terminal for receiving the mode signal M and no terminal for receiving a clock.

Abstract: An energy saving clock signal generator is disclosed including a source of multi-phase waveform signals, a shift register, and a matrix switch. The waveform source provide four, six or more waveform signals to the shift register and the matrix switch. A number of progressive pulses N.sub.pp which are an integer multiple of the number of waveform signals are applied from the shift register to the matrix switch. The matrix switch responds to the waveform signals and the progressive pulse signals to produce a number of output clock signals which may be used to drive adiabatic logic circuits.

Abstract: A driving circuit for use in a display apparatus for transmitting a video signal to data lines includes a plurality of shift registers; a control signal generating circuit for outputting a control signal which is at the ON level during a period shorter than a pulse width of signals outputted by the shift registers; a switching circuit controlled to be ON or OFF based on the control signal; and a sampling capacitor for holding the video signal sampled by the switching circuit. In such a driving circuit, the plurality of shift registers sequentially output signals so that the periods in which the signals are high are partially overlapped sequentially. The control signal generating circuit outputs a control signal which is at the On level during a period shorter than the signals from the shift registers. Since the switching circuit is controlled to be ON or OFF based on the control signal, a period in which the switching circuit is conductive is short.

Abstract: A successive-approximation register (SAR) has a single shift register for processing, that is presetting and selectively resetting, a number of bits. The single shift register is arranged to provide bit selection for processing the bits and also to provide desired result accumulation in the processed bits. Further, the single shift register comprises an array of stages, the stages including a first stage, a last stage and a number of active stages equal to the number of bits of digital output. Conveniently, the SAR adopts a "One-bits to Right" test implemented by a Manchester Carry Chain in the opposite direction to the shift direction.

Abstract: A driver circuit comprising an output level selection circuit and a shift register is disclosed. The output level selection circuit has driving terminals, potential level input terminals and data input terminals, and an output signal having one of the different potential levels from the driving terminals in response to the data signals. The shift register includes an input terminal, an output terminal, a control terminal, a control circuit, a first shift circuit, and a second shift circuit. The first shift circuit has an input coupled to the input terminal of the shift register and the control circuit, and an output coupled to the control circuit. The second shift circuit has an input coupled to the control circuit and an output coupled to the output terminal of the shift register.

Abstract: A first periodic digital waveform is to be synchronized with a second periodic digital waveform obtained by propagating the first waveform through a delay path (13) having an adjustable propagation delay. In the disclosed approach, the delay of the delay path is increased, even when an edge (43) of the second waveform trails a corresponding edge (45) of the first waveform by less than one-half cycle. The delay continues to be increased until the edge of the second waveform is eventually time-shifted past the next successive corresponding edge (49) of the first waveform.

Abstract: A clock control circuit for sequentially enabling the clock input terminal of a number of groups of shift register stages for reducing the power consumption. The groups are seccessively activated, and the groups currently not in operation are made not to consume power. During changeover between adjacent groups of shift register stages, the clocks for the different groups overlap to insure stable operation.

Abstract: A shift register comprises a plurality of latch circuits for latching time series signals inputted thereto, a multiplexer for selecting outputs of the latch circuits in sequence, and a clock control circuit for generating clocks used for controlling selection timings of the multiplexer, wherein the timing for selecting the output of a certain latch circuit is delayed with respect to the latch timing of the certain latch circuit by a predetermined timing. Accordingly, the number of elements constituting the shift register circuit is decreased and the power consumption is reduced.

Abstract: A system for generating an analog regulating voltage to be supplied to one or more circuit elements on an integrated circuit. The circuit elements have operational characteristics that are voltage dependent and the analog regulating voltage having the a property of changing with temperature, power supply voltage, and manufacturing process variations so as to substantially eliminate the effects of such variations on the operational characteristics of the circuit elements.

Abstract: A select line scanner for a liquid crystal display includes a plurality of cascaded stages each having an input terminal and an output terminal. Each stage includes an output circuit which switches the output terminal between high and low states. A first node switches the output terminal in response to an input signal and a second node keeps the output terminal low between the input pulse and a clocking pulse.

Abstract: A data detector comprises a counter having a plural-bit parallel output, compensation means for compensating a shift of output times of a low order bit and a high order bit of the counter caused by a carry signal from the low order bit to the high order bit, and detection means for detecting data of the low order bit and the high order bit of the counter compensated by the compensation means.

Abstract: A cascaded driver circuit has two or more stages connected to a common serial data signal line and a common clock pulse signal line. Each stage has a counter circuit for dividing the frequency of the clock pulse signal and an enable latch circuit for latching an enable signal, received from the preceding stage, in response to the divided clock pulses. A data latching circuit in each stage latches serial data in response to the clock pulse signal, starting when the enable signal is latched and stopping when a first number of bits of serial data have been latched. An enable output circuit in each stage sends an enable signal to the next stage when the data latching circuit has latched a second number of bits, the second number being at least two less than the first number.

Abstract: An all-optical circulating shift register encodes a received optical clock signal with a value derived from an encoded optical signal received at a control port thereof. A data input to the shift register is used to modify an encoded optical signal. The resulting encoded clock signal, appearing at an output port, is coupled back to the control port. The shift register uses the encoded clock signal at the control port to encode a subsequently-received clock signal. In one embodiment, the optical shift register is implemented using a Sagnac switch having a feedback path coupled between an output port and a control port of the Sagnac switch.

Abstract: A shift register circuit includes a logical operator which is added to an output terminal of a latch portion and takes a logical operation of input and output signals of the latch portion and outputs its result as a bit signal. The signal of a bit component is shifted to a higher order bit every half of the period of a clock signal so that a shifting speed thereof can be made two times faster than that in a conventional shift register circuit. It may be arranged such that a higher order bit section starts to output a signal after the preceding lower order bit section outputs a low level signal thereby enabling to avoid the signals outputted by the bit sections neighboring to each other becoming simultaneously intermediate values between a high level and a low level. Also, the bit sections may be cascade-connected such that each of the sections takes a logical operation of the input and output signals of the latch portion. In view of the configuration involved, the number of elements per bit can be reduced.

Abstract: Disclosed herewith is a shift register for shifting data in series in synchronism with a shift clock signal and is composed of a plurality of data-shift gages connected in cascade, each of which includes a shift-in terminal and a shift-out terminal, and each of which further includes a first transfer gate, a first data hold circuit, a second transfer gate and a second data hold circuit connected in this order between the shift-in and shift-out terminals. Further provided in each of the data-shift stages is a gate circuit, in particular a NOR gate, which responds to logic levels at selected ones of the respective circuit connection points and produces a pulse signal.

Abstract: A digital logic circuit (100) is provided for multiplying, such as doubling, the frequency of an input clock pulse sequence of period T. The circuit in one embodiment includes complementarily clocked first and second chains of cascaded delay elements (12, 13 in A1, A2, A3, . . . and B1, B2, B3, . . . ). Further, the n'th one of set of clocked latches (14, 15, 16 in A2, A4, A6, . . . ) derives its input from the 2n'th one of the delay elements in the first chain, where n is a running integer index (n=1,2,3, . . . ). The circuit (100) also includes a set of two-input logic gates (11), one of whose inputs (IN) is the output (OU) of a separate one of the logic elements (12, 13) in the second chain and the other of whose inputs is an output (MO) of a separate one of the latches (14, 15, 16). Each of the outputs of these logic gates (11) is fed to a multiple input output logic gate (25) whose output has a desired double-frequency feature (edges at T/4) relative to the frequency of the clocked pulse sequence (CLK).

Abstract: In order to compare the total reached by a counter counting pulses from a source with a given number, the more significant digits from the counter are compared with the corresponding digits of the given number. The comparator produces an output when the groups of more significant digits are equal. An adjusted output taking account of the less significant digits of the given number is obtained by delaying the output by a time period equal to that required for the number of pulses from the source to be incremented by the number represented by the less significant digits of the given number. The time delay is provided by a multi-stage shift register using the pulses from the source as shift pulses, the output from the comparator being applied to the first stage and the adjusted output being derived from a stage selected according to the less significant digits of the given number.

Abstract: A circuit for parallel-to-serial or serial-to-parallel conversion uses a multi-stage structure for conversion of long data words section-by-section. Each section of the data word corresponds to length/width of the respective registers or latches of the circuit which are successively controlled by an executive sequencer to process the data word in these smaller sections. The section-by-section conversion provides, for a high data rate, a reduction in clock loading and power dissipation.

Abstract: An integrated circuit apparatus for changing the phase relationship between at least one clock-phase output and a reference clock is disclosed. The sequence control apparatus is coupled to a waveform synthesizer apparatus producing at least one clock-phase output. The clock-phase output from the waveform synthesizer is looped back to a skew control apparatus. The deskew control apparatus measures the skew between the falling edge of the clock-phase output and the rising edge of the reference clock and generates a control signal to a shifter. The shifter deskews the clock-phase output automatically with respect to the reference clock by shifting an input pattern to a digital-to-time domain converter (DTC). A sampling window circuit in the deskew control apparatus is coupled to the shifter for reducing the skew between the reference clock and the clock-phase output to a small, well-defined amount.

Abstract: A shift register circuit comprises a series circuit comprising a plurality of first clocked gate inverters and inverters which are alternately connected in series, where a first one of the first clocked gate inverters is adapted to receive an input pulse signal, an output line connected to an output of each of the inverters for outputting an output pulse signal, and a second clocked gate inverter connected to the output of each of the inverters for outputting an output pulse signal. The first clocked gate inverters operate responsive to a first clock signal, and the second clocked gate inverters operate responsive to a second clock signal which is different from the first clock signal.

Abstract: A sample-hold circuit comprises a large number of sample-hold elements, and a multi-stage shift register for controlling sampling timings of the sample-hold elments, including a large number of stages corresponding to respective sample-hold elements, wherein each of stages of the multi-stage shift register includes an input gate for taking a signal shifted from the preceding stage thereinto, an output gate for shifting the signal taken in by the input gate to the succeeding stage, respective sampling timings of the sample-hold elements corresponding to respective stages being determined by signals taken in between the input and output gates through the input gates at the respective stages. Waveforms of output signals from respective stages for determining the sampling timing are not affected by interstage wiring capacity.

Abstract: A circuit is provided having a plurality of flip flops (F.sub.l -F.sub.n) that are serially connected for executing sequential operations under the control of a clock. The outputs (Q.sub.l -Q.sub.n) of the flip flops (F.sub.l -F.sub.n) are connected to corresponding inputs (I.sub.l -I.sub.n) of a binary decoder and the sequential outputs (O.sub.1 -O.sub.2) of the binary decoder execute the sequential selection. However, when an optional operation is selected during the execution of the sequential selection, a first switch switches the state of the clock terminals of the flip flops to a "high level" so that the flip flops memorize the state of the interrupted sequence selection. Subsequently, the option selection is carried out by the manipulation of a set of switches. Upon completion of the option selection, the first switch is switched back so that the execution of the interrupted sequence selection continues.

Abstract: A transistor (14) having a plurality of sub-transistors (26a-f) includes a voltage controlling device (45). The voltage controlling device induces a current through an elongated gate (24) producing a voltage drop across the elongated gate (24) by providing a path between one end of the gate and ground (32). The voltage drop across the elongated gate (24) sequentially reduces the gate voltage present at each of the sub-transistors (29a-f), thereby reducing the amount of current which the sub-transistors (29a-f) can conduct. The voltage controlling circuit (45) gradually reduces the current through the elongated gate (24), thereby increasing the amount of current through the sub-transistors (29a-f). The time interval over which the conductive device induces a current through the elongated gate (24) can be adjusted by positioning the connection to the gate of a transistor (62) along the elongated gate (24).

Abstract: An automatic reset scheme for a synchronized delay line detects the polarity of the tap signals from a predetermined number of delay stages. If the delay line powers up to lock onto one of the non-fundamental modes of operation, an inverted polarity is detected at the output of one of the selected taps coupled to the reset circuit and an automatic reset is initiated for the delay line.