Abstract: A display device is disclosed by the present disclosure. The display device includes: a display panel having a plurality of sub-pixels, the sub-pixels being connected to a plurality of scan lines and a plurality of data lines; and a gate driver for supplying a scan signal at a high level to the plurality of scan lines. The gate driver may include: a first gate driver for outputting a carry signal at a low level; a second gate driver for outputting the scan signal at the high level based on the carry signal; a first clock signal line connected to the first and the second gate driver; and a second clock signal line connected to the first and the second gate driver. Accordingly, the gate driver can generate a high-level scan signal based on the low-level carry signal from the first gate driver.

Abstract: A GOA circuit and a display panel are provided. The GOA circuit includes a plurality of GOA units connected in series. Each GOA unit includes a pull-up control module, a pull-up module, a download module, a pull-down maintaining module, a pull-down module, and a bootstrap capacitor. An AC signal applied to the pull-up module has high and low voltage levels. The high voltage level of the AC signal could reduce the rising time and the falling time of the conventional clock signal such that the output of the scan signal could be better. The low voltage level of the AC signal could pull down the signal in the blank time to perform a stress recovery such that the threshold voltage shift of the transistor caused by the high voltage level stress is reduced. This could raise the stability and the lifetime of the circuit.

Abstract: Narrowing of a picture-frame of a display device that can perform switching between vertical scanning directions is implemented. A gate driver (21) includes a shift register (211) including a plurality of unit circuits including n unit circuits connected to write control lines; a first scanning order switching circuit (212) including a plurality of first switching circuits respectively corresponding to the plurality of unit circuits; and a second scanning order switching circuit (213) including n second switching circuits connected to initialization control lines. The first scanning order switching circuit (212) controls operation of the shift register (211) based on scanning order instruction signals. Each second switching circuit applies, based on the scanning order instruction signals, an output signal from a unit circuit on a previous stage side or an output signal from a unit circuit on a subsequent stage side, as a second scanning signal, to an initialization control line.

Abstract: A scan driver includes a plurality of stages. A n-th stage among the plurality of stages includes a first input unit controlling a voltage of a first node in response to a previous carry signal, a scan output unit outputting a current scan signal corresponding to a scan clock signal in response to the voltage of the first node, a first switching unit controlling a voltage of a second node in response to the previous carry signal, a sensing output unit outputting a current sensing signal corresponding to a sensing clock signal in response to the voltage of the second node, a carry output unit outputting a current carry signal corresponding to a carry clock signal in response to the voltage of the second node, and a second switching unit controlling the voltage of the second node in response to the sensing clock signal or the carry clock signal.

Abstract: To suppress a malfunction of a circuit due to deterioration in a transistor. In a transistor which continuously outputs signals having certain levels (e.g., L-level signals) in a pixel or a circuit, the direction of current flowing through the transistor is changed (inverted). That is, by changing the level of voltage applied to a first terminal and a second terminal (terminals serving as a source and a drain) every given period, the source and the drain are switched every given period. Specifically, in a portion which successively outputs signals having certain levels (e.g., L-level signals) in a circuit including a transistor, L-level signals having a plurality of different potentials (L-level signals whose potentials are changed every given period) are used as the signals having certain levels.

Abstract: A timing controller includes: a field programmable gate array configured to generate a reference clock signal, and obtain at least one group of clock signals according to the reference clock signal. Each group of clock signals includes at least two clock signals, and a waveform of each clock signal is same as a waveform of the reference clock signal, and active levels in different clock signals are provided with a delay of a preset duration. The reference clock signal includes a first clock sub-signal for first duration and a second clock sub-signal for a second duration. At least one output interface group is connected to the field programmable gate array. Each output interface group includes at least two output interfaces, and each of the at least two output interfaces is configured to output one clock signal of a group of clock signals corresponding to the output interface group.

Abstract: A circuit includes a first transistor whose gate is connected to a set terminal and whose source or drain is connected to an internal node, a second transistor connected such that one of a source and a drain is electrically connected to the internal node and the other one of the source and the drain is electrically connected to a reference voltage source, a third transistor connected such that a gate is connected to the internal node, one of a source and a drain is connected to a clock terminal, and the other one of the source and the drain is connected to a first output terminal, a bootstrap capacitor which is connected to the internal node and the first output terminal, and a stabilization circuit that suppresses a drop in potential at the internal node in a charging period of the bootstrap capacitor.

Abstract: Disclosed is a shift register, a gate driving circuit, a display apparatus and a driving method, the shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a banking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of a first node, wherein the composite output signal includes a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.

Abstract: A shift register unit and a control method thereof, a gate driving circuit and a control method thereof, and a display apparatus are provided. The shift register unit includes: a first shift register coupled to an input signal terminal, a first clock signal terminal and a second clock signal terminal. The first shift register is configured to generate a first output signal based on the signal at the first clock signal terminal and generate a second output signal based on the signal at the second clock signal terminal; and a second shift register coupled to the input signal terminal and a third clock signal terminal, the second shift register is configured to generate a third output signal based on the signal at the third clock signal terminal. The first shift register includes a first control circuit, a first output circuit and a second output circuit.

Abstract: A semiconductor device and a method of operating a semiconductor device are provided. The semiconductor device includes a first latching circuit and a second latching circuit coupled to the first latching circuit. The second latching circuit includes a first feedback circuit and a first transmission circuit, the first feedback circuit configured to receive a first clock signal of a first phase and a second clock signal of a second phase, and the first transmission circuit configured to receive the second clock signal and a third clock signal of a third phase. The first feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the first transmission circuit is turned on by the second clock signal and the third clock signal.

Abstract: A circuit includes a first transistor whose gate is connected to a set terminal and whose source or drain is connected to an internal node, a second transistor connected such that one of a source and a drain is electrically connected to the internal node and the other one of the source and the drain is electrically connected to a reference voltage source, a third transistor connected such that a gate is connected to the internal node, one of a source and a drain is connected to a clock terminal, and the other one of the source and the drain is connected to a first output terminal, a bootstrap capacitor which is connected to the internal node and the first output terminal, and a stabilization circuit that suppresses a drop in potential at the internal node in a charging period of the bootstrap capacitor.

Abstract: A display panel includes an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal.

Abstract: A shift register is provided, which may include a compensation selection circuit, a holding circuit, and N shift register circuits. The hold circuit may hold a blanking input signal. Each of the shift register circuits may include a blanking input circuit and an output circuit. The blanking input circuit may provide a blanking pull-down signal to a first node according to the blanking input signal and a blanking control signal. The output circuit may output a shift signal via a shift signal output terminal and output a first drive signal via a first drive signal output terminal according to a voltage of the first node. The compensation selection circuit may provide, according to a compensation selection control signal and the shift signal from one of the N shift register circuits, the blanking input signal to the holding circuit and the N shift register circuits.

Abstract: A GOA circuit and a display panel are provided. The GOA circuit and the display panel decrease thin film transistors required by an inverter in a circuit structure. A thin film transistor number is decreased, and an area occupied by a GOA space can be effectively decreased, which facilitates decreasing of border sizes of panels. Gates of thin film transistors of the GOA circuit are controlled by clock signals that have not been attenuated, which can prevent failure resulting from an attenuated cascaded signal caused by threshold voltage drifting of thin film transistors.

Abstract: A circuit includes a first transistor whose gate is connected to a set terminal and whose source or drain is connected to an internal node, a second transistor connected such that one of a source and a drain is electrically connected to the internal node and the other one of the source and the drain is electrically connected to a reference voltage source, a third transistor connected such that a gate is connected to the internal node, one of a source and a drain is connected to a clock terminal, and the other one of the source and the drain is connected to a first output terminal, a bootstrap capacitor which is connected to the internal node and the first output terminal, and a stabilization circuit that suppresses a drop in potential at the internal node in a charging period of the bootstrap capacitor.

Abstract: A gate driver includes a first stage, a second stage, a third stage and a fourth stage. The first stage includes a first clock terminal receiving a first clock signal, a second clock terminal receiving a second clock signal, a carry terminal receiving a vertical start signal and an output terminal outputting a first gate output signal. The second stage includes a first clock terminal receiving the second clock signal, a second clock terminal receiving the first clock signal, a carry terminal receiving the vertical start signal and an output terminal outputting a second gate output signal. The third stage includes a first clock terminal receiving the second clock signal, a second clock terminal receiving the first clock signal, a carry terminal receiving the first gate output signal and an output terminal outputting a third gate output signal.

Abstract: In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.

Abstract: The present disclosure provides a shift register unit and a method for driving the same, a gate driving circuit and a display device. The shift register unit includes: an input sub-circuit configured to receive an input control signal and an input signal, and transmit the input signal to a first pull-down node of the shift register unit under control of the input control signal; a first control sub-circuit configured to receive a first clock signal and electrically couple the first pull-down node to a second pull-down node of the shift register unit under control of the first clock signal; and an output sub-circuit configured to receive a first constant voltage signal and transmit the first constant voltage signal to an output terminal of the shift register unit under control of a voltage at the second pull-down node.

Abstract: A gate driving circuit includes a plurality of shift registers coupled in series. An nth shift register includes a driving circuit and a pull-down circuit. The driving circuit is electrically coupled to an output node and a first node. The driving circuit is configured to receive a first clock signal and output a gate signal according to the first clock signal. The pull-down circuit is electrically coupled to the output node. The pull-down circuit is configured to receive an (n?m)th gate signal and an (n+m)th gate signal, and pull-down the gate signal to a low voltage level according to one of the (n?m)th gate signal and the (n+m)th gate signal, wherein m and n are positive integers.

Abstract: A shift register unit and a driving method thereof, a gate drive circuit, and a display device are provided. The shift register unit includes: an input circuit configured to control a potential of a first node; a first output circuit configured to output a carry signal to a first output terminal of the shift register unit through an output terminal of the first output circuit, under control of the potential and a clock signal; a second output circuit configured to output a driving signal to a second output terminal of the shift register unit, under control of the potential and the clock signal; a switching circuit configured to control the output terminal to be electrically connected to the first output terminal in response to a control signal; and a potential control circuit configured to control the output terminal to be electrically connected to a first voltage terminal.

Abstract: A gate driving unit, a gate driving method, a gate driving circuit, a display panel and a display device are provided. The gate driving unit includes a start terminal, a first gate driving signal output terminal, a second gate driving signal output terminal, a pull-up control node control circuit, a pull-up node control circuit, configured to control a potential of a first pull-up node and a potential of a second pull-up node based on the potential of the pull-up control node, a first gate driving signal output circuit, a second gate driving signal output circuit, and a pull-down node control circuit, configured to control and maintain the potential of the pull-down node under the control of a third clock signal and a fourth clock signal, and control to reset the potential of the pull-down node under the control of the potential of the pull-up control node.

Abstract: A gate driving unit, a gate driving method, a gate driving circuit, a display panel and a display device are provided. The gate driving unit includes a start terminal, a first gate driving signal output terminal, a second gate driving signal output terminal, a pull-up control node control circuit, a pull-up node control circuit, configured to control a potential of a first pull-up node and a potential of a second pull-up node based on the potential of the pull-up control node, a first gate driving signal output circuit, a second gate driving signal output circuit, and a pull-down node control circuit, configured to control and maintain the potential of the pull-down node under the control of a third clock signal and a fourth clock signal, and control to reset the potential of the pull-down node under the control of the potential of the pull-up control node.

Abstract: The present application discloses a shift-register circuit used as a shift-register unit of current stage including a control sub-circuit coupled to a shift-register unit of previous stage and configured to recharge a pull-up node of the shift-register unit of previous stage during a touch-control operation performed after a gate line scanning of previous stage ends and before the gate line scanning of current stage starts. The control sub-circuit is further configured to compensate an internal voltage of the shift-register unit of previous stage before the touch-control operation ends so that the shift-register unit of previous stage is triggered to perform the gate line scanning of previous stage followed by the shift-register unit of current stage to perform the gate line scanning of current stage.

Abstract: A driving circuit includes a S stage register, a first connect line, a (S+A) stage register and a second connect line. The S stage register receives a S stage control signal through a first switch unit and a second switch unit, so that the S stage register performs voltage regulation and outputs a S stage scan signal. The first connect line is electrically connected to the first switch unit of the S stage register. A third switch unit of the (S+A) stage register is electrically connected to the first connect line and a fourth switch unit of the (S+A) stage register for receiving the S stage scan signal, so that The (S+A) stage register performs voltage regulation. The second connect line is electrically connected to the second switch unit of the S stage register and the fourth switch unit of the (S+A) stage register.

Abstract: A display driving circuit is provided. The display driving circuit includes a multi-stage driving unit, and each stage of the driving unit includes a pull-up control unit and a pull-up unit. The pull-up unit is electrically connected to a second high voltage signal input terminal, so that high voltage signal input from the second high voltage signal input terminal is directly transmitted to a cascade signal output terminal through the pull-up unit, which further enables the display driving circuit to output a high voltage driving signal while a gate of a thin film transistor inside the display driving circuit is kept at low voltage.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes an input circuit, a first control circuit, a blanking control circuit, a first output circuit, and a second output circuit. The input circuit is configured to control a level of a first node in response to an input signal input; the first control circuit is configured to control a level of the second node in response to the input signal and the level of the first node; the blanking control circuit is configured to control the level of the first node and the level of the second node; the first output circuit is configured to output a first output signal at the first output terminal; and the second output circuit is configured to output a second output signal at the second output terminal.

Abstract: A shift register unit, a driving method thereof, a gate driving circuit, and a display device. The shift register unit comprises an input circuit, a control circuit, a reset circuit, an output circuit and a first capacitor, where the input circuit provides a signal from an input signal terminal to a first node; the control circuit controls signals from the first node and a second node; the reset circuit provides a signal from a reference signal terminal to the first node; the output circuit provides a signal from a clock signal terminal to a signal output terminal, and provides the signal from the reference signal terminal to the signal output terminal; and the first capacitor is coupled between the clock signal terminal and the second node.

Abstract: A gate driving circuit comprises a plurality of shift registers coupled in serial. An nth shift register includes a driving circuit, a pull-up circuit and a first auxiliary voltage regulator circuit. The driving circuit is electrically coupled to an output node and a first node. The driving circuit is configured to receive a clock signal and output a gate signal according to the clock signal. The pull-up circuit is electrically coupled to the driving circuit. The first auxiliary voltage regulator circuit is electrically coupled to the pull-up circuit and a second node. The first auxiliary voltage regulator circuit is configured to receive a control signal and the second node corresponding to a second voltage.

Abstract: A gate driving circuit includes a plurality of stages connected to one another, wherein each of the plurality of stages includes an output unit which outputs a first clock signal as a gate voltage in accordance with a voltage of a Q node and a voltage of a QB node; a first node control unit which controls the voltage of the Q node; and a second node control unit which controls the QB node, wherein the first node control unit includes second and third transistors which discharge the Q node, the second transistor outputs a ground voltage to the Q node in response to a second clock signal, and the third transistor outputs the ground voltage to the Q node in response to the voltage of the QB node.

Abstract: There is provided in the present disclosure a shift register unit, including: an input sub-circuit, whose first terminal is coupled to an input signal terminal, and second terminal is coupled to a pull-up node; an output sub-circuit, whose first terminal is coupled to the pull-up node, second terminal is coupled to a clock signal terminal, and third terminal is coupled to an output terminal, and configured to output a clock signal of the clock signal terminal to the output terminal under the control of a level signal of the pull-up node; a first electro-static discharge sub-circuit, whose first terminal is coupled to the pull-up node, second terminal is coupled to an electro-static discharge control terminal, and third terminal is coupled to a ground, and configured to discharge static electricity accumulated at the pull-up node under the control of a level signal of the electro-static discharge control terminal.

Abstract: A shift register unit, a shift register circuit and a display panel is provided. The shift register unit includes: an input circuit configured to transmit a power signal to the pull-up node; an output circuit configured to transmit a clock signal to the signal output terminal; a reset circuit configured to transmit a reference signal to the pull-up node and the signal output terminal; a first pull-down control circuit configured to transmit the reference signal to the pull-down control node and the pull-down node; a second pull-down control circuit configured to transmit the power signal to the pull-down control node and the pull-down node; and a pull-down circuit configured to transmit the reference signal to the pull-up node and the signal output terminal.

Abstract: The embodiments of the present application provide a shift register, a method for controlling the same, a gate driving circuit, and a display apparatus. The shift register includes: an input circuit coupled to a signal input terminal and a pull-up node; a pull-up circuit coupled to the pull-up node, a first clock signal terminal and a signal output terminal; a pull-down circuit coupled to a reset signal terminal, a first voltage signal terminal, the pull-up node, and the signal output terminal; a pull-down control circuit coupled to a second clock signal terminal, the pull-up node, a pull-down node, and the first voltage signal terminal; a first de-noising circuit coupled to the pull-up node, the signal input terminal, the first voltage signal terminal, and a compensation node; and a compensation circuit coupled to the first clock signal terminal, the second clock signal terminal, and the compensation node.

Abstract: A shift register unit and a method for driving the same, a gate drive circuitry and a display device are provided. The shift register unit includes: an output circuit, coupled to a first signal output terminal and a pull-up control node, and configured to receive a first clock signal and output the first clock signal to the first signal output terminal under control of a potential of the pull-up control node; an output control circuit, coupled to a signal input terminal, the pull-up control node and the first signal output terminal; a clock control circuit configured to receive a first clock signal and at least one additional clock signal and generate a second clock signal using the first clock signal and the at least one additional clock signal; and a transmission circuit coupled to a second signal output terminal and the pull-up control node.

Abstract: The present invention is related to a gate driving circuit. The gate driving circuit may comprise at least two scan modules coupled to a same clock signal. Each of the at least two scan modules may have an input terminal, a reset terminal, and at least one stage of shift register unit. The reset terminal of at least one of the at least two scan modules is coupled to a touch control enable signal line.

Abstract: A shift register unit and a driving method thereof, a gate driving circuit and a display apparatus. The shift register unit includes an input circuit, a first pull-down circuit, a second pull-down circuit, and an output circuit. In a first state, the first pull-down circuit is configured to pull down the level of a pull-up node, and the second pull-down circuit is configured to pull down a level of the output terminal.

Abstract: A GOA circuit uses the high voltage level of a high-frequency clock signal for pulling up the voltage level of a second node during the period of outputting a scan signal, to make the voltage level of the second node be larger than the voltage level of a stage transmitting signal of the (n?4)th stage of GOA unit, thereby to keep the pull-up controlling module in off state during the period of outputting the scan signal, for promoting the stability of the GOA circuit and preventing the GOA circuit from malfunction.

Abstract: The present application discloses to provide a display device capable of displaying an image with a luminance depending on a data signal by controlling pulling of a gate voltage of a driving transistor occurring when a writing period starts and ends and a driving method of the display device. A pixel circuit including a compensation circuit compensating variation of a threshold value of a driving transistor is provided with a boost capacitor including a MOS capacitor between a node connected to a gate terminal of the driving transistor and a scanning line. A current value of a drive current is controlled by the driving transistor by using the pulling of the potential of the node being different between a case that a low level voltage is applied the scanning line connected to the boost capacitor and a case that a high level voltage is applied.

Abstract: Provided are a signal processing circuit and a method for driving the same, a display panel, and a display device. The signal processing circuit includes: an output circuit and a plurality of first input control circuits; each of the input control circuits has a corresponding pulse signal input terminal. All input control circuits and the output circuit are coupled at a first node. Each of the input control circuits may input a first operating voltage supplied from a first power supply terminal to the first node in certain cases. The output circuit may output an active-level voltage supplied from an active-level providing terminal or an inactive-level voltage supplied from an inactive-level providing terminal to the signal output terminal in certain cases.

Abstract: An HVA wiring method based on a GOA circuit is disclosed. A direct-current low voltage input end and a reset signal input end are connected to a first signal providing end, and the first signal providing end is configured to provide a direct-current low voltage signal to the direct-current low voltage input end and to provide a reset signal to the reset signal input end. When the HVA wiring method is used, the GOA circuit in which the reset signal is added can share the existing HVA jigs.

Abstract: The shift register unit includes an input circuit, a first reset circuit, an output circuit, a second reset circuit, and a first pull-down control circuit. The input circuit provides a forward scan control signal to a first node according to an input signal. The first reset circuit provides a reverse scan control signal to the first node according to a reset signal. The output circuit provides a clock signal to a signal output terminal according to the voltage of the first node. The second reset circuit provides a first voltage signal to the first node and the signal output terminal according to the voltage of a second node. The first pull-down control circuit controls the voltage of the second node according to the voltage of the first node.

Abstract: The present disclosure provides a shift register, a driving method of the shift register, an emission driving circuit, and a display device. The shift register includes a first node control module, a second node control module and an output control module. A first low level signal VGL1 provides low level at a first node, and a high level signal provides high level at a second node. The output control module includes a transistor for outputting low level, so that an output terminal outputs a third low level signal. The first low level signal VGL1, the third low level signal VGL3 and a threshold voltage Vth1 of the transistor in the output control module satisfy a relation of VGL3>VGL1+|Vth1|, such that in a phase following the output terminal outputting the high level signal, the output terminal completely outputs the third low level signal.

Abstract: The present invention provides a GOA circuit, which includes, which includes multi-stage GOA circuit repeat unit that are cascade connected, and each stage of the GOA circuit repeat units includes: a first pull-up control module (101), a first pull-down holding module (102), a first pull-down module (106), a first bootstrap capacitor module (103), a first output module (104), a second output module (105), a second pull-up control module (201), a second pull-down holding module (202), a second pull-down module (206), a second bootstrap capacitor module (203), a third output module (204) and a fourth output module (205). The present invention can reduce the number of thin film transistors (TFTs) in the GOA circuit for realizing a narrow-border design as well as reducing power consumption of the GOA circuit.

Abstract: A shift register, a gate driving circuit, a display device and a driving method. The shift register includes: a driving unit, configured to supply a gate line signal to a corresponding pixel unit group; and a compensation circuit provided corresponding to the driving unit; where the compensation circuit is configured to compensate for one or more threshold voltage offsets of one or more transistors in the driving unit.

Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.

Abstract: The invention provides a display panel and a gate driving circuit thereof including multiple stages of gate driving units. Each gate driving unit includes: a first pulling control circuit for outputting a first pulling control signal at a first node; a first pulling circuit for generating a gate driving signal according to the first pulling control signal and a first clock signal; a second pulling control circuit for outputting a second pulling control signal; and a second pulling circuit for pulling levels at the first node and an output terminal of the gate driving signal according to the second pulling control signal. A frequency of the second pulling control signal is lower than a frequency of the first clock signal but higher than a refresh rate of the display panel. The invention can prevent thin film transistor characteristic drift and thereby improve reliability of the gate driving unit.

Abstract: A shift register unit, a gate line driving device includes multiple stages of the shift register units, and a driving method for being applied to the shift register unit; the shift register unit includes: an input module connected between an input terminal and a pull-up node, and configured to charge the pull-up node; an output module connected between the pull-up node, a first clock signal terminal and an output terminal, and configured to output to the output terminal a first clock signal received at the first clock signal terminal; a pull-up node reset module connected between a reset terminal, a pull-down node and the pull-up node, and configured to reset the pull-up node; and an output reset module connected between a second clock signal terminal, the pull-down node and the output terminal, and configured to reset the output terminal.

Abstract: A GOA circuit includes a plurality of cascaded GOA units. An N-th stage GOA unit controls charging of an N-th horizontal scanning line. The N-th stage GOA unit includes a pull-high control unit, a pull-high unit, a pull-down unit, a pull-down sustain unit, and a boast capacitor (Cb). The pull-high unit, the pull-down sustain unit and the boast capacitor (Cb) are connected with a first node (Q(N)) and a gate signal output terminal (G(N)) of the N-th stage GOA unit. The pull-high control unit and the pull-down unit are connected with the first node (Q(N)) of the N-th stage GOA unit. The pull-down sustain unit includes a first TFT (T61), a second TFT (T62), a third TFT (T64), a fourth TFT (T43), and a fifth TFT (T33). Also provided is a liquid crystal display device using the GOA circuit.

Abstract: Disclosed is a GOA driving circuit including multistage cascaded GOA units. A current-stage GOA unit includes a pull-up control module, a pull-up module, a pull-down module, and a pull-down holding module. The pull-down holding module is configured to hold the pull-up control signal and the line-scanning signal of the current-stage GOA unit at a low level according to a second clock signal, during a scan cycle of pixel units not in a current line. The GOA driving circuit simplifies a structure of a GOA driving circuit and is conducive to a narrow-bezel design.

Abstract: The disclosure provides a gate driving circuit, an array substrate and a method for recovering the same. The gate driving circuit comprises: a plurality of cascaded shift registers; a recovering signal line and a first reference signal line, extending along an arrangement direction of the shift registers; and a plurality of recovering units, corresponding to the shift registers respectively. After determining a failed shift register in the gate driving circuit, the recovering unit replaces a signal outputted from the failed shift register with a first reference signal from the first reference signal line and loads the first reference signal to the corresponding gate line for recovering. Thus, compared with a structure of outputting the signal provided by the recovering signal line to the gate line, the gate driving circuit of the disclosure has a less significant attenuation on the signal outputted to the gate line.

Abstract: A gate driver on array (GOA) and a liquid crystal display are disclosed. The GOA circuit includes a plurality of cascaded GOA units and a plurality of pull-down maintaining circuits. The cascaded GOA units are configured for respectively outputting gate driving signals of first level signals to charge corresponding horizontal scanning lines within a display area when being controlled by a plurality of clock signals. Each of the pull-down maintaining circuits corresponds to at least two cascaded GOA units, and each of the pull-down maintaining circuits is configured for maintaining the corresponding at least two cascaded GOA units to output second level signals as the gate driving signals during a non-operation period. As described above, the disclosure can reduce the amount of the pull-down maintaining circuits, so as to decrease the width of the layout of the GOA circuit to meet the need to design a narrow-frame liquid crystal display.