Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.

Abstract: The invention provides a display panel and a gate driving circuit thereof including multiple stages of gate driving units. Each gate driving unit includes: a first pulling control circuit for outputting a first pulling control signal at a first node; a first pulling circuit for generating a gate driving signal according to the first pulling control signal and a first clock signal; a second pulling control circuit for outputting a second pulling control signal; and a second pulling circuit for pulling levels at the first node and an output terminal of the gate driving signal according to the second pulling control signal. A frequency of the second pulling control signal is lower than a frequency of the first clock signal but higher than a refresh rate of the display panel. The invention can prevent thin film transistor characteristic drift and thereby improve reliability of the gate driving unit.

Abstract: A shift register unit, a gate line driving device includes multiple stages of the shift register units, and a driving method for being applied to the shift register unit; the shift register unit includes: an input module connected between an input terminal and a pull-up node, and configured to charge the pull-up node; an output module connected between the pull-up node, a first clock signal terminal and an output terminal, and configured to output to the output terminal a first clock signal received at the first clock signal terminal; a pull-up node reset module connected between a reset terminal, a pull-down node and the pull-up node, and configured to reset the pull-up node; and an output reset module connected between a second clock signal terminal, the pull-down node and the output terminal, and configured to reset the output terminal.

Abstract: A GOA circuit includes a plurality of cascaded GOA units. An N-th stage GOA unit controls charging of an N-th horizontal scanning line. The N-th stage GOA unit includes a pull-high control unit, a pull-high unit, a pull-down unit, a pull-down sustain unit, and a boast capacitor (Cb). The pull-high unit, the pull-down sustain unit and the boast capacitor (Cb) are connected with a first node (Q(N)) and a gate signal output terminal (G(N)) of the N-th stage GOA unit. The pull-high control unit and the pull-down unit are connected with the first node (Q(N)) of the N-th stage GOA unit. The pull-down sustain unit includes a first TFT (T61), a second TFT (T62), a third TFT (T64), a fourth TFT (T43), and a fifth TFT (T33). Also provided is a liquid crystal display device using the GOA circuit.

Abstract: Disclosed is a GOA driving circuit including multistage cascaded GOA units. A current-stage GOA unit includes a pull-up control module, a pull-up module, a pull-down module, and a pull-down holding module. The pull-down holding module is configured to hold the pull-up control signal and the line-scanning signal of the current-stage GOA unit at a low level according to a second clock signal, during a scan cycle of pixel units not in a current line. The GOA driving circuit simplifies a structure of a GOA driving circuit and is conducive to a narrow-bezel design.

Abstract: The disclosure provides a gate driving circuit, an array substrate and a method for recovering the same. The gate driving circuit comprises: a plurality of cascaded shift registers; a recovering signal line and a first reference signal line, extending along an arrangement direction of the shift registers; and a plurality of recovering units, corresponding to the shift registers respectively. After determining a failed shift register in the gate driving circuit, the recovering unit replaces a signal outputted from the failed shift register with a first reference signal from the first reference signal line and loads the first reference signal to the corresponding gate line for recovering. Thus, compared with a structure of outputting the signal provided by the recovering signal line to the gate line, the gate driving circuit of the disclosure has a less significant attenuation on the signal outputted to the gate line.

Abstract: A gate driver on array (GOA) and a liquid crystal display are disclosed. The GOA circuit includes a plurality of cascaded GOA units and a plurality of pull-down maintaining circuits. The cascaded GOA units are configured for respectively outputting gate driving signals of first level signals to charge corresponding horizontal scanning lines within a display area when being controlled by a plurality of clock signals. Each of the pull-down maintaining circuits corresponds to at least two cascaded GOA units, and each of the pull-down maintaining circuits is configured for maintaining the corresponding at least two cascaded GOA units to output second level signals as the gate driving signals during a non-operation period. As described above, the disclosure can reduce the amount of the pull-down maintaining circuits, so as to decrease the width of the layout of the GOA circuit to meet the need to design a narrow-frame liquid crystal display.

Abstract: The present invention provides a GOA circuit driving architecture, which comprises a plurality of data lines providing data signals, a plurality of scanning lines providing scanning signals, a plurality of pixel in array arrangement, each pixel is electrically connected to one of the data lines and one of the scanning lines. Odd stage GOA circuits are sequentially arranged on one side of AA area pixel Even stage GOA circuits are sequentially arranged on one other side of AA area pixel. Each stage of the GOA circuits outputs a gate signal to scan the corresponding scanning line, and each stage of the GOA circuits respectively are connected to a first low-frequency clock signal, a second low-frequency clock signal and a DC low voltage, the odd stage GOA circuits are connected to one of a first high-frequency clock signal and a third high-frequency clock signal, and the even stage of GOA circuits are connected to one of a second high-frequency clock signal and a fourth high-frequency clock signal.

Abstract: A gate driving apparatus and an array substrate using the same are described. The gate driving apparatus comprises a driving circuit for outputting a first gate signal during a signal period wherein the signal period comprises an activated interval and an inactivated interval; a gate signal-processing module for receiving the first gate signal and processing the first gate signal to generate a second gate signal wherein the second gate signal comprises a first amplitude level during the inactivated interval; and a control unit activates the gate signal-processing module in the activated interval or inactivates the gate signal-processing module in the inactivated interval; wherein when the gate signal-processing module is in the activated interval, a first resistance value is formed to adjust the received first gate signal to generate the second gate signal having a second amplitude level, and the second amplitude level is less than the first amplitude level.

Abstract: The present invention is related to a gate driving circuit for a display device. The gate driving circuit may comprise x stages of driving shift register units connected in series. Each of the driving shift register units may comprise an input terminal, an output terminal, and a reset terminal. The input terminal may comprise a first input port and a second input port. A row of pixel units driven by the driving shift register unit of the m-th stage may have the same polarity distribution as a row of pixel units driven by the driving shift register unit of the (m?N)-th stage. N is an integer greater than 1. m is an integer and N+1<m?x.

Abstract: A GOA circuit, a display device, and a driving method of GOA circuit are disclosed. A N-th level GOA unit is configured for charging the N-th level horizontal scanning line (G(N)) within a display area of the display device. The N-th level horizontal scanning line (G(N)) connects to GAS. In response to the GAS, the horizontal scanning lines corresponding to all of the GOA units are in a charging state. In this way, the horizontal scanning lines at each level are connected to the GAS, such that when the GAS are valid, the corresponding horizontal scanning line at each level are in the charging state of in an on-state so as to realize the All Gate On function.

Abstract: The present application discloses a shift register unit circuit including an input port for receiving an input signal, an output port for outputting a gate driving signal, a first clock input port for receiving a first clock signal, a second clock input port for receiving a second clock signal, a pull-up node, a first pull-down node, a second pull-down node, a pull-up control sub-circuit connected to the input port and the pull-up node, a pull-up sub-circuit connected to the first clock input port and the pull-up node, a pull-down control sub-circuit connected to the first clock input port, a pull-down sub-circuit connected to the first pull-down node and the second pull-down node, a reset sub-circuit receiving a reset signal to control the potential level at the second pull-down node, and an initialization sub-circuit configured to receive an enabling signal for pulling-down the potential level at the second pull-down node.

Abstract: The embodiments of the present disclosure provide a shift register, a gate driving circuit and a display apparatus. The shift register comprises an input unit, a first reset unit, a node control unit, a gate-shaping unit, a first output unit and a second output unit. The shift register is configured to change a potential of a scan signal outputted from a driving signal output terminal, so as to produce a scan signal having a gate-shaped waveform.

Abstract: The present disclosure proposes a gate driver on array (GOA) driving circuit and a liquid crystal display. The GOA driving circuit includes cascaded GOA units. An Nth stage GOA unit outputs a gate driving signal to an Nth scan line on a display area. The Nth stage GOA unit includes a pull-up module, a pull-down module, a pull-up controlling module, a pull-down holding module, and a bootstrap capacitance module.

Abstract: A gate driving circuit includes: a pull-up controller applying a carry signal of one of previous stages to a first node in response to the carry signal of the one of the previous stages; a pull-up part outputting a clock signal as an N-th gate output signal; a carry part outputting the clock signal as an N-th carry signal; a first pull-down part pulling down the signal at the first node to a second off voltage; a second pull-down part pulling down the N-th gate output signal to a first off voltage; an inverting part generating an inverting signal based on the clock signal and the second off voltage to output the inverting signal to an inverting node; and a reset part outputting a reset signal to the inverting node.

Abstract: The present disclosure relates to the display technologies, which provides a GOA unit, a GOA circuit, a display driving circuit and a display device, for outputting a gate driving signal and a reset signal of a pixel electrode through a GOA unit, to simplify the display driving circuit. The GOA unit comprises a first node control module, a second node control module, a third node control module, a first output module and a second output module, wherein the first output module outputs the gate driving signal under the control of the node voltage of a first node, the node voltage of a second node and a second input signal inputted at a second input terminal; and the second output module outputs the reset signal of the pixel electrode under the control of the node voltage of the second node, the node voltage of the third node and a third input signal inputted at a third signal input terminal.

Abstract: In a scan driver including a plurality of stages configured to supply scan signals to scan lines, the scan driver includes: an i?1th stage configured to supply an i?1th scan signal to an i?1th scan line while controlling a node Qi?1 (i is a natural number) in response to a first clock signal, a third clock signal, and a control voltage; an ith stage configured to supply an ith scan signal to an ith scan line while controlling a node Qi in response to a second clock signal, a fourth clock signal, and the control voltage; and a controller connected to the i?1th stage and the ith stage, and configured to supply the control voltage.

Abstract: A shift register unit is provided. The shift register unit includes a first input module configured to output a first voltage signal as a pull-up control signal under the control of a first signal, a first reset module configured to reset the pull-up control signal under the control of a first reset signal, a pull-up module configured to output a first clock signal under the control of the pull-up control signal, a pull-down control module configured to output a second clock signal as a pull-down control signal under the control of a second clock signal, a pull-down module configured to pull down a voltage of the pull-up control signal, a first output module, and a second output module.

Abstract: Disclosed is a GOA circuit. By locating the thirteenth thin film transistor (T13) coupled with the tenth thin film transistor (T10) in series and controlled by the Mth clock signal (CK(M)) in the output module (400) of the nth stage GOA unit, as entering signal interrupt and performing touch scan, the output competition of the output ends (G(n)) can be prevented; by locating the twelfth thin film transistor (T12) controlled by the global control signal (Gas) in the output end pull-down module (600), and by setting the composite signal (CS) to be the pulse signal consistent with the touch scan signal as entering signal interrupt and performing touch scan, the twelfth thin film transistors (T12) of the GOA units of all stages can be activated, and the output ends of the GOA units of all stages outputs the composite signal (CS) consistent with the touch scan signal (TP).

Abstract: The present disclosure discloses a scan driving circuit on an array substrate which includes a multi-stage cascade circuit, each stage of the cascade circuit inputs a clock signal corresponding to a current stage, and outputs an current stage scanning signal and a current stage cascade signal, different stages of the cascade circuit are connected with each other via a cascade signal; a plurality of cancellation circuits, each cancellation circuit is corresponding to one stage of the cascade circuit, the cancellation circuit corresponding to the current stage cascade circuit inputs a clock signal corresponding to an adjacent stage cascade circuit, and outputs a cancellation signal to offset a part of the current stage scanning signal outputted from the current stage cascade circuit, so that the scanning signals outputted from two adjacent stages of the cascade circuit are not overlapped. An array substrate is also disclosed in the present disclosure.

Abstract: A display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; an output terminal connected to a gate line of the gate lines; a first transistor connected to a first node, a first clock signal input terminal and the output terminal; a second transistor connected to a second clock signal input terminal, a low-level power voltage and the output terminal; a third transistor connected to a second node, the low-level power voltage and the first node; a fourth transistor connected to a first forward input terminal, the low-level power voltage and the second node; and a fifth transistor connected to a first backward input terminal, the low-level power voltage and the second node.

Abstract: The present invention provides a GOA circuit based on oxide semiconductor thin film transistor, which cannot only prevent the electrical leakage to raise the reliability of the GOA circuit but also avoid the generation of the crossfire current in the non-function period by shorting the gate and the source of the fortieth thin film transistor (T40) in the first pull-down module (400) for avoiding the influence of the constant high voltage level (DCH) to the pull-down holding of the first node by electrically coupling both the gate and the drain of the seventy-fifth thin film transistor (T75) in the pull-down holding module (600) to the first node (Q(N)), and clearing the interference of the residual charge to the GOA circuit by providing the reset module (700) to reset the first node (Q(N)) before generating the each frame to guarantee the normal output of the GOA circuit and the normal display of the image.

Abstract: A driving circuit of a display device includes first to third output signal lines which are continuously arranged, a first transistor that has a source connected to the second output signal line and a drain connected to a first clock signal line, and a second transistor that provides a non-active potential to a gate of the first transistor when a second clock signal becomes the active potential, wherein a circuit that outputs the active potential to the first output signal line and the third output signal line is disposed at an opposite side to a circuit that outputs the active potential to the second output signal line with a display region interposed therebetween, and wherein the gate of the first transistor is connected to the first output signal line and the third output signal line via rectifying circuits.

Abstract: The present invention provides a CMOS GOA circuit. The latch module (3) comprises a NOR gate (Y), and the two input ends of the NOR gate (Y) are respectively inputted with the inverted stage transfer signal (XQ(N)) and the global signal (Gas). When the global signal (Gas) is high voltage level, all the scan driving signals (G(N)) of the respective stages are controlled to be raised up to high voltage levels at the same time, and meanwhile, the NOR gate (Y) is controlled to pull down voltage levels of the stage transfer signals (Q(N)) of the respective stages to clear and reset the stage transfer signals (Q(N)) of the respective stages. In comparison with prior art, an independent reset module is not required.

Abstract: The present invention discloses a shift register unit, employed for providing a gate voltage to a nth pixel of a liquid crystal display, and comprising first to third P-type transistors, and gates of the first, second P-type transistors respectively receive gate voltages of n?2th, n?2th pixels, and first end of the first, second P-type transistors respectively receive first and second input signals, and both second ends of the first and second P-type transistors are coupled to a gate of the third P-type transistor; the gate voltages of the n?2th, n?2th pixels are respectively employed to control on-off of the first and second P-type transistors, and to make the first input signal on-off the third P-type transistor; n is a nature number larger than 2; a first end of the third P-type transistor is coupled to a first clock signal or a second clock signal, and a second end is employed as being a voltage output end to be coupled to the nth pixel.

Abstract: A shift register unit and driving method thereof, a gate driving circuit and a display apparatus are provided. The potential of the pull-up control node is continuously raised by the output signals of multiple stages of shift register circuits. The high level of the pull-up control node can be used to release output noise of the shift register unit, such as to improve the quality of the display apparatus product, and ensures the life and the long time stable operation of the GOA circuit. The shift register unit provided by embodiments of the present disclosure comprises an input module, a pull-up module, a pull-down control module, a pull-up control module and a pull-down module.

Abstract: The present invention relates to a gate driving circuit including a multiple of gate driving units. Each of the gate driving units comprises a pull-up control part, a pull-up part, a transfer part, a key pull-down part, a pull-down holding part and a boost part. In this case, the key pull-down part and the transfer part are configured, respectively, to pull potential on a gete signal output end down to and hold potentials on the control ends of the pull-up part and the transfer part at a potential of the first power supply or the second power supply, and also to pull potential on the output end of the transfer part ransfer signal down to and/or hold at a potential of the second power supply, wherein the potential of the second power supply is lower than that of the first power supply.

Abstract: A gate driving unit, a gate driving circuit, a driving method thereof, and a display device are disclosed. The gate driving unit includes first to eighth transistors, a first capacitor and a second capacitor. The gate driving circuit includes multiple gate driving units arranged along a first direction, of which first timing control signal terminals and second timing control signal terminals of respective stages are electrically connected to a first lead terminal and a second lead terminal respectively. In addition, the gate driving circuit is driven along the first direction or along a second direction in reset periods and shift periods. The display device includes a display region and a frame region surrounding the display region, where a portion of the frame region on at least one side of the display region is provided with a gate driving circuit.

Abstract: A clock generator circuit of a liquid display panel includes a charge sharing switch unit, a first capacitor, a first switch, a second switch, a third switch and a fourth switch. The charge sharing switch unit is configured to receive control signals and accordingly output a first-polarity voltage to the first capacitor. The clock generator circuit is configured to turn on the first switch, the second switch, the third switch and the fourth switch according to a specific sequence thereby outputting a clock signal. An operation method for the aforementioned clock generator circuit is also provided.

Abstract: The disclosure discloses a GOA circuit and a liquid crystal display. The GOA circuit comprises a plurality of GOA units, each sequentially charging the Nth-staged horizontal scanning lines and the (N+1)th-staged horizontal scanning lines in the display region. The GOA unit comprises N-staged pull-up control circuits, (N+1)-staged pull-up control circuits, N-staged pull-up circuits, (N+1)-staged pull-up circuits, N-staged pull-down circuits, (N+1)-staged pull-down circuits, and a pull-down holding circuit. The pull-down holding circuit holds the voltage level of the Nth-staged gate signal point and the Nth-staged horizontal scanning line to the low level after the Nth-staged horizontal scanning line is charged, and holds the voltage level of the (N+1)th-staged gate signal point and the Nth-staged horizontal scanning line to the low level after the (N+1)th-staged horizontal scanning line is charged.

Abstract: The present invention provides a self-compensating gate driving circuit, comprising: a plurality of GOA units which are cascade connected, and a Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit comprises a pull-up controlling part, a pull-up part, a transmission part, a first pull-down part, a bootstrap capacitor part and a pull-down holding part; the pull-up part, the first pull-down part, the bootstrap capacitor part and the pull-down holding circuit are respectively coupled to a Nth gate signal point Q(N) and the Nth horizontal scanning line G(n), and the pull-up controlling part and the transmission part are respectively coupled to the Nth gate signal point Q(N), and the pull-down holding part is inputted with a DC low voltage VSS; the pull-down holding part comprises a first pull-down holding part and a second pull-down holding part to alternately work.

Abstract: The present invention provides a scan driving circuit for oxide semiconductor thin film transistors, a pull-down holding circuit part (600) employed in the scan driving circuit for the oxide semiconductor thin film transistors comprises a main inverter and an auxiliary inverter. By introducing a constant low voltage level (DCL) and setting the constant low voltage level (DCL)<the second negative voltage level (VSS2)<the first negative voltage level (VSS1), the influence of electrical property of the oxide semiconductor thin film transistors to the scan driving circuit, particularly the bad function due to the electric leakage issue, can be prevented to ensure that the pull-down holding circuit part (600) can be normally pulled down in the functioning period and at higher voltage level in a non-functioning period to effectively maintain the first node (Q(N)) and the output end (G(N)) at low voltage level.

Abstract: To reduce a variation in the electrical characteristics of a transistor. A potential generated by a voltage converter circuit is applied to a back gate of a transistor included in a voltage conversion block. Since the back gate of the transistor is not in a floating state, a current flowing through the back channel can be controlled so as to reduce a variation in the electrical characteristics of the transistor. Further, a transistor with low off-state current is used as the transistor included in the voltage conversion block, whereby storage of the output potential is controlled.

Abstract: The present invention provides a self-compensating gate driving circuit, comprising: a plurality of GOA units which are cascade connected, and a Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit comprises a pull-up controlling part, a pull-up part, a transmission part, a first pull-down part, a bootstrap capacitor part and a pull-down holding part; the pull-up part, the first pull-down part, the bootstrap capacitor part and the pull-down holding circuit are respectively coupled to a Nth gate signal point Q(N) and the Nth horizontal scanning line G(n), and the pull-up controlling part and the transmission part are respectively coupled to the Nth gate signal point Q(N), and the pull-down holding part is inputted with a DC low voltage VSS.

Abstract: The present invention provides a gate driver circuit basing on IGZO process, comprising GOAs in cascade connection comprising a Nth-stage GOA, wherein the Nth-stage GOA further comprising a pull-up control part 100, a pull-up part 200, a transfer part 300, a pull-down part 400, a pull-down holding part 500, a boost part 600, a first negative supply VSS1, a second negative supply VSS2, a third negative supply VSS3, which are three gradually decreasing negative supplies and pull down an output terminal G(N), a first node Q(N), a second node P(N), and a driving single ST(N) to prevent the electrical leakage of TFTs effectively. And channels of the TFT switches of the gate driver circuit basing on the IGZO process are oxide semiconductor channels.

Abstract: A display panel includes a substrate, a plurality of pixels, a plurality of scan lines, a pull-down control circuit, and a gate driving circuit. The pixels are disposed on a display area of the substrate. The scan lines are disposed on the substrate and respectively coupled to the corresponding pixels. The pull-down control circuit is disposed on a peripheral area of the substrate, receives a plurality of clock signals, and has a plurality of pull-down units to provide a plurality of pull-down signals. The gate driving circuit is disposed on the peripheral area and has a plurality of shift registers. The shift registers are coupled to the scan lines to provide a plurality of gate driving signals and pull down the gate driving signals in sequence according to the pull-down signals. The pull-down control circuit and the gate driving circuit are arranged along a side of the display area.

Abstract: A gate driving circuit is disclosed. The gate driving circuit includes m stages of shift registers, where each stage of shift register includes a first reset terminal, a first input terminal, and an output terminal. A first input terminal of the first stage of shift register is configured to receive an initial signal, and a first reset terminal of the first stage of shift register is configured to receive a reset signal. In addition, first reset terminals of the second to i-th stages of shift registers are configured to receive first signals, where a first reset terminal of each stage of shift register is electrically connected to an output terminal of the previous stage of shift register to receive an output signal from the previous stage of shift register, such that the output signal from the previous stage of shift register causes the next stage of shift register to reset.

Abstract: The present invention provides a GOA circuit based on LTPS semiconductor TFT, comprising a plurality of GOA units which are cascade connected, and N is set to be a positive integer and an Nth GOA unit comprises a pull-up control part (100), a pull-up part (200), a first pull-down part (400), a pull-down holding part (500) and a transfer part (600); the pull-down holding part (500) utilizes a high/low voltage reverse design and comprises a first, a second and a third DC constant low voltage levels (VSS1, VSS2, VSS3) which are sequentially abated and a DC constant high voltage level (H), the influence of electrical property of the LTPS semiconductor TFT to the GOA driving circuit, and particularly the bad function due to the electric leakage issue can be solved; meanwhile, the existing issue that the second node voltage level the pull-down holding circuit part in the GOA circuit based on the LTPS semiconductor TFT cannot be at higher voltage level in the functioning period can be solved to effectively maintain

Abstract: A shift register is disclosed which includes, at respective stages, unit circuits (11) each including (i) a flip-flop (11a) including first and second CMOS circuits and (ii) a signal generation circuit (11b) for generating an output signal (SROUTk) for the current stage with use of an output (Q, QB) of the flip-flop (11a), the shift register including a floating control circuit (11c) between a gate terminal of an output transistor (Tr7) of the signal generation circuit (11b) and a Q terminal. This makes it possible to reduce a circuit scale of a display driving circuit without causing a shift register to malfunction.

Abstract: A gate on array driver unit, a gate on array driver circuit, and a display device. The gate on array driver unit comprises an input sampling unit, an output unit, a reset unit, and a storage capacitor. The storage capacitor is connected at a first end thereof to a gate electrode driving signal output end of the present stage. The input sampling unit is connected to a second end of the storage capacitor, and, under the control of a gate electrode driving signal of a previous stage of the gate on array driver unit, precharges the storage capacitor and allows the gate driving signal of the present stage to sample the input signal. The output unit is connected to the second end of the storage capacitor, and, when the input sampling unit completes the precharging of the storage capacitor, controls the output of the gate electrode driving signal of the present stage.

Abstract: The present invention relates to a GOA circuit for liquid crystal displaying and a display device. The GOA circuit includes a plurality of cascaded GOA units and the nth-stage GOA unit includes a pull-up part (100), a key pull-down part (200), a pull-down holding part (300), a pull-up control part (400), and a boost capacitor (Cb). In operation, a nth-stage clock signal (CK(n)) and first and second clock signals (LC1 and LC2) are inputted. The frequencies of the first clock signal (LC1) and the second clock signal (LC2) are lower than the nth clock signal (CK(n)). The first clock signal (LC1) charging a first circuit point (P) and the second clock signal (LC2) charging a second circuit point (K) are alternately carried out. The present invention also provides a corresponding display device.

Abstract: The invention provides a semiconductor device and a shift register, in which low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire. One of a source and a drain of the third transistor is connected to a second wire, the other of the source and the drain thereof is connected to the gate electrode of the second transistor, and a gate electrode thereof is connected to a fourth wire.

Abstract: The present invention provides a gate driver on array (GOA) circuit and a display panel with the GOA circuit. The driver circuit includes multiple stages of gate driver units and multiple stages of supplementary gate driver units connected in cascade, in which the nth stage gate driver unit includes a driving unit (42) and a pull-down unit (44) and the mth stage supplementary gate driver unit includes a supplementary driving unit (52) and a supplementary pull-down unit (54).

Abstract: An array substrate row driving unit, an array substrate row driving circuit and a display device. The array substrate row driving unit comprises an emission control module (12) and an gate driving module (11) for generating an gate driving signal. The emission control module (12), connected to the output for the gate driving signal of the gate driving module (11), for generating an emission control signal for controlling the switching of OLED under control of the gate driving signal. The gate driving signal having an opposite phase to that of the emission control signal.

Abstract: A shift register includes a signal input unit for receiving and providing an input signal, a signal output unit for controlling whether outputting a clock signal according to the input signal provided by the signal input unit, and a plurality of stable modules. Each of the stable modules is electrically coupled to an output terminal of the signal input unit, an output terminal of the signal output unit, and a default potential. Each of the stable modules receives a corresponding operation signal and is enabled in a duty of the corresponding operation signal, such that both the output terminal of the signal input unit and the output terminal of the signal output unit are electrically coupled to the default potential when the input signal is disabled. Before one of the stable modules is disabled, another of the stable modules has already been enabled.

Abstract: To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

Abstract: An LCD and a bidirectional shift register device thereof are provided. The bidirectional shift register device of the invention is disposed on the substrate of the panel and includes multi-stages shift registers in series connection. Each stage shift register includes a pre-charging unit, a pull-up unit and a pull-down unit, in which the pre-charging unit receives a first preset clock signal and the output from a (i?1)th stage shift register or a (i+1)th stage shift register so as to thereby output a charging signal. The pull-up unit receives the charging signal and a second preset clock signal so as to thereby output a scan signal. The pull-down unit receives the second preset clock signal, a third preset clock signal and the output from the (i+2)th stage shift register or the (i?2)th stage shift register so as to decide whether or not pulling down the scan signal to a reference level.

Abstract: A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

Abstract: A shift register unit comprises: a first transistor, a pulling-up close unit, a pulling-up start unit, a first pulling-up unit, a second pulling-up unit, a trigger unit, and an output unit. A shift register circuit, an array substrate and a display device are also provided. The shift register unit, the shift register circuit, the array substrate and the display device can reduce drift of a gate threshold voltage of a gate line driving transistor and improve operation stability of devices.

Abstract: An output thin film transistor threshold voltage offset compensation circuit, a GOA circuit, and a display. The circuit includes: a first capacitor, comprising a first electrode and a second electrode, the first electrode being connected to the gate of an output thin film transistor and receiving a charge signal, the second electrode being connected to the drain of the output thin film transistor, the first capacitor being used for, under the action of the charge signal, making the first electrode and the second electrode have a same voltage, so that a voltage difference between the drain and the source of the output thin film transistor is equal to a threshold voltage thereof; a first switch unit, connected to the drain and the source of the output thin film transistor, and opening under the action of a first clock signal, so that a voltage difference between the gate and the source of the output thin film transistor is equal to the threshold voltage thereof.