With Pretreatment Of Substrate Patents (Class 427/97.8)
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Patent number: 12028990Abstract: Provided are a multilayer board and a method for manufacturing same, in which a different kind of metal layer is formed between an upper metal layer and an interlayer insulating layer, the different kind of metal layer being formed only in a wiring area without being formed in a via area. The multilayer board comprises: a substrate layer; a plurality of first metal layers sequentially stacked on the substrate layer; an interlayer insulating layer formed between two different first metal layers, having a first via hole, and electrically connecting the two different first metal layers through a third metal layer formed in the first via hole; and a second metal layer formed between the upper layer of the two different first metal layers and the interlayer insulating layer.Type: GrantFiled: July 9, 2021Date of Patent: July 2, 2024Assignee: STEMCO CO., LTD.Inventors: Sung Jin Lee, Young Jun Kim, Su Jeong Shin
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Patent number: 11824205Abstract: A method of refurbishing a singulated fuel cell stack interconnect includes scanning a first pulsed laser beam on an air side of the interconnect to vaporize seal and corrosion barrier layer residue without vaporizing a metal oxide layer located on the air side of the interconnect below the corrosion barrier layer residue, and scanning a second pulsed laser beam which is different from the first pulsed laser beam on the exposed metal oxide layer on the air side of the interconnect to reflow the metal oxide layer without removing the metal oxide layer.Type: GrantFiled: January 18, 2021Date of Patent: November 21, 2023Assignee: BLOOM ENERGY CORPORATIONInventors: Drew Paran, Ali Delkaninia, Kendall Lui, Tulin Akin
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Patent number: 11557490Abstract: A method for producing a metal-ceramic substrate with electrically conductive vias includes: attaching a first metal layer in a planar manner to a first surface side of a ceramic layer; after attaching the first metal layer, introducing a copper hydroxide or copper acetate brine into holes in the ceramic layer delimiting a via, to form an assembly; converting the copper hydroxide or copper acetate brine into copper oxide; subjecting the assembly to a high-temperature step above 500° C. in which the copper oxide forms a copper body in the holes; and after converting the copper hydroxide or copper acetate brine into the copper oxide, attaching a second metal layer in a planar manner to a second surface side of the ceramic layer opposite the first surface side. The copper body produces an electrically conductive connection between the first and the second metal layers.Type: GrantFiled: September 1, 2020Date of Patent: January 17, 2023Assignee: Infineon Technologies AGInventor: Alexander Roth
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Patent number: 9149952Abstract: Described herein are bioprinters comprising: one or more printer heads, wherein a printer head comprises a means for receiving and holding at least one cartridge, and wherein said cartridge comprises contents selected from one or more of: bio-ink and support material; a means for calibrating the position of at least one cartridge; and a means for dispensing the contents of at least one cartridge. Further described herein are methods for fabricating a tissue construct, comprising: a computer module receiving input of a visual representation of a desired tissue construct; a computer module generating a series of commands, wherein the commands are based on the visual representation and are readable by a bioprinter; a computer module providing the series of commands to a bioprinter; and the bioprinter depositing bio-ink and support material according to the commands to form a construct with a defined geometry.Type: GrantFiled: September 27, 2011Date of Patent: October 6, 2015Assignee: ORGANOVO, INC.Inventors: Keith Murphy, Scott Dorfman, Nathan Smith, Larry Bauwens, Ian Sohn, Tim McDonald, Chris Leigh-Lancaster, Richard Jin Law
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Patent number: 8962085Abstract: Disclosed are pre-wetting apparatus designs and methods. These apparatus designs and methods are used to pre-wet a wafer prior to plating a metal on the surface of the wafer. Disclosed compositions of the pre-wetting fluid prevent corrosion of a seed layer on the wafer and also improve the filling rates of features on the wafer.Type: GrantFiled: January 8, 2010Date of Patent: February 24, 2015Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, David W. Porter, Mark J. Willey
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Patent number: 8952259Abstract: The invention relates to a method for producing a ceramic component, a ceramic component, and a component assembly having a ceramic component and a connection component. The method according to the invention for producing a ceramic component (1) comprises the steps: a) providing a ceramic substrate (2), wherein a conducting path (3) is arranged in the interior and/or on the surface of the ceramic substrate (2), and at least some regions of the ceramic substrate (2) are covered by a glaze (5); b) creating a contacting opening (6) in the glaze (5) in a region of a contact region (15) of the conducting path (3) to be contacted; c) applying a metallic layer (7) in the region of the contacting opening (6) for contacting the conducting path (3) in the contact region (15).Type: GrantFiled: September 1, 2010Date of Patent: February 10, 2015Assignee: Robert Bosch GmbHInventors: Oliver Gradtke, Walter Roethlingshoefer, Paul Wickett
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Publication number: 20150008019Abstract: A wiring board includes a variable wettability layer situated on a top surface of a support board and containing a material of which a critical surface tension changes by energy given thereto. A conductive layer is situated inside a concave portion formed in the variable wettability layer. The concave portion has opposite side walls formed in tapered surfaces inclining so that a distance between the side walls is reduced toward a bottom of the concave portion in a cross-sectional shape taken along a plane perpendicular to a conducting direction of the conductive layer. Upper edges of the side walls are formed in gently curved surfaces.Type: ApplicationFiled: June 30, 2014Publication date: January 8, 2015Applicant: RICOH COMPANY, LTD.Inventors: Hiroshi MIURA, Koei SUZUKI, Atsushi ONODERA, Takanori TANO
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Patent number: 8916232Abstract: The embodiments fill the need of improving electromigration and reducing stress-induced voids of copper interconnect by enabling deposition of a thin and conformal barrier layer, and a copper layer in the copper interconnect. The adhesion between the barrier layer and the copper layer can be improved by making the barrier layer metal-rich prior copper deposition and by limiting the amount of oxygen the barrier layer is exposed prior to copper deposition. Alternatively, a functionalization layer can be deposited over the barrier layer to enable the copper layer being deposit in the copper interconnect with good adhesion between the barrier layer and the copper layer. An exemplary method of preparing a substrate surface of a substrate to deposit a functionalization layer over a metallic barrier layer of a copper interconnect to assist deposition of a copper layer in the copper interconnect in an integrated system in order to improve electromigration performance of the copper interconnect is provided.Type: GrantFiled: December 13, 2006Date of Patent: December 23, 2014Assignee: Lam Research CorporationInventors: Hyungsuk Alexander Yoon, John Boyd, Yezdi Dordi, Fritz C. Redeker
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Publication number: 20140262442Abstract: A module includes a circuit board, a resin layer, an external connection conductor, a solder bump. The resin layer is disposed on a first principal surface of the circuit board. The external connection conductor is arranged in the resin layer, has a first end connected to the circuit board and a second end protruding through the surface of the resin layer and includes a projection extending along the surface of the resin layer in a portion that protrudes through the surface of the resin layer. The solder bump is disposed on the second end of the external connection conductor.Type: ApplicationFiled: February 14, 2014Publication date: September 18, 2014Applicant: Murata Manufacturing Co., Ltd.Inventors: Tadashi Nomura, Yoichi Takagi, Nobuaki Ogawa, Akihiko Kamada
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Publication number: 20140166345Abstract: A transparent conducting glass includes a glass substrate and a conducting glue. The glass substrate includes a first surface and a second surface opposite to the first surface, and defines a number of strip recesses on the first surface according to a circuit route. The conducting glue is infilled into the strip recesses and forms a circuit for transmitting signals.Type: ApplicationFiled: February 20, 2013Publication date: June 19, 2014Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventor: SEI-PING LOUH
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Patent number: 8647577Abstract: The described embodiments may provide a method of fabricating a chemical detection device. The method may comprise forming a microwell above a CMOS device. The microwell may comprise a bottom surface and sidewalls. The method may further comprise applying a first chemical to be selectively attached to the bottom surface of the microwell, forming a metal oxide layer on the sidewalls of the microwell, and applying a second chemical to be selectively attached to the sidewalls of the microwell. The second chemical may lack an affinity to the first chemical.Type: GrantFiled: October 10, 2012Date of Patent: February 11, 2014Assignee: Life Technologies CorporationInventors: Wolfgang Hinz, John Matthew Mauro, Shifeng Li, James Bustillo
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Publication number: 20130319734Abstract: Disclosed herein is a package substrate including: a base substrate; insulation layers formed on upper and lower portions of the base substrate; a first metal layer formed on an upper portion of the insulation layer; a first through-via penetrating through the base substrate, the insulation layer, and the first metal layer and being made of an insulating material; a seed layer formed on upper and lower portions and an inner wall of the first through-via; a second metal layer formed on upper portions of the first metal layer and the seed layer; and a second through-via formed in the seed layer formed at the inner wall of the first through-via and the second metal layer.Type: ApplicationFiled: August 27, 2012Publication date: December 5, 2013Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Sang Hyun Shin, Kwang Jik Lee, Hye Sook Shin, Joon Seok Kang
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Publication number: 20130216699Abstract: Disclosed is a metal paste filling apparatus that fills the metal paste in a non-through hole of a substrate conveniently and efficiently without producing a void. The metal paste filling apparatus includes a pad, an exhaust unit, a metal paste supply unit, and a controller. One or more exhaust ports and one or more inlet ports are formed in the acting surface of the pad. The exhaust unit includes a vacuum apparatus connected to a gas flow path in the pad through an exhaust tube, and a direction switching valve installed in the way of the exhaust tube. The metal paste supply unit includes a syringe unit connected to a paste flow path in the pad. The syringe unit includes a paste container, a compressed air supply source, a suck-back valve, and a regulator.Type: ApplicationFiled: February 14, 2013Publication date: August 22, 2013Applicant: TOKYO ELECTRON LIMITEDInventor: Tokyo Electron Limited
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Publication number: 20130209672Abstract: A method for manufacturing a component having a through-connection. The method includes providing a semiconductor substrate, forming a recess in the semiconductor substrate, and introducing into the recess a pourable starting material which has a metal. The method furthermore includes carrying out a heating process, an electrically conductive structure forming the through-connection being developed from the pourable starting material.Type: ApplicationFiled: February 8, 2013Publication date: August 15, 2013Inventors: Jochen REINMUTH, Frank SCHNELL, Heribert WEBER, Erhard HIRTH, Yvonne BERGMANN
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Publication number: 20130149437Abstract: Disclosed herein is a method for manufacturing a printed circuit board. According to a preferred embodiment of the present invention, there is provided a method for manufacturing a printed circuit board, including: preparing a base substrate; forming a carrier layer on the base substrate; forming a through via hole penetrating the carrier layer and the base substrate; forming a plating layer on the carrier layer and an inner wall of the through via hole; filling the through via hole with a conductive paste; removing a portion of the plating layer formed on the carrier layer; removing the carrier layer; and forming a circuit layer on the base substrate.Type: ApplicationFiled: February 22, 2012Publication date: June 13, 2013Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Kyung Seob Oh, Young Do Kweon, Jin Gu Kim, Hyung Jin Jeon
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Publication number: 20130089658Abstract: There is provided a laser processing method of forming via holes 23 and 24 by removing processed layers including a flexible insulating base member 1, in which conformal masks 7 and 8a are provided on the surface, and an adhesive layer 12 having a higher absorbance in a wavelength area of processing laser and a lower decomposition temperature than the insulating base member 1, the method including radiating one shot of pulse light having a first energy density that can remove the insulating base member 1 by one shot without causing the deformation and penetration of a conducting film 2A, and subsequently radiating pulse light having a second energy density that is lower than the first energy density and can remove the rest of the processed layers by a predetermined number of shots without causing the deformation and penetration of the conducting film 2A.Type: ApplicationFiled: February 1, 2011Publication date: April 11, 2013Applicant: NIPPON MEKTRON LTD.Inventors: Fumihiko Matsuda, Yoshihiko Narisawa
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Publication number: 20130081861Abstract: A printed circuit board of the present invention includes a base body, a through-hole that penetrates through the base body in the thickness direction, and a through-hole conductor that covers an inner wall of the through-hole. The base body has a fiber layer including a plurality of glass fibers and a resin that covers the plurality of glass fibers. The glass fibers have a groove-shaped concavity on a surface exposed to the inner wall of the through-hole. The concavity is filled with a part of the through-hole conductor.Type: ApplicationFiled: September 26, 2012Publication date: April 4, 2013Applicant: KYOCERA SLC TECHNOLOGIES CORPORATIONInventor: KYOCERA SLC Technologies Corporation
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Patent number: 8377506Abstract: A substrate structure is provided. The substrate structure includes a substrate, a first insulation layer, a conductive part, a second insulation layer, a seed layer and a conductive layer. The substrate has a first circuit pattern layer and a second circuit pattern layer, which are located on two opposite surfaces of the substrate respectively. The first insulation layer formed on the first circuit pattern layer has a first insulation hole, which exposes a first opening in the outer surface of the first insulation layer. The conductive part formed on the first insulation hole for electrically connecting with a chip is enclosed by the edge of the first opening. The second insulation layer formed on the second circuit pattern layer has a second insulation hole in which the seed layer is formed. The conductive layer is formed on the seed layer for electrically connecting with a circuit board.Type: GrantFiled: October 6, 2009Date of Patent: February 19, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Chih-Cheng Lee
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Publication number: 20130008700Abstract: On a printed wiring board obtained by a method of manufacturing a printed board, a predetermined component is to be mounted on at least one of a front surface side and a back surface side. The manufacturing method includes preparing a CFRP core, forming a through hole so as to penetrate the CFRP core from the front surface side to the back surface side and include a region in which the component is to be mounted when viewed in a plan view, and embedding a GFRP core having insulating properties within the through hole by filling the through hole with a resin having insulating properties and curing the resin. According to the manufacturing method, the component mounted on the printed board is not affected by a stray capacitance due to a CFRP, and it is not difficult to form a circuit.Type: ApplicationFiled: February 23, 2011Publication date: January 10, 2013Applicants: NIPPON AVIONICS, CO., LTD., Mitsubishi Electric CorporationInventors: Hiroyuki Osuga, Sohei Samejima, Kazuhito Sakurada, Akira Yagasaki, Tatsuya Hinata
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Publication number: 20120301630Abstract: A method for forming a flexible printed circuit board is provided. First, an insulating substrate with a first side and a second side is provided. Second, a through hole connecting the first side and the second side is formed in the insulating substrate. Then, a printing step is carried out to print a conductive precursor which is on the first side and cover and fill the through hole. Later, the conductive precursor is cured to form a conductive composition and to simultaneously form a circuit to obtain a flexible printed circuit board. The conductive composition includes at least one of carbon and silver.Type: ApplicationFiled: September 22, 2011Publication date: November 29, 2012Inventor: Chin-Chun Huang
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Publication number: 20120246925Abstract: A method for manufacturing a printed wiring board includes preparing a core substrate having a first surface and a second surface on the opposite side of the first surface, forming on the first-surface side of the substrate a first opening portion tapering from the first toward second surface, forming on the second-surface side of the substrate a second opening portion tapering from the second toward first surface, forming a third opening portion such that a penetrating hole formed of the first opening portion, the second opening portion and the third opening portion connecting the first and second opening portions is formed in the substrate, forming a first conductor on the first surface of the substrate, forming a second conductor on the second surface of the substrate, and filling a conductive material in the penetrating hole such that a through-hole conductor connecting the first and second conductors is formed.Type: ApplicationFiled: March 26, 2012Publication date: October 4, 2012Applicant: IBIDEN CO., LTD.Inventors: Toshiaki Hibino, Takema Adachi
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Publication number: 20120234583Abstract: The invention relates to a method for producing a ceramic component, a ceramic component, and a component assembly having a ceramic component and a connection component. The method according to the invention for producing a ceramic component (1) comprises the steps: a) providing a ceramic substrate (2), wherein a conducting path (3) is arranged in the interior and/or on the surface of the ceramic substrate (2), and at least some regions of the ceramic substrate (2) are covered by a glaze (5); b) creating a contacting opening (6) in the glaze (5) in a region of a contact region (15) of the conducting path (3) to be contacted; c) applying a metallic layer (7) in the region of the contacting opening (6) for contacting the conducting path (3) in the contact region (15).Type: ApplicationFiled: September 1, 2010Publication date: September 20, 2012Applicant: ROBERT BOSCH GMBHInventors: Oliver Gradtke, Walter Roethlingshoefer, Paul Wickett
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Publication number: 20120213944Abstract: A method for manufacturing a printed wiring board including forming a penetrating hole in a core substrate, forming a first conductor on a first surface of the substrate, forming a second conductor on a second surface of the substrate, and filling a conductive material in the hole such that a through-hole conductor is formed in the hole and the first and second conductors are connected via the through-hole conductor. The forming of the hole includes forming a first opening in the first surface, forming a second opening from the bottom of the first opening toward the second surface such that the second opening has a smaller diameter than the first opening, forming a third opening in the second surface, and forming a fourth opening from the bottom of the third opening toward the first surface such that the fourth opening has a smaller diameter than the third opening.Type: ApplicationFiled: December 14, 2011Publication date: August 23, 2012Applicant: IBIDEN CO., LTD.Inventors: Tsutomu YAMAUCHI, Satoru Kawai
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Patent number: 8196298Abstract: Disclosed is a method for manufacturing an electroconductive material-filled throughhole substrate that is free from any void part in the electroconductive material filled into the throughholes. The method comprises forming an electroconductive base layer on one side of a core substrate having throughholes, and precipitating and growing an electroconductive material from one direction within the throughholes by electroplating using the electroconductive base layer as a seed layer to fill the electroconductive material into the throughholes without forming any void part and thus to manufacture an electroconductive material-filled throughhole substrate.Type: GrantFiled: October 13, 2010Date of Patent: June 12, 2012Assignee: Dai Nippon Printing Co., Ltd.Inventors: Shigeki Chujo, Koichi Nakayama
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Publication number: 20120138336Abstract: Disclosed herein is a printed circuit board and a method of manufacturing the same, in which a circuit pattern one end of which is embedded in a trench and the other end of which protrudes from an insulating layer is formed, so that the circuit pattern is not easily separated from the insulating layer and the separation problems of the circuit pattern due to undercutting are solved. Also, the adhesion between the insulating layer and the circuit pattern is enhanced, more stably forming a fine circuit pattern. Even when a plating resist is formed thin, it is possible to form the circuit pattern, resulting in a high-solution circuit pattern.Type: ApplicationFiled: April 20, 2011Publication date: June 7, 2012Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Ryoichi WATANABE, Going Sik KIM, Chang Sup RYU
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Patent number: 8182864Abstract: The present invention provides a method for modification of microchannels of a polydimethylsiloxane (PDMS) microchip, which includes the steps of: a) mixing an alkoxysilane precursor, an alkyl alkoxysilane precursor, and a solvent to prepare a sol-gel solution; b) oxidizing microchannels of the PDMS microchip; and c) coating the oxidized microchannels with the sol-gel solution prepared in step a). The PDMS microchip modified according to the method of the present invention shows higher hydrophilicity than an unmodified PDMS microchip. And, when the modified PDMS channels are filled with an organic solvent, channel swelling can be reduced, and thus various organic solvents can be used for the modified PDMS microchip compared to an unmodified PDMS microchip. Further, it can be widely applied for various fields because absorptivity of non-polar substances can be reduced.Type: GrantFiled: August 13, 2008Date of Patent: May 22, 2012Assignees: Postech Academy-Industry Foundaction, POSCOInventors: Jong-Hoon Hahn, Jin Hee Park, Miok Shin
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Patent number: 8065798Abstract: A fabrication method which can improve electrical properties, shorten processing time, and reduce the thickness of a chip package by achieving an ultra-thin fine circuit pattern. The method for fabricating a printed circuit board includes: providing an insulating material; forming in the insulating material at least one via-hole for interlayer electrical connection; ion beam treating the surface of the insulating material having the via-hole formed therein; forming a copper seed layer on the surface-treated insulating material using a vacuum deposition process; and plating a copper pattern on the copper seed layer to form a circuit pattern.Type: GrantFiled: July 22, 2010Date of Patent: November 29, 2011Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Dong Sun Kim, Taehoon Kim, Jong Seok Song, Sam Jin Her, Jun Heyoung Park
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Publication number: 20110095419Abstract: There is provided a conductive film. The conductive film includes: an anodized layer having a plurality of through holes extending therethrough in its thickness direction; a plurality of linear conductors each formed in a corresponding one of the through holes and each having first and second protrusions protruding from the anodized layer, wherein at least one of the first and second protrusions is covered by a coating material; and an uncured thermosetting resin layer formed on the anodized layer to cover at least one of the first and second protrusions.Type: ApplicationFiled: October 21, 2010Publication date: April 28, 2011Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda, Tsuyoshi Kobayashi, Tatsuaki Denda
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Patent number: 7921799Abstract: A pattern forming apparatus comprises a surface treatment system and an ink jet system 14, where a solvent is sprayed from a solvent spray nozzle of the surface treatment system to surface of a glass substrate where a bus line pattern groove is formed. The ink is discharged from an ink discharge nozzle of the ink jet system into the groove of bus line pattern on a glass substrate, and a bus line pattern is formed.Type: GrantFiled: May 31, 2006Date of Patent: April 12, 2011Assignee: Future Vision Inc.Inventors: Fumitaka Takemura, Tomoe Yamazaki, Yosuke Kobayashi, Tsutomu Tanaka
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Patent number: 7749556Abstract: A method for manufacturing a field emission substrate is disclosed. The method includes the following steps: providing a substrate having a conductive layer; forming a hydrophobic layer on the conduction layer; patterning the hydrophobic layer; and removing the hydrophobic layer from the surface of the conductive layer so that the formed layer of electron-emitting materials can contact the surface of the conductive layer. The patterned hydrophobic layer can include plural bumps, and the pitches between the neighboring bumps are in a range of 1 ?m to 500 ?m. By way of the steps illustrated above, the emitting layer on the substrate can be made easily and arranged accurately. Hence, the electrons can be emitted homogeneously.Type: GrantFiled: June 30, 2006Date of Patent: July 6, 2010Assignees: Tatung Company, Industrial Technology Research InstituteInventors: Hung-Yung Li, Tsuey-May Yin, Tsai-Ling Ho
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Publication number: 20090190880Abstract: A method of manufacturing an opto-electric hybrid board which is capable of reducing the number of steps for the manufacture of the opto-electric hybrid board and which achieves the reduction in thickness of the opto-electric hybrid board to be manufactured, and an opto-electric hybrid board obtained thereby. A plurality of protruding cores (optical interconnect lines) 3 are formed in a predetermined pattern. Thereafter, a thin metal film 4 is formed in grooves defined between adjacent ones of the cores 3. Via-filling plating is performed on the thin metal film 4 to fill the above-mentioned grooves with a via-filling plated layer 6a. The plated layer 6a serves as electrical interconnect lines 6.Type: ApplicationFiled: January 23, 2009Publication date: July 30, 2009Applicant: NITTO DENKO CORPORATIONInventors: Takami HIKITA, Kazunori MUNE, Toshiki NAITOU, Yasunari OOYABU
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Publication number: 20090084588Abstract: A circuit board includes a substrate, a circuit pattern and a through electrode. The circuit pattern is disposed on one side of the substrate in a thickness direction thereof. The through electrode is filled in a through-hole formed in the substrate with one end connected to the circuit pattern. The circuit pattern and the through electrode each have an area containing a noble metal component (e.g., Au component) and are connected to each other therethrough.Type: ApplicationFiled: July 28, 2008Publication date: April 2, 2009Applicant: Napra Co., Ltd.Inventors: Shigenobu SEKINE, Yurina Sekine, Yoshiharu Kuwana
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Publication number: 20080218983Abstract: A method of manufacturing a circuit board is provided. The method includes forming a plurality of first holes in a semiconductor substrate, each of the first holes being opened toward a front surface of the semiconductor substrate, filling a bottom side of the plurality of first holes with an insulating layer, filling the first holes filled with the insulating layer on the bottom side thereof with a first electro-conductive layer, polishing the semiconductor substrate from the back surface thereof until the respective insulating layers filled in the plurality of first holes are exposed, and forming a second hole in each of the exposed insulating layers so as to reach the first electro-conductive layer, and forming a second electro-conductive layer by filling each second hole with the second electro-conductive layer to connect the first electro-conductive layer.Type: ApplicationFiled: March 6, 2008Publication date: September 11, 2008Applicant: SONY CORPORATIONInventor: Takuya Nakamura
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Patent number: 7404251Abstract: A process of copper plating a through-hole in a printed circuit board, and the printed circuit board made from such process. The process comprises: providing a printed circuit board with at least two copper interconnect lines separated by an insulator in the vertical direction; providing a through-hole in the printed circuit board in the vertical direction such that the interconnect lines provide a copper land in the through-hole; applying a seed layer to an interior surface of the through-hole; removing an outermost portion of the seed layer from the interior surface of the through-hole with a laser; applying copper on the seed layer.Type: GrantFiled: April 18, 2006Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Stephen L. Buchwalter, Russell Alan Budd
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Patent number: 7240419Abstract: A method of manufacturing a magnetoresistance effect element includes forming an insulating layer on a first ferromagnetic layer, forming an aperture reaching the first ferromagnetic layer by thrusting a needle from the top surface of the insulating layer, and depositing a ferromagnetic material to form a second ferromagnetic layer overlying the insulating layer which buries the aperture. The aperture can have an opening width not larger than 20 nm. A current flowing between the first ferromagnetic layer and the needle can be monitored, and thrusting of the needle can be interrupted when the current reaches a predetermined value.Type: GrantFiled: March 10, 2004Date of Patent: July 10, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Shiho Okuno, Yuichi Ohsawa, Shigeru Haneda, Yuzo Kamiguchi, Tatsuya Kishi
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Patent number: 7005236Abstract: Maintaining photoresist thickness and uniformity over a substrate that includes various cavities presents problems, such as preventing distortion of features in the resist image close to cavity edges. These problems have been overcome by laying down the photoresist as two separate layers. The first layer is used to eliminate or reduce problems associated with the presence of the cavities. The second layer is processed in the normal way and does not introduce distortions close to a cavity's edge. A first embodiment introduces some liquid into the cavity before laying down the first layer while the second embodiment etches away part of the first layer before applying the second one. Application of the process to the formation of a cantilever that overhangs a cavity is also described.Type: GrantFiled: April 23, 2003Date of Patent: February 28, 2006Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Su-Jen Cheng, Bor-Ping Jang, Chun-Chieh Wang, Jy-Jie Gau
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Patent number: 6926922Abstract: A process and composition for manufacturing printed wiring boards that reduces or eliminates the problem of depositing electroless nickel in through holes that are not designed to be metal plated is provided. Also provided by the present invention is a method and composition for depositing a final finish that is even and bright. The present invention is particularly suitable for the manufacture of printed circuit boards containing one or more electroless nickel-immersion gold layers.Type: GrantFiled: April 7, 2003Date of Patent: August 9, 2005Assignee: Shipley Company, L.L.C.Inventors: Mei Kiu Leung, Willetta Lai, Pit Kai Peter Cheng, Cecilia Po Sze Wong