Abstract: A method of performing electroless electrochemical atomic layer deposition is provided and includes: providing a substrate including an exposed upper metal layer; exposing the substrate to a first precursor solution to create a sacrificial metal monolayer on the exposed upper metal layer via underpotential deposition, where the first precursor solution is an aqueous solution including a reducing agent; subsequent to the forming of the sacrificial metal monolayer, rinsing the substrate; subsequent to the rinsing of the substrate, exposing the substrate to a second precursor solution to replace the sacrificial metal monolayer with a first deposition layer; and subsequent to replacing the sacrificial metal monolayer with the first deposition layer, rinsing the substrate. The exposure of the substrate to the first precursor solution and the exposure of the substrate to the second precursor solution are electroless processes.

Abstract: The present invention relates to method for activating a copper or copper alloy surface for depositing a metal or metal alloy layer by electroless (autocatalytic) plating thereon wherein the formation of undesired voids is suppressed. The copper or copper alloy surface is contacted with palladium ions, at least one phosphonate compound and halide ions followed by electroless (autocatalytic) deposition of a metal such as palladium or a metal alloy such as a Ni—P alloy.

Abstract: The present invention relates to an electrolyte for the electroless deposition of a metal layer on a substrate, wherein the electrolyte is free of heavy metal stabilizers, cyanides, selenium compounds and sulfur compounds comprising sulfur in an oxidation state between ?2 and +5, and in which instead a ?-amino acid is used as stabilizer. In particular, the inventive electrolyte can comprise 3-aminopropionic acid, 3-aminobutyric acid, 3-amino-4-methylvaleric acid, and 2-aminoethane-sulfonic acid. Furthermore, the invention is directed to a method for the electroless deposition of metal layers utilizing an inventive electrolyte as well as the use of ?-amino acids as stabilizer in electrolytes for the electroless deposition of metal layers in general.

Abstract: Disclosed are pre-wetting apparatus designs and methods. These apparatus designs and methods are used to pre-wet a wafer prior to plating a metal on the surface of the wafer. Disclosed compositions of the pre-wetting fluid prevent corrosion of a seed layer on the wafer and also improve the filling rates of features on the wafer.

Abstract: The invention relates to a method for producing a ceramic component, a ceramic component, and a component assembly having a ceramic component and a connection component. The method according to the invention for producing a ceramic component (1) comprises the steps: a) providing a ceramic substrate (2), wherein a conducting path (3) is arranged in the interior and/or on the surface of the ceramic substrate (2), and at least some regions of the ceramic substrate (2) are covered by a glaze (5); b) creating a contacting opening (6) in the glaze (5) in a region of a contact region (15) of the conducting path (3) to be contacted; c) applying a metallic layer (7) in the region of the contacting opening (6) for contacting the conducting path (3) in the contact region (15).

Abstract: The embodiments fill the need of improving electromigration and reducing stress-induced voids of copper interconnect by enabling deposition of a thin and conformal barrier layer, and a copper layer in the copper interconnect. The adhesion between the barrier layer and the copper layer can be improved by making the barrier layer metal-rich prior copper deposition and by limiting the amount of oxygen the barrier layer is exposed prior to copper deposition. Alternatively, a functionalization layer can be deposited over the barrier layer to enable the copper layer being deposit in the copper interconnect with good adhesion between the barrier layer and the copper layer. An exemplary method of preparing a substrate surface of a substrate to deposit a functionalization layer over a metallic barrier layer of a copper interconnect to assist deposition of a copper layer in the copper interconnect in an integrated system in order to improve electromigration performance of the copper interconnect is provided.

Abstract: Microfabricated inductors with through-wafer vias and including a first wafer and a second wafer, each wafer having a plurality of metal fillings therein, and a plurality of metal conductors connecting the plurality of metal fillings together to form a spiral. A method for producing an inductor including steps of forming a first plurality of vias in a first substrate, filling the first plurality of vias in the first substrate with a first plurality of metal fillings, forming a first plurality of metal conductors, connecting pairs of the first plurality of metal fillings together using the first plurality of metal conductors to form a spiral, performing the foregoing steps similarly on a second substrate formed with a second plurality of vias filled with a second plurality of metal fillings, and bonding the first substrate with the second substrate.

Abstract: A method of manufacturing ULSI wiring in which wiring layers are separately formed via a diffusion prevention layer and an insulating interlayer portion made of SiO2. The method comprises the steps of treating, with a silane compound, a SiO2 surface of the insulating interlayer portion on which the diffusion layer is to be formed, performing catalyzation with an aqueous solution containing a palladium compound, forming the diffusion prevention layer by electroless plating, and then forming the wiring layer on this diffusion prevention layer. A capping layer may be formed on the wiring layer by electroless plating. Consequently, a diffusion prevention layer having good adhesive properties can be formed through a simple wet process, and, the wiring layer can directly be formed on this diffusion prevention layer by a wet process. The capping layer can also be directly formed on the wiring layer by electroless plating.

Abstract: The copper electroless baths are formaldehyde free and are environmentally friendly. The electroless copper baths include one or more sulfinate compounds as reducing agents to replace formaldehyde. The electroless baths are stable and deposit a bright copper on substrates.

Abstract: Zero-valent silver compositions include 4-dimethylaminopyridine as stabilizers. The zero-valent silver and the 4-diemthylaminopyridine form stabilized nano-particles in solution. The zero-valent silver compositions may be used as catalysts in the metallization of non-conductive substrates.

Abstract: The present disclosure describes an article and a method of forming a microstructure. The method includes providing a substrate having a structured surface region comprising one or more recessed features with recessed surfaces. The structured surface region is substantially free of plateaus. The method includes disposing a fluid composition comprising a functional material and a liquid onto the structured surface region. The method includes evaporating liquid from the fluid composition. The functional material collects on the recessed surfaces such that a remainder of the structured surface region is substantially free of the functional material.

Abstract: A fabrication method for a flexible circuit board is provided. The fabrication method includes the following steps. Firstly, a release film having an upper surface and a lower surface opposite to each other is provided. Next, two flexible substrates are respectively disposed on the upper surface and the lower surface. Next, a plurality of nano-scale micro-pores are formed on each flexible substrate to form two non-smooth flexible substrates. The nano-scale micro-pores evenly distributed over an outer surface of each non-smooth flexible substrate. Each non-smooth flexible substrate being adapted to be performed a plating process directly on the outer surface thereof.

Abstract: An apparatus for making an electrode of a dye-sensitized solar cell, includes a dye container, a number of nozzles, a roller and a number of holders. The dye container has a chamber for receiving a dye material, and the chamber has a top wall and a number of through holes formed through the top wall. The nozzles each have an opening facing toward a substrate to be formed into the electrode and configured for jetting a working material to the substrate. The roller rolls the working material on the substrate. The holders are rotatably mounted on the top wall and each hold a corresponding substrate to first receive the working material and then to be submerged into the dye material through one of the through holes of the dye container by rotation, thereby obtaining the electrode of a dye-sensitized solar cell.

Abstract: A method of manufacturing a multilayer printed wiring board includes forming a first interlaminar resin insulating layer, a first conductor circuit on the first interlaminar resin insulating layer, a second interlaminar resin insulating layer, opening portions in the second interlaminar resin insulating layer to expose a face of the first conductor circuit, an electroless plating film on the second interlaminar resin insulating layer and the exposed face, and a plating resist on the electroless plating film. The method further includes substituting the electroless plating film with a thin film conductor layer, having a lower ion tendency than the electroless plating film, and a metal of the exposed face, forming an electroplating film including the metal on a portion of the electroless plating film and the thin film conductor layer, stripping the plating resist, and removing the electroless plating film exposed by the stripping.

Abstract: A method for forming electrical traces on a substrate includes the steps of: providing a substrate; printing an ink pattern using an ink on the substrate, the ink including a aqueous medium containing silver ions and a heat sensitive reducing agent; heating the ink pattern to reduce silver ions into silver particles thereby forming an semi-finished traces; and forming a metal overcoat on the semi-finished traces by electroless plating thereby obtaining patterned electrical traces.

Abstract: Disclosed herein is a method for manufacturing a printed circuit board. According to a preferred embodiment of the present invention, there is provided a method for manufacturing a printed circuit board, including: preparing a base substrate; forming a carrier layer on the base substrate; forming a through via hole penetrating the carrier layer and the base substrate; forming a plating layer on the carrier layer and an inner wall of the through via hole; filling the through via hole with a conductive paste; removing a portion of the plating layer formed on the carrier layer; removing the carrier layer; and forming a circuit layer on the base substrate.

Abstract: Some embodiments include methods of forming conductive material within high aspect ratio openings and low aspect ratio openings. Initially, the high aspect ratio openings may be filled with a first conductive material while the low aspect ratio openings are only partially filled with the first conductive material. Additional material may then be selectively plated over the first conductive material within the low aspect ratio openings relative to the first conductive material within the high aspect ratio openings. In some embodiments, the additional material may be activation material that only partially fills the low aspect ratio opening, and another conductive material may be subsequently plated onto the activation material to fill the low aspect ratio openings.

Abstract: A substrate structure is provided. The substrate structure includes a substrate, a first insulation layer, a conductive part, a second insulation layer, a seed layer and a conductive layer. The substrate has a first circuit pattern layer and a second circuit pattern layer, which are located on two opposite surfaces of the substrate respectively. The first insulation layer formed on the first circuit pattern layer has a first insulation hole, which exposes a first opening in the outer surface of the first insulation layer. The conductive part formed on the first insulation hole for electrically connecting with a chip is enclosed by the edge of the first opening. The second insulation layer formed on the second circuit pattern layer has a second insulation hole in which the seed layer is formed. The conductive layer is formed on the seed layer for electrically connecting with a circuit board.

Abstract: The invention relates to a method for producing a ceramic component, a ceramic component, and a component assembly having a ceramic component and a connection component. The method according to the invention for producing a ceramic component (1) comprises the steps: a) providing a ceramic substrate (2), wherein a conducting path (3) is arranged in the interior and/or on the surface of the ceramic substrate (2), and at least some regions of the ceramic substrate (2) are covered by a glaze (5); b) creating a contacting opening (6) in the glaze (5) in a region of a contact region (15) of the conducting path (3) to be contacted; c) applying a metallic layer (7) in the region of the contacting opening (6) for contacting the conducting path (3) in the contact region (15).

Abstract: A main reservoir holds cool reactant liquid. A reaction vessel for treating a substrate is connected to the main reservoir by a feed conduit. A heater is configured to heat reactant liquid in the feed conduit before the liquid enters the reaction vessel. Preferably, the heater is a microwave heater. A recycle conduit connects the reaction vessel with the main reservoir. Preferably, a recycle cooler cools reactant liquid in the recycle conduit before the liquid returns to the main reservoir. Preferably, an accumulation vessel is integrated in the feed conduit for accumulating, heating, conditioning and monitoring reactant liquid before it enters the reaction vessel. Preferably, a recycle accumulator vessel is integrated in the recycle conduit to accommodate reactant liquid as it empties out of the reaction vessel.

Abstract: The present invention provides a method of forming a metal pattern and a metal pattern obtained by the method. The method includes the steps of (I) forming on a substrate a polymer layer in which a polymer having a functional group that interacts with an electroless plating catalyst or a precursor thereof is chemically bonded directly to the substrate in a pattern form, (II) adding the electroless plating catalyst or precursor thereof to the polymer layer, and (III) forming a metal layer in the pattern form by electroless plating.

Abstract: The embodiments fill the need to enhance electro-migration performance, provide lower metal resistivity, and improve metal-to-metal interfacial adhesion for copper interconnects by providing improved processes and systems that produce an improved metal-to-metal interface, more specifically barrier-to-copper interface. An exemplary method of preparing a substrate surface of a substrate to deposit a metallic barrier layer to line a copper interconnect structure of the substrate and to deposit a thin copper seed layer on a surface of the metallic barrier layer in an integrated system to improve electromigration performance of the copper interconnect is provided. The method includes cleaning an exposed surface of a underlying metal to remove surface metal oxide in the integrated system, wherein the underlying metal is part of a underlying interconnect electrically connected to the copper interconnect.

Abstract: A method of forming a metal film, the method including: (a) forming a primer layer on a substrate by applying a first polymer including a unit having a cyano group in a side chain; (b) forming a polymer layer on the surface of the primer layer by applying a second polymer, the second polymer having a functional group that interacts with an electroless plating catalyst or a precursor thereof and a polymerizable group; (c) applying the electroless plating catalyst or the precursor thereof to the polymer layer; and (d) forming a metal film on the polymer layer by performing electroless plating.

Abstract: The invention provides a method of forming a metallic pattern including: (a) forming, in a pattern form on a substrate, a polymer layer which contains a polymer that has a functional group that interacts with an electroless plating catalyst or a precursor thereof; (b) imparting the electroless plating catalyst or precursor thereof onto the polymer layer; and (c) forming a metallic film in the pattern form by subjecting the substrate having the polymer layer to electroless plating using an electroless plating solution, wherein the substrate is treated using a solution comprising a surface charge modifier or 1×10?10 to 1×10?4 mmol/l of a plating catalyst poison before or during the (c) forming of the metallic film. The invention further provides a metallic pattern obtained thereby. Furthermore, the invention provides a printed wiring board and a TFT wiring board, each of which uses the metallic pattern as a conductive layer.

Abstract: A method for manufacturing a metal clad laminate having a film and a metal layer formed of a foundation layer and an upper layer includes the steps of forming the foundation layer on at least a part of a surface of the film by plating to obtain a first laminate; forming the upper layer on the first laminate by plating to obtain a second laminate; and heating the second laminate to obtain the metal clad laminate. Further, the film is a flexible thermoplastic polymer film, the foundation layer is formed of a nickel alloy, the upper layer is formed of copper, at least one of the foundation layer and the upper layer has a compression stress before the step of heating the second laminate, and the metal clad laminate shrinks in a planar direction of the film during the step of heating the second laminate.

Abstract: Methods and systems are provided which are adapted to process a microelectronic topography, particularly in association with an electroless deposition process. In general, the methods may include loading the topography into a chamber, closing the chamber to form an enclosed area, and supplying fluids to the enclosed area. In some embodiments, the fluids may fill the enclosed area. In addition or alternatively, a second enclosed area may be formed about the topography. As such, the provided system may be adapted to form different enclosed areas about a substrate holder. In some cases, the method may include agitating a solution to minimize the accumulation of bubbles upon a wafer during an electroless deposition process. As such, the system provided herein may include a means for agitating a solution in some embodiments. Such a means for agitation may be distinct from the inlet/s used to supply the solution to the chamber.

Abstract: An electroless plating system includes a plating solution, and controlling reducing agents in the plating solution for deposition over outlier features smaller than about five hundred nanometers and isolated by about one thousand nanometers.

Abstract: Some embodiments include methods of forming conductive material within high aspect ratio openings and low aspect ratio openings. Initially, the high aspect ratio openings may be filled with a first conductive material while the low aspect ratio openings are only partially filled with the first conductive material. Additional material may then be selectively plated over the first conductive material within the low aspect ratio openings relative to the first conductive material within the high aspect ratio openings. In some embodiments, the additional material may be activation material that only partially fills the low aspect ratio opening, and another conductive material may be subsequently plated onto the activation material to fill the low aspect ratio openings.

Abstract: Methods of electroless metallalization are disclosed. The methods include treating through-holes of printed wiring boards to increase catalyst adsorption on the walls of the through-holes. The increased catalyst adsorption improves electroless metallization of the through-hole walls.

Abstract: Disclosed herein is a coreless substrate having filled via pads and a method of manufacturing the same. Insulating layers are formed on both sides of a build-up layer, and via-pads are embedded in the insulating layers such that the via-pads are flush with the insulating layers. The via pads are not separated from a substrate, and thus reliability of the pads is increased. Flatness of bumps is increased, and thus bonding of flip chips becomes easy.

Abstract: A method of forming a patterned thin film comprises the step of forming a frame having an undercut near the bottom thereof on an electrode film, and the plating step of forming the patterned thin film by plating through the use of the frame. The patterned thin film includes a plurality of linear portions disposed side by side. Each of the linear portions has a portion close to the electrode film. This portion has a width greater than the width of the remaining portion of each of the linear portions.

Abstract: The present invention relates to an electrocatalytic coating and an electrode having the coating thereon, wherein the coating is a mixed metal oxide coating, preferably ruthenium, titanium and tin or antimony oxides. The coating uses water as a solvent that provides for a smoother surface than alcohol based solvents. The electrocatalytic coating can be used especially as an anode component of an electrolysis cell and in particular a cell for the electrolysis of aqueous chlor-alkali solutions.

Abstract: Electroless copper and copper alloys plating baths are disclosed. The electroless baths are formaldehyde free and are environmentally friendly. The electroless baths are stable and deposit a bright or copper alloy on substrates.

Abstract: A process for producing an electronic component The electronic component includes a base material equipped with a core material and having a conductor layer on at least one surface thereof; a via hole formed through laser irradiation from the other surface side of the base material; a first plating layer formed by using the conductor layer as an electrode so as to cover the core material, which is exposed on an inner wall surface of the via hole; an electroless plating layer which is formed on the upper side of the first plating layer and which is in close contact with the inner wall surface of the via hole; and a second plating layer formed by using the conductor layer as an electrode so as to cover the electroless plating layer. A conductor part is formed in the via hole.

Abstract: Electroless copper plating baths are disclosed. The electroless copper baths are formaldehyde free and are environmentally friendly. The electroless copper baths are stable and deposit a bright copper deposit on substrates.

Abstract: Electroless copper and copper alloy plating baths are disclosed. The electroless baths are formaldehyde free and are environmentally friendly. The electroless baths are stable and deposit a bright copper or copper alloy on substrates.

Abstract: A printed wiring board having a conductor circuit comprising a copper layer adjacent to an insulating layer and an electroless gold plating, wherein the insulating layer has ten-point mean surface roughness (Rz) of 2.0 ?m or less is provided. According to the present invention, there is no such a defect that gold plating is deposited on a resin, and fine wiring formation with accuracy is realized.

Abstract: A method for fabricating a passive circuit in a circuit substrate is provided. The circuit substrate comprising a first metallic layer, a second metallic layer, and a dielectric layer is provided firstly, and the dielectric layer is disposed between the first metallic layer and the second metallic layer. Thereafter, a strip shaped through hole through the circuit substrate is formed. Afterward, a third metallic layer is formed on a part of a wall of the strip shaped through hole, and the third metallic layer is electrically connected to the first metallic layer and/or the second metallic layer. The third metallic layer functions as the passive circuit.

Abstract: In the present invention, a reference conductive layer and a first surface conductive layer are respectively provided on a surface and a back face of a first base film. The first base film includes a first via hole penetrating the first surface conductive layer. After a first electroless plating layer and a first conductive material are sequentially grown on a surface of the first base film, a first coating conductive layer composed of the first electroless plating layer, the first conductive material and the first surface conductive layer, is etched to have a reduced thickness. Then, the first coating conductive layer is patterned to form a first wiring layer. In this manner, a desired pattern width can be obtained even in the case where the first coating conductive layer is patterned by isotropic etching such as wet etching.

Abstract: A hole plugging method for a printed circuit board, a hole plugging device in accordance therewith and a manufacturing method in accordance therewith where a mask for selectively exposing a via hole, a through hole and a surface pattern of the printed circuit board is positioned on the board having the via hole and the through hole to electrically connect circuit patterns formed on the surface of the board and in the board and an insulating material is plugged in the via hole by abutting and pushing the material on the surface of the board. Therefore, the insulating material can be plugged smoothly without a void, the processing is simplified by plugging the insulating material just to the height of the circuit pattern in a space between the circuit patterns and accordingly, damage to the circuit pattern can be prevented.

Abstract: A process and composition for manufacturing printed wiring boards that reduces or eliminates the problem of depositing electroless nickel in through holes that are not designed to be metal plated is provided. Also provided by the present invention is a method and composition for depositing a final finish that is even and bright. The present invention is particularly suitable for the manufacture of printed circuit boards containing one or more electroless nickel-immersion gold layers.

Abstract: An interconnection structure comprising a substrate having a dielectric layer with a via opening therein; a barrier layer located in the via opening; an interlayer of palladium and/or platinum on the barrier layer; and a layer of copper or copper alloy on the interlayer is provided.