Including Metal Layer Patents (Class 428/209)
  • Patent number: 11324541
    Abstract: Thermal cutting surgical instruments incorporate a blade incorporating a first substrate of high thermal conductivity material in the heated portion of the blade and a support and, the first substrate of high thermal conductivity material joined to a second substrate of low thermal conductivity material in the support region of the blade; an electrically insulative dielectric layer disposed on the first surface of the first substrate and on the first surface of second substrate; an electrically resistive heating element disposed on the electrically insulative dielectric; electrically conductive power leads and electrically conductive sense leads disposed on the electrically insulative dielectric layer and that are in electrical communication with the electrically resistive heating element; and an electrically insulative dielectric overcoat layer disposed on the electrically resistive heating element and on the distal portion of the electrically conductive power leads and electrically conductive sense leads.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: May 10, 2022
    Assignee: Eggers & Associates, LLC
    Inventor: Philip E. Eggers
  • Patent number: 11322176
    Abstract: A method of manufacturing a magnetic recording medium forms an unfinished product including a magnetic recording layer and a protection layer that are successively formed on a substrate, and forms a lubricant layer on the protection layer of the unfinished product. The lubricant layer is formed by coating a first organic fluorine compound on the protection layer of the unfinished product, and supplying a gas, including a second organic fluorine compound, onto the protection layer of the unfinished product, and decomposing the second organic fluorine compound by Townsend discharge and ultraviolet ray irradiation. The protection layer includes carbon, and the first organic fluorine compound includes a functional group at a terminal thereof.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: May 3, 2022
    Assignees: SHOWA DENKO K.K., The School Corporation Kansai University
    Inventors: Hiroshi Tani, Hiroshi Sakai, Eishin Yamakawa, Kazuki Shindo
  • Patent number: 11302871
    Abstract: Provided are an organic light-emitting device including a capping layer including an amine-based compound represented by a set or predetermined formula and a radical scavenger, and a light-emitting apparatus including the organic light-emitting device. The organic light-emitting device includes: a first electrode; a second electrode facing the first electrode; an organic layer between the first electrode and the second electrode and including an emission layer a capping layer on the second electrode, wherein the capping layer includes the amine-based compound.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: April 12, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jaeweon Hur, Soungwook Kim, Seulong Kim
  • Patent number: 11277909
    Abstract: The disclosure provides a three-dimensional circuit assembly including a printed circuit board comprising a top film surface and a bottom film surface opposite to the top film surface. The three-dimensional circuit assembly may also include a first layer of a composite material bonded or laminated on the top film surface. The three-dimensional circuit assembly may further include a second layer of the composite material bonded or laminated on the bottom film surface of the printed circuit board.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: March 15, 2022
    Assignee: TTM TECHNOLOGIES INC.
    Inventors: John Vesce, III, Joseph William Heery, Jr.
  • Patent number: 11267390
    Abstract: A lamp arrangement for a motor vehicle, including a lamp with a transparent carrier for at least one light source, in particular a micro-LED, and a control device. The lamp arrangement has at least one environmental sensor which is arranged behind the carrier and which acquires sensor data through the carrier.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: March 8, 2022
    Assignee: AUDI AG
    Inventors: Jacques Helot, Ulrich Müller
  • Patent number: 11259401
    Abstract: A resin multilayer substrate includes a plurality of insulating resin base material layers and a plurality of conductor patterns provided on the plurality of insulating resin base material layers. The plurality of conductor patterns include a signal line and a ground conductor overlapping the signal line as viewed from a laminating direction of the insulating resin base material layers. A plurality of openings are provided in the ground conductor, and an aperture ratio is higher in a zone far from the signal line than in a zone adjacent to or in a vicinity of the signal line in a direction perpendicular or substantially perpendicular to the laminating direction.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: February 22, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hiromasa Koyama
  • Patent number: 11241752
    Abstract: Nanometers thick conformal coatings deposited by atomic-layer deposition (ALD) onto the metal surface of an active braze joint modifies the surface chemistry to eliminate excess braze filler metal flow. Unlike other means used to prevent braze filler metal runout, the thin ALD coating does not hinder next assembly processes, does not require post-braze cleaning, and does not alter the base material mechanical properties.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: February 8, 2022
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Ronald S. Goeke, Charles A. Walker, Juan A. Romero
  • Patent number: 11239185
    Abstract: A panel type fan-out wafer level package with embedded film type capacitors and resistors is described. The package comprises a silicon die at a bottom of the package wherein a top side and lateral sides of the silicon die are encapsulated in a molding compound, at least one redistribution layer connected to the silicon die through copper posts contacting a top side of the silicon die, at least one embedded capacitor material (ECM) sheet laminated onto the package, and at least one embedded resistor-conductor material (RCM) sheet laminated onto the package wherein the at least one redistribution layer, capacitors in the at least one ECM, and resistors in the at least one RCM are electrically interconnected.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: February 1, 2022
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Ernesto Gutierrez, III, Jesus Mennen Belonio, Jr., Shou Cheng Eric Hu
  • Patent number: 11230787
    Abstract: Embodiments of nanostructures comprising metal oxide and methods for forming the nanostructure on surfaces are disclosed. In certain embodiments, the nanostructures can be formed on a substrate made of a nickel titanium alloy, resulting in a nanostructure containing both titanium oxide and nickel oxide. The nanostructure can include a lattice layer disposed on top of a nanotube layer. The distal surface of the lattice layer can have a titanium oxide to nickel oxide ratio of greater than 10:1, or about 17:1, resulting in a nanostructure that promotes human endothelial cell migration and proliferation at the interface between the lattice layer and human cells or tissue. The nanostructure may be formed on the outer surface of an implantable medical device, such a stent or an orthopedic implant (e.g. knee implant, bone screw, or bone staple).
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: January 25, 2022
    Assignee: Alfred E. Mann Institute for Biomedical Engineering at the University of Southern California
    Inventors: David Alvin Tyvoll, Nan Chen, Bharat Kumar Menon, Heather Michelle Grandin, Cesar Escobar Blanco
  • Patent number: 11224117
    Abstract: An integrated heat exchanger has a heat exchanger within a circuit board. The circuit board can be a PCB having one or more electronic components coupled to its top-side surface. The conductive layers of the PCB include a first sub-set of electrically conductive interconnects and as second sub-set of electrically conductive interconnects. The first sub-set of conductive layers are electrically connected to each other and to the one or more electronic components. The second sub-set of conductive layers are electrically isolated from the first sub-set of conductive layers by intervening non-conductive layers such as prepreg. In this manner, the heat exchanger is electrically isolated from the one or more electronic components. The second sub-set of conductive layers include a dedicated top-side conductive layer to which a baseplate can be attached. The baseplate is also attached to the one or more electronic components via an electrically non-conductive gap filler.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: January 11, 2022
    Assignee: Flex Ltd.
    Inventors: Magnus Karlsson, Oscar Persson
  • Patent number: 11192821
    Abstract: The subject of the invention is a material comprising a glass sheet coated on at least one portion of one of the faces thereof with a stack of thin layers comprising at least one layer based on a nitride, said stack being coated on at least one portion of its surface with an enamel layer comprising bismuth, said stack further comprising, in contact with the enamel layer, a layer, referred to as a contact layer, which is based on an oxide.
    Type: Grant
    Filed: November 23, 2018
    Date of Patent: December 7, 2021
    Assignee: SAINT-GOBAIN GLASS FRANCE
    Inventor: Juliette Jamart
  • Patent number: 11183425
    Abstract: A semiconductor device includes a semiconductor part; an electrode selectively provided on the semiconductor part, the electrode being electrically connected to the semiconductor part; and multiple metal layers provided on the electrode. A method of manufacturing the semiconductor device includes selectively forming a first metal layer on the electrode; forming a palladium layer on the first metal layer, the palladium layer covering the first metal layer; forming a second metal layer on the palladium layer, the second metal layer covering the palladium layer; and forming a gold layer directly on the palladium layer by replacing the second metal layer with the gold layer.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: November 23, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Kengo Furutani
  • Patent number: 11171080
    Abstract: A wiring substrate includes a first insulation layer, an electronic component including a first surface and a second surface which is an opposite surface to the first surface, the electronic component being mounted on the first insulation layer with the first surface facing toward the first insulation layer, and a second insulation layer including a first layer and a second layer. The first layer is formed on the first insulation layer and configured to cover the second surface of the electronic component, and the second layer is stacked on the first layer. The first layer includes therein fillers. At least one of the fillers is in direct contact with the second surface of the electronic component at one side, and is exposed from the first layer and is thus in direct contact with the second layer at the other side.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: November 9, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takahiko Kiso, Masahiro Kyozuka
  • Patent number: 11163386
    Abstract: A touch display panel and a liquid crystal display device are disclosed. The touch display panel comprises: a substrate (1); a Chip-On-Film (COF) (2), one end of the COF (2) being bound on the substrate and the other end of the COF (2) having a first binding pin (21); and a flexible circuit board (3), one end of the flexible circuit board (3) being bound on the substrate (1) and the other end of the flexible circuit board (3) having a second binding pin (31), wherein a width L2 of the second binding pin (31) is greater than a width L1 of the first binding pin (21).
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: November 2, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Kangpeng Dang, Cheng Zuo, Shuai Hou
  • Patent number: 11155114
    Abstract: A multi-purpose sticker for decorating and sealing an envelope and also for attaching the sealed envelope to a package, such as a gift. The multi-purpose sticker generally includes a double-sided adhesive layer hidden below a decorative covering. With the decorative cover in place, one side of the double-sided adhesive of the sticker can be used to seal an envelope, and the sticker serves as a decorative sticker. If desired, the decorative cover can be peeled off to expose an adhesive in order to affix the sealed envelope to a package.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: October 26, 2021
    Inventor: Nathan A. Zaffke
  • Patent number: 11145689
    Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chips and related methods are disclosed. LED chips are provided that include an indicia arranged between a primary light-emitting face and a mounting face of the LED chip. The indicia may include at least one of a logo, one or more alphanumeric characters, or a symbol, among others that are configured to convey information. Arrangements of at least one of an n-contact, a p-contact, or a reflector layer of the LED chip may form the indicia. LED chips are also provided where at least a portion of an indicia is arranged on a mounting face of the LED chip. Indicia are provided that may be visible through primary light-emitting faces when LED chips are electrically activated or electrically deactivated. In this regard, the indicia may be embedded within LED chips while still being able to convey information.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: October 12, 2021
    Assignee: CreeLED, Inc.
    Inventors: Nikolas Hall, Derek Miller, Anoop Mathew, Colin Blakely, Luis Breva, Jesse Reiherzer, David Todd Emerson
  • Patent number: 11133491
    Abstract: A high-yield fabricating method of a semiconductor device including a peeling step is provided. A peeling method includes a step of stacking and forming a first material layer and a second material layer over a substrate and a step of separating the first material layer and the second material layer from each other. The second material layer is formed over the substrate with the first material layer therebetween. The first material layer includes a first compound layer in contact with the second material layer and a second compound layer positioned closer to the substrate side than the first compound layer is. The first compound layer has the highest oxygen content among the layers included in the first material layer. The second compound layer has the highest nitrogen content among the layers included in the first material layer. The second material layer includes a resin.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: September 28, 2021
    Inventors: Seiji Yasumoto, Kayo Kumakura, Yuka Sato, Satoru Idojiri, Hiroki Adachi, Kenichi Okazaki
  • Patent number: 11127692
    Abstract: A semiconductor package includes a semiconductor chip, and a connection structure disposed on at least one side of the semiconductor chip, and including an insulating layer and a redistribution layer electrically connected to the semiconductor chip, wherein the redistribution layer includes a plurality of conductive patterns, and at least two of the plurality of conductive patterns have different degrees of surface roughness, and a conductive pattern having a higher surface roughness has a width wider than a width of a conductive pattern having a lower surface roughness.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: September 21, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gun Lee, Jun Gul Hwang, Ji Eun Woo, Sung Keun Park
  • Patent number: 11104281
    Abstract: Provided is a vehicle engine room structure to cause high-temperature air in an engine room to be discharged outside, regardless of the presence or absence of rushing air. The structure includes: a baffle plate including a curved portion to surround a turbocharger of a vehicle from behind, when disposed in a vehicle, and an extending portion continuous from the curved portion and extending upward, when disposed in the vehicle. The baffle plate is disposed between the turbocharger and a lower dash panel of the vehicle. The baffle plate further includes a lower fixing portion fixed to the lower dash panel. The baffle plate and the lower dash panel define an installation space therebetween, in which in-vehicle components are installed.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: August 31, 2021
    Assignee: HONDA MOTOR CO., LTD.
    Inventor: Tomoya Takeda
  • Patent number: 11102892
    Abstract: A carbene-coated metal foil is produced by applying an N-heterocyclic carbene (NHC) compound to one or more surfaces of a metal foil (e.g., an electrodeposited copper foil having a surface that is smooth and non-oxidized). The NHC compound contains a matrix-reactive pendant group that includes at least one of a vinyl-, allyl-, acrylic-, methacrylic-, styrenic-, amine-, amide- and epoxy-containing moiety capable of reacting with a base polymer (e.g., a vinyl-containing resin such as a polyphenylene oxide/triallyl-isocyanurate (PPO/TAIC) composition). The NHC compound may be synthesized by, for example, reacting a halogenated imidazolium salt (e.g., 1,3-bis(4-bromo-2,6-dimethylphenyl)-4,5-dihydro-1H-imidazol-3-ium chloride) and an organostannane having a vinyl-containing moiety (e.g., tributyl(vinyl)stannane) in the presence of a palladium catalyst.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Dylan J. Boday, Joseph Kuczynski, Jason T. Wertz, Jing Zhang
  • Patent number: 11102891
    Abstract: A method of manufacturing a polymer printed circuit board contains in a sequential order steps of: A), B), C), D, and F). In the step A), a material layer consisting of polymer is provided. In the step B), circuit pattern is formed on the material layer. In the step C), metal nanoparticles are deposited on the laser induced graphene (LIG) of the circuit pattern so as to use as a material seed. In the step D) a metal layer on the nanoparticles are deposited and the LIG of the circuit pattern are formed. In the step E), the circuit pattern is pressed. In the step E), the circuit pattern, the material layer, the metal nanoparticles, and the metal layer are pressed in a laminating manner to obtain the polymer printed circuit board.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: August 24, 2021
    Assignee: BGT MATERIALS LIMITED
    Inventors: Kuo-Hsin Chang, Jia-Cing Chen, We-Jei Ke, Jingyu Zhang, Chung-Ping Lai
  • Patent number: 11101745
    Abstract: An actuator is configured to include a first substrate that has a first conductive surface, which may be or include a first conductive electrode layer. The actuator also includes a second substrate that has a second conductive surface, which may be or include a second conductive electrode layer. The first and second conductive surfaces face toward each other across a compression space between the first and second substrates. A group of elastic support nodules span the compression space and separate the first and second conductive surfaces. The compression space is less than fully filled with solid elastic material and is configured to be compressed by relative movement of the first and second conductive surfaces toward each other in response to a voltage difference between the first and second conductive surfaces.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: August 24, 2021
    Assignee: Pix Art Imaging Inc.
    Inventors: Ville Mäkinen, Roberto Tejera-Garcia, Aki Salminen
  • Patent number: 11095070
    Abstract: An object of the invention is to suppress rotation around the axis of a tip part of a single wire and to suppress removal of the single wire from a housing. An electrical connector 1 according to the invention includes a housing 2; a terminal 3 to which a single wire W is to be connected; and a holding member 4, wherein the holding member 4 has a leading-out part 44 to lead out the single wire W from the inside to the outside of the housing 2, and the leading-out part 44 is configured to lead out the single wire W being bent and extending in a given extending direction so as to cross the axis X direction of a tip part W11 of the single wire W connected to a single wire connecting part 32.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: August 17, 2021
    Assignee: J.S.T. MFG. CO., LTD.
    Inventors: Takahiro Ishikawa, Masaaki Ishigami, Kensuke Takahashi
  • Patent number: 11088347
    Abstract: A light emitting device including a base, a first electrode, a barrier structure layer, a light emitting layer and a second electrode is provided. The barrier structure layer includes a first barrier layer in contact with the first electrode, a second barrier layer and a third barrier layer. The first barrier layer, the second barrier layer and the third barrier layer stack sequentially. The materials of the first barrier layer and the third barrier layer include a dielectric material. The material of the second barrier layer includes a metal material. A boundary between the third barrier layer and the second barrier layer keeps a vertical distance from the first electrode. The light emitting structure layer is disposed between the first electrode and the second electrode and surrounded by the barrier structure layer. The thickness of the light emitting structure layer is not greater than the vertical distance.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: August 10, 2021
    Assignee: Au Optronics Corporation
    Inventors: Kent-Yi Lee, Wen-Pin Chen, Wen-Tai Chen, Kuo-Jui Chang, Tsu-Wei Chen, Kuo-Kuang Chen, Shih-Hsing Hung
  • Patent number: 11077650
    Abstract: A method for producing a composite pane for a motor vehicle includes heating the plastic film at least in the region of the LED into a fluid state by a heating source positioned on an outer surface of the first pane or the second pane or arranged at a distance from the outer surface of the first pane or the second pane, and introducing the LED into the plastic film into the fluid state with displacement of a predefined volume of the plastic film. After introducing the LED into the plastic film, the method includes laminating the first pane and the second pane with the interposed plastic film.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: August 3, 2021
    Assignee: SAINT-GOBAIN GLASS FRANCE
    Inventors: Stephan Gillessen, Pascal Bauerle, Jean Jacques Bris
  • Patent number: 11065182
    Abstract: A resin composite containing azole-functionalized silica nanoparticles. The resin composite further includes a polymerizable monomer and a polymerization initiator system. A dental restoration fabricated by curing the resin composite is also specified.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: July 20, 2021
    Inventor: Ayhan Bozkurt
  • Patent number: 11057996
    Abstract: A circuit board includes: a first substrate including a first through hole, a first metal layer formed over an inner wall of the first through hole, and a first conductive composite resin provided on an inner side of the first metal layer of the first through hole; and a second substrate stacked together with the first substrate and including a second through hole that faces the first through hole and has a first open end which is provided on a side of the first through hole and is located on the inner side of the first metal layer, and a second conductive composite resin that is provided in the second through hole and is coupled to the first conductive composite resin.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: July 6, 2021
    Assignee: FUJITSU INTERCONNECT TECHNOLOGIES LIMITED
    Inventors: Toshiki Iwai, Daisuke Mizutani, Seiki Sakuyama, Taiji Sakai
  • Patent number: 11046046
    Abstract: The invention is a laminate having a resin layer containing a crystalline alicyclic structure-containing resin and a metal layer in direct contact with the resin layer, wherein an average linear expansion coefficient of the resin layer at 60 to 100° C. is 5 to 50 ppm/° C., and a ten-point average roughness (Rz) on an interface between the resin layer and the metal layer is 2.0 ?m or less, and a method for producing the laminate, and a flexible printed circuit board using the laminate. One aspect of the invention provides a laminate which has a resin layer and a metal layer in direct contact with the resin layer and is suitably used as a substrate material, and a production method therefor, as well as a flexible printed circuit board using the laminate.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: June 29, 2021
    Assignee: ZEON CORPORATION
    Inventor: Mitsuteru Endo
  • Patent number: 11048165
    Abstract: A resist composition comprising a base polymer and a sulfonium salt of brominated indole or brominated indazole carboxylic acid offers a high sensitivity, minimal LWR and improved CDU independent of whether it is of positive or negative tone.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 29, 2021
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Jun Hatakeyama, Daisuke Domon
  • Patent number: 11040517
    Abstract: Provided are a printed circuit board in which warps are effectively suppressed, and a semiconductor package having a semiconductor device mounted on said printed circuit board, even though circuit patterns of different amounts of metal are formed on both sides of one cured product of a prepreg. Specifically, said printed circuit board is a printed circuit board which comprises a cured product of a prepreg comprising a fiber base material and a resin composition, in which circuit patterns of different amounts of metal are formed on both sides of one cured product of the prepreg, in which said prepreg has layers on the front and back of said fiber base material, wherein said layers comprise resin compositions having different heat curing shrinkage rates, in which among these layers, the layer made of the resin composition having a smaller heat curing shrinkage rate is present on the side on which the circuit pattern with a smaller amount of metal is formed.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 22, 2021
    Assignee: Showa Denko Materials Co., Ltd.
    Inventors: Takeshi Saitoh, Yukio Nakamura, Ryohta Sasaki, Junki Somekawa, Yuji Tosaka, Hiroshi Shimizu, Ryoichi Uchimura
  • Patent number: 11027977
    Abstract: A method of manufacturing a tantalum carbide material of the present invention includes heating a tantalum material (1) interposed between a pair of graphite guide members (2 and 3) under an atmosphere of a carbon source-containing gas (4) at 1,500° C. or higher for 0.5 hours or longer.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: June 8, 2021
    Assignee: SHOWA DENKO K.K.
    Inventor: Shunsuke Noguchi
  • Patent number: 11031185
    Abstract: An electronic component includes external electrodes formed on an external surface of a body to be electrically connected to internal electrodes, and containing metal particles and glass, wherein the metal particles include particles having a polyhedral shape.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jeong Ryeol Kim, Bum Suk Kang, Hyo Min Kang, Hang Kyu Cho, Chang Hoon Kim
  • Patent number: 11032915
    Abstract: A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board comprises the following steps: drilling a hole on a substrate, the hole comprising a blind hole and/or a through hole; on a surface of the substrate, forming a photoresist layer having a circuit negative image; forming a conductive seed layer on the surface of the substrate and a hole wall of the hole; removing the photoresist layer, and forming a circuit pattern on the surface of the substrate, wherein forming a conductive seed layer comprises implanting a conductive material below the surface of the substrate and below the hole wall of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: June 8, 2021
    Assignee: RICHVIEW ELECTRONICS CO., LTD.
    Inventors: Siping Bai, Xianglan Wu, Zhijian Wang, Zhigang Yang, Jinqiang Zhang
  • Patent number: 11021606
    Abstract: In a first aspect, a multilayer film includes a first outer layer including a first thermoplastic polyimide, a core layer including a polyimide, and a second outer layer including a second thermoplastic polyimide. The polyimide of the core layer includes a first aromatic dianhydride including 3,3?,4,4?-biphenyl tetracarboxylic dianhydride and a first aromatic diamine including p-phenylenediamine. The multilayer film has a total thickness in a range of from 5 to 150 ?m. A thickness of the core layer is in a range of from 35 to 73% of the total thickness of the multilayer film. A minimum peel strength for at least one of the first and second outer layers, when adhered to copper foil and tested following ASTM method IPC-TM-650, method No. 2.4.9B, is greater than 0.9 kgf/cm (0.88 N/mm). In a second aspect, a metal-clad laminate includes the multilayer film of the first aspect and a first metal layer adhered to an outer surface of the first outer layer of the multilayer film.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 1, 2021
    Assignee: E I DU PONT DE NEMOURS AND COMPANY
    Inventors: Kostantinos Kourtakis, Rosa Irene Gonzalez, Herbert W Lim
  • Patent number: 11001759
    Abstract: A resin composition is provided. The resin composition comprises the following constituents: (A) an epoxy resin, which has at least two epoxy functional groups per molecule; (B) a reactive flame retardant with (a DOPO functional group) in structure; and (C) a non-reactive phosphorus-containing flame retardant, which is compatible with the other constituents of the resin composition.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: May 11, 2021
    Assignee: TAIWAN UNION TECHNOLOGY CORPORATION
    Inventors: Chih-Wei Liao, Chang-Chien Yang, Tsung-Hsien Lin, Ju-Ming Huang
  • Patent number: 10993331
    Abstract: High-speed interconnects for printed circuit boards and methods for forming the high-speed interconnects are described. A high-speed interconnect may comprise a region of a conductive film having a reduced surface roughness and one or more regions that have been treated for improved bonding with an adjacent insulating layer. Regions of reduced roughness may be used to carry high data rate signals within PCBs. Regions treated for bonding may include a roughened surface, adhesion-promoting chemical treatment, and/or material deposited to improve wettability of the surface and/or adhesion to a cured insulator.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: April 27, 2021
    Assignee: Amphenol Corporation
    Inventors: Arthur E. Harkness, Jr., Eva M. Kenny-McDermott, Paul W. Farineau, Raymond A. Lavallee, Michael Fancher
  • Patent number: 10985225
    Abstract: The present disclosure provides a method for manufacturing an OLED display substrate, including a step of forming a pattern of a pixel definition layer on a substrate through a patterning process. A bottom wall of the pixel definition layer is formed on the substrate, a top wall of the pixel definition layer is arranged parallel to the bottom wall, and a side wall of the pixel definition layer is angled relative to the top wall at an acute angle.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: April 20, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Feng Zhang, Wenqu Liu, Zhijun Lv, Liwen Dong, Shizheng Zhang, Ning Dang
  • Patent number: 10978702
    Abstract: A novel hybrid lithium-ion anode material based on coaxially coated Si shells on vertically aligned carbon nanofiber (CNF) arrays. The unique cup-stacking graphitic microstructure makes the bare vertically aligned CNF array an effective Li+ intercalation medium. Highly reversible Li+ intercalation and extraction were observed at high power rates. More importantly, the highly conductive and mechanically stable CNF core optionally supports a coaxially coated amorphous Si shell which has much higher theoretical specific capacity by forming fully lithiated alloy. Addition of surface effect dominant sites in close proximity to the intercalation medium results in a hybrid device that includes advantages of both batteries and capacitors.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: April 13, 2021
    Assignee: CF TRAVERSE LLC
    Inventor: Ronald A. Rojeski
  • Patent number: 10962659
    Abstract: A process for manufacturing an optical system includes forming a first hydrophobic surface at a semiconductor substrate, providing a first drop of transparent material having a first shape on the first hydrophobic surface, and allowing the first drop to harden to form a first optical element having the first shape. The optical system may be a particle detector, and the process may optionally further include forming a light source at the semiconductor substrate configured to generate a light beam that passes through the first optical element and a cavity to a photodetector.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: March 30, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Sara Loi, Alberto Pagani
  • Patent number: 10950531
    Abstract: A semiconductor device package includes a first dielectric layer, a conductive pad and an electrical contact. The first dielectric layer has a first surface and a second surface opposite to the first surface. The conductive pad is disposed within the first dielectric layer. The conductive pad includes a first conductive layer and a barrier. The first conductive layer is adjacent to the second surface of the first dielectric layer. The first conductive layer has a first surface facing the first surface of the first dielectric layer and a second surface opposite to the first surface. The second surface of the first conductive layer is exposed from the first dielectric layer. The barrier layer is disposed on the first surface of the first conductive layer. The electrical contact is disposed on the second surface of the first conductive layer of the conductive pad.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 16, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Shun Chang, Teck-Chong Lee
  • Patent number: 10948820
    Abstract: A method for protecting a coating on a surface of a component is provided. The method includes a coating step that coats at least a portion of the component with a ceramic slurry. A projecting step projects a pattern of light onto the component with a lithographic process to expose and solidify a ceramic layer. A removing step removes unexposed portions of the ceramic slurry from the component. The ceramic layer comprises multiple stress raising elements or multiple anchoring elements.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: March 16, 2021
    Assignee: General Electric Company
    Inventors: Lacey Lynn Schwab, Kathleen Blanche Morey
  • Patent number: 10943873
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a conductive structure over the substrate. The semiconductor device structure includes first metal oxide fibers over the conductive structure. The semiconductor device structure includes a dielectric layer over the substrate and covering the conductive structure and the first metal oxide fibers. The dielectric layer fills gaps between the first metal oxide fibers.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Szu-Wei Lu, Yen-Yao Chi
  • Patent number: 10943164
    Abstract: Spoolable RFID-enabled wristbands with maximized read range. In an embodiment, a wristband comprises flexible material formed into a flag portion and a strap portion. The flag portion comprises a radio-frequency identification (RFID) inlay embedded within the material. The strap portion extends from the flag portion, and is perforated in a line along a longitudinal axis of the wristband from a distal end of the strap portion that is distal to the flag portion to a hole at a proximal end of the strap portion that is proximal to the flag portion, such that the strap portion may be torn, from the distal end to the hole at the proximal end, along the perforated line, into two sections of substantially equal dimension, which each extend from the flag portion.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: March 9, 2021
    Assignee: QUAKE GLOBAL, INC.
    Inventors: Luke Christopher Waidmann, Tom C. Lorenzana, Enrique Adrian Valdez, Chetan Shantilal Karani, Kevin W. Harris
  • Patent number: 10929585
    Abstract: A recording medium recording a program for a process, the process includes: calculating an amount of distortion in a via of a printed circuit board based on an expression using coefficient m, ??={(L×?×?t×E)/(D×T)}×m, where ?? is the amount of distortion, L is a length of the via, ? is a thermal expansion coefficient of a base material, ?t is a temperature change of an environment, E is a Young's modulus, D is a diameter of the via, and T is a thickness of plating in the via; and calculating a lifetime of the via based on an expression, M=N/(n×365), where M is the lifetime of the via, n is a frequency of the temperature change, and N is the number of cycles of the lifetime satisfying an expression Nx=C/??.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: February 23, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Mitsunori Abe, Yoshiyuki Hiroshima, Takahiro Kitagawa, Naoki Nakamura, Akiko Matsui
  • Patent number: 10923382
    Abstract: An electrostatic chuck includes a ceramic dielectric substrate, a base plate, and a heater plate. The heater plate is provided between the ceramic dielectric substrate and the base plate. The heater plate includes first and second support plates, first and second resin layers, and a heater element. Each of the first and second resin layers is provided between the first support plate and the second support plate. The heater element includes first and second electrically conductive portions. The first electrically conductive portion is provided between the first resin layer and the second resin layer. The second electrically conductive portion is separated from the first electrically conductive portion in an in-plane direction. The first resin layer contacts the second resin layer between the first electrically conductive portion and the second electrically conductive portion.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: February 16, 2021
    Assignee: Toto Ltd.
    Inventors: Jumpei Uefuji, Hitoshi Sasaki, Kosuke Yamaguchi, Kengo Maehata, Yuichi Yoshii
  • Patent number: 10903543
    Abstract: Signal transmission structures within a printed circuit are formed to have reduced loss by making specific accommodations to reduce the surface roughness of an adjacent power plane, and thereby reducing the effects of magnetically induced currents. The power plane structure will retain sufficient surface roughness to accommodate manufacturing operations, while also contributing to reduced signal transmission losses in the adjacent signal transmission structure. The transmission structures thereby being capable of more efficiently transmitting high speed signals without undesired attenuation and loss.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: January 26, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Andy Becker
  • Patent number: 10890669
    Abstract: A flexible organic X-ray detector, an imaging system including the flexible organic detector and methods for fabricating a flexible organic X-ray detector having a layered structure are presented. The detector includes a flexible substrate and a thin glass substrate operatively coupled to the flexible substrate. Further, the detector includes a thin film transistor array disposed on the thin glass substrate. Additionally, the detector includes an organic photodiode including one or more layers disposed on the thin film transistor array. Moreover, the detector includes a scintillator layer disposed on the organic photodiode.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: January 12, 2021
    Assignee: General Electric Company
    Inventors: Ri-an Zhao, Aaron Judy Couture
  • Patent number: 10886146
    Abstract: There is provided a copper foil provided with a carrier providing excellent chemical resistance against the copper flash etching solution during the formation of the wiring layer on the surface of the coreless support and excellent visibility of the wiring layer due to high contrast to the antireflective layer in image inspection after copper flash etching. The copper foil provided with a carrier comprises a carrier; a release layer provided on the carrier; an antireflective layer provided on the release layer and composed of at least one metal selected from the group consisting of Cr, W, Ta, Ti, Ni and Mo; and an extremely-thin copper layer provided on the antireflective layer; wherein at least the surface adjacent to the extremely-thin copper layer of the antireflective layer comprises an aggregate of metal particles.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: January 5, 2021
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventor: Yoshinori Matsuura
  • Patent number: 10875997
    Abstract: This invention relates to epoxy resin formulations for preforms to be used in molding processes, especially resin transfer molding processes and to methods for preparing the performs. The epoxy formulation is based on liquid or solid epoxy resins blended, with medium to high molecular weight, phenoxy resins. These formulations are highly compatible with epoxy curable injection resins, and more over are reacted in the polymeric matrix, without reducing the glass transition temperature (Tg) of the cured composite material.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: December 29, 2020
    Assignee: HEXION INC.
    Inventors: Helga De Velder, Alain Leroy, Jean Riviere, Eckhard Rühle
  • Patent number: 10872655
    Abstract: Instant optical DRAM data erasure can be performed. In wafer level packaging (chip scale package) die is usually on top (flip-chip) and metal interconnections does not interfere with penetrating light during chip illumination. IR light penetrates through chip's thin epoxy on top and deeply into die. Light is absorbed in the die, near active layer, generating electron-hole pairs. Electron-hole pairs diffuse to chip active layer and generate discharging photocurrents in DRAM capacitors.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: December 22, 2020
    Inventor: Goran Krilic