Including Metal Layer Patents (Class 428/209)
  • Patent number: 10993331
    Abstract: High-speed interconnects for printed circuit boards and methods for forming the high-speed interconnects are described. A high-speed interconnect may comprise a region of a conductive film having a reduced surface roughness and one or more regions that have been treated for improved bonding with an adjacent insulating layer. Regions of reduced roughness may be used to carry high data rate signals within PCBs. Regions treated for bonding may include a roughened surface, adhesion-promoting chemical treatment, and/or material deposited to improve wettability of the surface and/or adhesion to a cured insulator.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: April 27, 2021
    Assignee: Amphenol Corporation
    Inventors: Arthur E. Harkness, Jr., Eva M. Kenny-McDermott, Paul W. Farineau, Raymond A. Lavallee, Michael Fancher
  • Patent number: 10985225
    Abstract: The present disclosure provides a method for manufacturing an OLED display substrate, including a step of forming a pattern of a pixel definition layer on a substrate through a patterning process. A bottom wall of the pixel definition layer is formed on the substrate, a top wall of the pixel definition layer is arranged parallel to the bottom wall, and a side wall of the pixel definition layer is angled relative to the top wall at an acute angle.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: April 20, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Feng Zhang, Wenqu Liu, Zhijun Lv, Liwen Dong, Shizheng Zhang, Ning Dang
  • Patent number: 10978702
    Abstract: A novel hybrid lithium-ion anode material based on coaxially coated Si shells on vertically aligned carbon nanofiber (CNF) arrays. The unique cup-stacking graphitic microstructure makes the bare vertically aligned CNF array an effective Li+ intercalation medium. Highly reversible Li+ intercalation and extraction were observed at high power rates. More importantly, the highly conductive and mechanically stable CNF core optionally supports a coaxially coated amorphous Si shell which has much higher theoretical specific capacity by forming fully lithiated alloy. Addition of surface effect dominant sites in close proximity to the intercalation medium results in a hybrid device that includes advantages of both batteries and capacitors.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: April 13, 2021
    Assignee: CF TRAVERSE LLC
    Inventor: Ronald A. Rojeski
  • Patent number: 10962659
    Abstract: A process for manufacturing an optical system includes forming a first hydrophobic surface at a semiconductor substrate, providing a first drop of transparent material having a first shape on the first hydrophobic surface, and allowing the first drop to harden to form a first optical element having the first shape. The optical system may be a particle detector, and the process may optionally further include forming a light source at the semiconductor substrate configured to generate a light beam that passes through the first optical element and a cavity to a photodetector.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: March 30, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Sara Loi, Alberto Pagani
  • Patent number: 10950531
    Abstract: A semiconductor device package includes a first dielectric layer, a conductive pad and an electrical contact. The first dielectric layer has a first surface and a second surface opposite to the first surface. The conductive pad is disposed within the first dielectric layer. The conductive pad includes a first conductive layer and a barrier. The first conductive layer is adjacent to the second surface of the first dielectric layer. The first conductive layer has a first surface facing the first surface of the first dielectric layer and a second surface opposite to the first surface. The second surface of the first conductive layer is exposed from the first dielectric layer. The barrier layer is disposed on the first surface of the first conductive layer. The electrical contact is disposed on the second surface of the first conductive layer of the conductive pad.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 16, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Shun Chang, Teck-Chong Lee
  • Patent number: 10948820
    Abstract: A method for protecting a coating on a surface of a component is provided. The method includes a coating step that coats at least a portion of the component with a ceramic slurry. A projecting step projects a pattern of light onto the component with a lithographic process to expose and solidify a ceramic layer. A removing step removes unexposed portions of the ceramic slurry from the component. The ceramic layer comprises multiple stress raising elements or multiple anchoring elements.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: March 16, 2021
    Assignee: General Electric Company
    Inventors: Lacey Lynn Schwab, Kathleen Blanche Morey
  • Patent number: 10943164
    Abstract: Spoolable RFID-enabled wristbands with maximized read range. In an embodiment, a wristband comprises flexible material formed into a flag portion and a strap portion. The flag portion comprises a radio-frequency identification (RFID) inlay embedded within the material. The strap portion extends from the flag portion, and is perforated in a line along a longitudinal axis of the wristband from a distal end of the strap portion that is distal to the flag portion to a hole at a proximal end of the strap portion that is proximal to the flag portion, such that the strap portion may be torn, from the distal end to the hole at the proximal end, along the perforated line, into two sections of substantially equal dimension, which each extend from the flag portion.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: March 9, 2021
    Assignee: QUAKE GLOBAL, INC.
    Inventors: Luke Christopher Waidmann, Tom C. Lorenzana, Enrique Adrian Valdez, Chetan Shantilal Karani, Kevin W. Harris
  • Patent number: 10943873
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a conductive structure over the substrate. The semiconductor device structure includes first metal oxide fibers over the conductive structure. The semiconductor device structure includes a dielectric layer over the substrate and covering the conductive structure and the first metal oxide fibers. The dielectric layer fills gaps between the first metal oxide fibers.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Szu-Wei Lu, Yen-Yao Chi
  • Patent number: 10929585
    Abstract: A recording medium recording a program for a process, the process includes: calculating an amount of distortion in a via of a printed circuit board based on an expression using coefficient m, ??={(L×?×?t×E)/(D×T)}×m, where ?? is the amount of distortion, L is a length of the via, ? is a thermal expansion coefficient of a base material, ?t is a temperature change of an environment, E is a Young's modulus, D is a diameter of the via, and T is a thickness of plating in the via; and calculating a lifetime of the via based on an expression, M=N/(n×365), where M is the lifetime of the via, n is a frequency of the temperature change, and N is the number of cycles of the lifetime satisfying an expression Nx=C/??.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: February 23, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Mitsunori Abe, Yoshiyuki Hiroshima, Takahiro Kitagawa, Naoki Nakamura, Akiko Matsui
  • Patent number: 10923382
    Abstract: An electrostatic chuck includes a ceramic dielectric substrate, a base plate, and a heater plate. The heater plate is provided between the ceramic dielectric substrate and the base plate. The heater plate includes first and second support plates, first and second resin layers, and a heater element. Each of the first and second resin layers is provided between the first support plate and the second support plate. The heater element includes first and second electrically conductive portions. The first electrically conductive portion is provided between the first resin layer and the second resin layer. The second electrically conductive portion is separated from the first electrically conductive portion in an in-plane direction. The first resin layer contacts the second resin layer between the first electrically conductive portion and the second electrically conductive portion.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: February 16, 2021
    Assignee: Toto Ltd.
    Inventors: Jumpei Uefuji, Hitoshi Sasaki, Kosuke Yamaguchi, Kengo Maehata, Yuichi Yoshii
  • Patent number: 10903543
    Abstract: Signal transmission structures within a printed circuit are formed to have reduced loss by making specific accommodations to reduce the surface roughness of an adjacent power plane, and thereby reducing the effects of magnetically induced currents. The power plane structure will retain sufficient surface roughness to accommodate manufacturing operations, while also contributing to reduced signal transmission losses in the adjacent signal transmission structure. The transmission structures thereby being capable of more efficiently transmitting high speed signals without undesired attenuation and loss.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: January 26, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Andy Becker
  • Patent number: 10890669
    Abstract: A flexible organic X-ray detector, an imaging system including the flexible organic detector and methods for fabricating a flexible organic X-ray detector having a layered structure are presented. The detector includes a flexible substrate and a thin glass substrate operatively coupled to the flexible substrate. Further, the detector includes a thin film transistor array disposed on the thin glass substrate. Additionally, the detector includes an organic photodiode including one or more layers disposed on the thin film transistor array. Moreover, the detector includes a scintillator layer disposed on the organic photodiode.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: January 12, 2021
    Assignee: General Electric Company
    Inventors: Ri-an Zhao, Aaron Judy Couture
  • Patent number: 10886146
    Abstract: There is provided a copper foil provided with a carrier providing excellent chemical resistance against the copper flash etching solution during the formation of the wiring layer on the surface of the coreless support and excellent visibility of the wiring layer due to high contrast to the antireflective layer in image inspection after copper flash etching. The copper foil provided with a carrier comprises a carrier; a release layer provided on the carrier; an antireflective layer provided on the release layer and composed of at least one metal selected from the group consisting of Cr, W, Ta, Ti, Ni and Mo; and an extremely-thin copper layer provided on the antireflective layer; wherein at least the surface adjacent to the extremely-thin copper layer of the antireflective layer comprises an aggregate of metal particles.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: January 5, 2021
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventor: Yoshinori Matsuura
  • Patent number: 10875997
    Abstract: This invention relates to epoxy resin formulations for preforms to be used in molding processes, especially resin transfer molding processes and to methods for preparing the performs. The epoxy formulation is based on liquid or solid epoxy resins blended, with medium to high molecular weight, phenoxy resins. These formulations are highly compatible with epoxy curable injection resins, and more over are reacted in the polymeric matrix, without reducing the glass transition temperature (Tg) of the cured composite material.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: December 29, 2020
    Assignee: HEXION INC.
    Inventors: Helga De Velder, Alain Leroy, Jean Riviere, Eckhard Rühle
  • Patent number: 10872655
    Abstract: Instant optical DRAM data erasure can be performed. In wafer level packaging (chip scale package) die is usually on top (flip-chip) and metal interconnections does not interfere with penetrating light during chip illumination. IR light penetrates through chip's thin epoxy on top and deeply into die. Light is absorbed in the die, near active layer, generating electron-hole pairs. Electron-hole pairs diffuse to chip active layer and generate discharging photocurrents in DRAM capacitors.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: December 22, 2020
    Inventor: Goran Krilic
  • Patent number: 10861985
    Abstract: The present invention provides a thick-film paste composition for printing the front side of a solar cell device having one or more insulating layers. The thick-film paste comprises an electrically conductive metal and a dual-frit oxide composition dispersed in an organic medium.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: December 8, 2020
    Assignee: DuPont Electronics, Inc.
    Inventors: Kenneth Warren Hang, Kathryn Lynn Goetschius, Yusuke Tachibana, Paul Douglas Vernooy
  • Patent number: 10852873
    Abstract: The present disclosure relates to pressure-sensitive detection apparatus. One example apparatus includes a pressure sensor array located in a touch display screen. One half-bridge circuit is constituted in each row of the pressure sensor array. When there is a touch input signal on the touch display screen, a first half-bridge circuit and a second half-bridge circuit corresponding to a touch location of the touch input signal output signals. A deformation amount generated when pressure is applied to a first pressure sensor component in the first half-bridge circuit is less than a deformation amount generated when the pressure is applied to a second pressure sensor component in the first half-bridge circuit, and a deformation amount generated when the pressure is applied to a first pressure sensor component in the second half-bridge circuit is greater than a deformation amount generated when the pressure is applied to a second pressure sensor component in the second half-bridge circuit.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 1, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jiang Liu, Jingdong Wu, Zeshi Zhang
  • Patent number: 10836680
    Abstract: A glass ceramic material is disclosed that includes a residual glass, and a crystalline phase that includes a yoshiokaite phase. The yoshiokaite phase constitutes a main crystalline phase of the glass ceramic material. A method for making a glass ceramic material is also disclosed that includes heat treating frit glass to form the glass ceramic material, wherein the frit glass comprises: SiO2 from 15 mol % to 37 mol %; Al2O3 from 40 mol % to 47 mol %; and CaO from 20 mol % to 30 mol %.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: November 17, 2020
    Assignee: Corning Incorporated
    Inventor: Marie Jacqueline Monique Comte
  • Patent number: 10842027
    Abstract: A base material for a printed circuit board includes: an insulating base film; a sintered layer that is layered on at least one side surface of the base film and that is formed of a plurality of sintered metal particles; an electroless plating layer that is layered on a surface of the sintered layer that is opposite to the base film; and an electroplating layer that is layered on a surface of the electroless plating layer that is opposite to the sintered layer, wherein an arithmetic mean height Sa of the surface of the electroless plating layer opposite to the sintered layer is greater than or equal to 0.001 ?m and less than or equal to 0.5 ?m.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: November 17, 2020
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Kazuhiro Miyata, Takashi Kasuga, Yoshio Oka, Hiroshi Ueda
  • Patent number: 10840067
    Abstract: A fluorine plasma resistant coating on a substrate being a component in a semiconductor manufacturing system is disclosed. In one embodiment the composition includes an AlON coating that overlies a substrate, and an optional yttria coating layer that overlies the AlON coating, with a total coating thickness of about 5-6 microns.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: November 17, 2020
    Assignee: ENTEGRIS, INC.
    Inventor: Nilesh Gunda
  • Patent number: 10827622
    Abstract: Wiring boards, including an embedded type wiring boards and flexible wiring boards, may be produce by: (1) preparing a wiring layer-attached base including a base and a wiring layer provided on at least one surface of the base, (2) laminating an adhesive sheet including (i) a thermosetting resin composition layer and (ii) a resin film layer on the wiring layer-attached base so that the wiring layer will be embedded in (i) the thermosetting resin composition layer and performing thermal curing to form an insulating layer, (3) forming via holes in the insulating layer, (4) forming a conductor layer, and (5) removing the base.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: November 3, 2020
    Assignee: Ajinomoto Co., Inc.
    Inventors: Shigeo Nakamura, Chihiro Fujiwara
  • Patent number: 10826136
    Abstract: A battery pack comprises a stack of battery-board assemblies. Each battery-board assembly includes a circuit board, an electrical connector mounted on the circuit board, and a battery cell secured to a side of the circuit board. The battery cells are sandwiched between the circuit boards and the connectors are interconnected. The circuit boards and the connectors electrically connect the battery cells together.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: November 3, 2020
    Assignee: The Boeing Company
    Inventor: Suhat Limvorapun
  • Patent number: 10821704
    Abstract: The invention relates to a substrate (1) for electrical circuits comprising at least one first composite layer (2) which is produced by means of roll cladding and, after said roll cladding, has at least one copper layer (3) and an aluminium layer (4) attached thereon, wherein at least the surface side of the aluminium layer (4) facing away from the copper layer (3) is anodized for the generation of an anodic or insulating layer (5) made of aluminium oxide, and wherein the anodic or insulating layer (5) made of aluminium oxide is connected to a metal layer (7) or at least one second composite layer (2?) or at least one paper-ceramic layer (11) via at least one adhesive layer (6, 6?).
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: November 3, 2020
    Assignee: ROGERS GERMANY GMBH
    Inventors: Andreas Meyer, Karsten Schmidt
  • Patent number: 10818808
    Abstract: A method of producing a nanograin material wherein a hole-transporting surfactant is injected into an InP/ZnS dispersion solution, and the surface of an InP/ZnS quantum dot is covered with the hole-transporting surfactant to prepare an InP/ZnS dispersion solution with a hole-transporting surfactant. The InP/ZnS dispersion solution with a hole-transporting surfactant is then applied to a substrate using a spin coating process of the like to form a quantum dot layer with a hole-transporting surfactant having one or more layers. Then, a dispersion solution (replacement solution) containing an electron-transporting surfactant is prepared. The substrate having the quantum dot layer with a hole-transporting surfactant is immersed in the replacement solution for a predetermined time, and part of the hole-transporting surfactant is replaced with the electron-transporting surfactant to form a quantum dot layer having one or more layer.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: October 27, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Koji Murayama
  • Patent number: 10784322
    Abstract: Embodiments of the present disclosure provide an array substrate, a manufacturing method, and a display device. The array substrate comprises: a pixel define layer located on a base substrate, the pixel define layer having a hollow for defining a sub-pixel light emitting area, and a light emitting functional layer located in the hollow, wherein, the pixel define layer has protrusion structures on one or more sides facing the hollow.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 22, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Qing Dai
  • Patent number: 10779401
    Abstract: A flexible printed circuit board (FPC) is provided, which includes a dielectric layer. Copper foil layers and cover layers are sequentially provided from inside to outside on both sides of the dielectric layer. The cover layer on one side of the dielectric layer is provided with a reinforced plate. The FPC includes a bending area. The copper foil layer and the cover layer on one side at the bending area and the reinforced plate are each provided with a windowed area. Edges of the copper foil layer, the cover layer, and the reinforced plate that are defined by windowed areas are not in one vertical plane. In the structure, stress concentrations in the bending area are distributed, so that the tearing risk to the edges of the bending area is reduced, and the bending resistance of the flexible circuit board is enhanced.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: September 15, 2020
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: Yan Chen
  • Patent number: 10772220
    Abstract: A printed circuit board (PCB) has multiple layers, where select portions of inner layer circuitry, referred to as inner core circuitry, are covered by a coverlay material and the covered inner core circuitry is exposed from the remaining layers of the PCB. The PCB having covered inner core circuitry is formed using a dummy core plus coverlay process. The select inner core circuitry is part of an inner core. The inner core corresponding to the covered inner core circuitry forms a flexible PCB portion. The flexible PCB portion is an extension of the remaining adjacent multiple layer PCB. The remaining portion of the multiple layer PCB is rigid. The inner core is common to both the flexible PCB portion and the remaining rigid PCB portion.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: September 8, 2020
    Assignee: Multek Technologies Limited
    Inventors: J L Zhou, Pui Yin Yu
  • Patent number: 10765005
    Abstract: A method of manufacturing a component carrier is disclosed. The method includes galvanically depositing at least part of at least one electrically conductive pillar on a component, and inserting the at least one electrically conductive pillar and an electrically insulating layer structure into one another.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: September 1, 2020
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Hannes Stahr, Hannes Voraberger, Andreas Zluc, Bettina Schuster
  • Patent number: 10756589
    Abstract: A motor coil includes a magnet structure, and a laminated coil substrate formed on the magnet structure and including coil substrates and adhesive layers alternately laminated. The coil substrates are formed by folding a printed wiring board including a resin substrate, a first conductor layer formed on a first surface of the resin substrate and forming coils, and a second conductor layer formed on a second surface on the opposite side with respect to the first surface and forming coils, and the adhesive layers include an adhesive layer including a magnetic sheet.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: August 25, 2020
    Assignee: IBIDEN CO., LTD.
    Inventors: Haruhiko Morita, Shinobu Kato, Hitoshi Miwa, Hisashi Kato, Toshihiko Yokomaku
  • Patent number: 10748980
    Abstract: A display device includes a substrate including a display region, a pad region spaced apart from the display region, and a bending region between the display region and the pad region. A plurality of pixel structures is positioned in the display region of the substrate. A plurality of pad wirings is positioned in the pad region of the substrate. A plurality of connection wirings electrically connect the pad wirings to the pixel structures. The connection wirings include a plurality of notches in the bending region.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Seil Cho
  • Patent number: 10747073
    Abstract: A display device includes a display panel, a flexible film, and a conductive adhesion member. The display panel includes a first substrate which includes a pad electrode connected to a signal line, a second substrate, and a metal electrode electrically connected to the pad electrode and on a side surface of the display panel. The flexible film includes a line electrode electrically connected to the metal electrode and attached to the side surface of the display panel. The conductive adhesion member includes a connection electrode electrically connecting the metal electrode to the line electrode. The conductive adhesion member attaches the flexible film to the surface of the display panel. The connection electrode includes the solder particles in melted form.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Youngmin Cho, Minseok Kim, Jonghwan Kim, Yongyoul Cho
  • Patent number: 10741466
    Abstract: A first packaged semiconductor device is provided. The first packaged semiconductor device includes a first semiconductor die having a first terminal, a first electrically conductive lead that is electrically connected to the first terminal, and a first electrically insulating mold compound that encapsulates the first semiconductor die and exposes an end portion of the first lead at an outer surface of the first mold compound. A conductive track is formed in the outer surface of the first mold compound. Forming the conductive track includes activating a portion of the outer surface of the first mold compound for an electroless plating process, and performing the electroless plating process so as to form an electrically conductive material only within the activated portion of the outer surface of the first mold compound.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: August 11, 2020
    Assignee: Infineon Technologies AG
    Inventors: Cher Hau Danny Koh, Norliza Morban, Yong Chern Poh, Khay Chwan Saw, Si Hao Vincent Yeo
  • Patent number: 10741322
    Abstract: Decorative, multi-layer surfacing materials, surfaces made therewith, methods of making such and wireless power transmission using the same, which surfacing materials comprise: a first resin-impregnated paper layer and a second resin-impregnated paper layer, and a first conductive material having a first terminus and a second terminus and capable of carrying an electric current from the first terminus to the second terminus; wherein the first conductive material is disposed on a first surface of the first resin-impregnated paper layer; wherein the first resin-impregnated paper layer and the second resin-impregnated paper layer are disposed in a stacked and compressed such that the first conductive material is encapsulated between the first resin-impregnated paper layer and the second resin-impregnated paper layer; and wherein at least one of the first resin-impregnated paper layer, the second resin-impregnated paper layer or an optional additional resin-impregnated paper layer is a decorative layer.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: August 11, 2020
    Assignee: THE DILLER CORPORATION
    Inventors: Kevin O'Brien, Bryce Cole, Robert Jacob Kramer
  • Patent number: 10714703
    Abstract: An organic light emitting diode (OLED) display includes: a substrate including a plurality of organic light emitting elements; an adhesive member on at least a portion of an upper surface of the substrate; a flexible circuit board adhered to the upper surface of the adhesive member and having a portion bent to be mounted to a lower surface of the substrate; and a light blocking member at the upper surface of the substrate, wherein the light blocking member is laterally offset from the adhesive member.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: July 14, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young-Min You, Dae-Kil Park
  • Patent number: 10709017
    Abstract: A multilayer ceramic substrate includes: a plurality of ceramic layers 300a, 300b stacked together; a via hole 400a, 400b provided in each of the plurality of ceramic layers, the via holes of the plurality of ceramic layers being connected together in a layer stacking direction of the plurality of ceramic layers; a via wire 406a, 406b including an electrical conductor filled into each of the via holes; a first conductor 404a, 404b provided on an upper surface of at least one of the plurality of ceramic layers, the first conductor having an annular or partially annular shape surrounding the via wire; and a second conductor 403a, 403b including a first portion and a second portion, the first portion being located outside the first conductor on the upper surface of the at least one ceramic layer, the second portion overlying the first conductor, and an inner rim of the second portion being located outside an inner rim of the first conductor, wherein a thickness of the first conductor 404a, 404b is greater than a
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: July 7, 2020
    Assignee: HITACHI METALS, LTD.
    Inventor: Kenji Hayashi
  • Patent number: 10701811
    Abstract: A surface-treated copper foil of the present disclosure includes a copper foil substrate, at least one surface of which has a surface treatment coat including at least a roughening-treated surface on which roughening particles are formed. Observation of a cross-section of the surface-treated copper foil with a scanning electron microscope shows that on a surface of the surface treatment coat, a standard deviation of the particle height of the roughening particles is 0.16 ?m or more and 0.30 ?m or less, and an average value of the ratio of the particle height to the particle width (particle height/particle width) of the roughening particles is 2.30 or more and 4.00 or less.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: June 30, 2020
    Assignees: Furukawa Electric Co., Ltd., Murata Manufacturing Co., Ltd.
    Inventors: Takeo Uno, Yuko Okuno, Takahiro Tsuruta, Yoshimasa Nishi, Sunao Fukutake
  • Patent number: 10681473
    Abstract: Some preferred embodiments include a microphone system for receiving sound waves, the microphone including a back plate, a radiation plate, first and second electrodes, first and second insulator layers, a power source and a microphone controller. The radiation plate is clamped to the back plate so that there is a hermetically sealed circular gap between the radiation plate and the back plate. The first electrode is fixedly attached to a side of the back plate proximate to the gap. The second electrode is fixedly attached to a side of the radiation plate. The insulator layers are attached to the back plate and/or the radiation plate, on respective gap sides thereof, so that the insulator layers are between the electrodes. The microphone controller is configured to use the power source to drive the microphone at a selected operating point comprising normalized static mechanical force, bias voltage, and relative bias voltage level.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: June 9, 2020
    Inventors: Hayrettin Koymen, Abdullah Atalar
  • Patent number: 10670440
    Abstract: In order to provide a flow measuring device high in thermal responsiveness, the flow measuring device includes a temperature detecting element 2 for temperature detection, and a conductive metal lead frame 3 that supports and fixes the temperature detecting element. Of the metal lead frame, a part of the metal lead frame mounted with the temperature detecting element has a portion which is thinner than the thickness of the other metal lead frame or narrower than the width of the other metal lead frame.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: June 2, 2020
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Shinobu Tashiro, Keiji Hanzawa, Noboru Tokuyasu, Takeshi Morino, Ryosuke Doi
  • Patent number: 10670472
    Abstract: A temperature measuring mask includes: a substrate 10; a temperature sensor 11 being provided to the substrate 10, and being capable of sensing a temperature inside a charged particle beam lithography device 4; a circuit board 12 being provided to the substrate 10, and including a measuring circuit 121A that measures the temperature using the temperature sensor 11 and a storage device 121B that stores measurement data of the measured temperature; a secondary cell 13 being provided to the substrate 10, and supplying electric power to the circuit 121A; and a photoelectric cell 14 being provided to the substrate 10, and generating electric power by being irradiated with an energy beam to charge the secondary cell 13.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: June 2, 2020
    Assignee: NuFlare Technology, Inc.
    Inventor: Kota Fujiwara
  • Patent number: 10645808
    Abstract: Dielectric such as polyether ether ketone may be used in forming radio-frequency flexible printed circuits. Filler may be incorporated into the dielectric to adjust the coefficient of thermal expansion of the flexible printed circuit. One or more layers of the flexible printed circuit may be unfilled and one or more layers of the flexible printed circuit may be filled. Antennas may be formed from metal traces on the flexible printed circuit, metal electronic device housing structures, or other conductive structures. A transmission line on the flexible printed circuit may couple radio-frequency transceiver circuitry in an electronic device to an antenna. A flexible printed circuit may have a portion with enhanced bendability in a location that overlaps a bend region. The enhanced bendability region may have less filler than other portions of the flexible printed circuit.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: May 5, 2020
    Assignee: Apple Inc.
    Inventors: Kevin M. Froese, Qian Zhang, Paul Choiniere, Derek C. Krass
  • Patent number: 10629466
    Abstract: Provided is an electrostatic chuck device which includes: an electrostatic chuck section having one main surface serving as a placing surface on which a plate-shaped sample is placed, and having a built-in internal electrode for electrostatic attraction; a first adhesion layer which contains spacers and a silicone adhesive and in which a layer thickness D is in a range of 3 to 25 ?m and a ratio (?S/D) between the layer thickness D and an average particle diameter ?S of the spacers is in a range of 0.1 to 1.0; a plurality of heating members bonded to the surface on the side opposite to the placing surface of the electrostatic chuck section in a pattern having a gap with respect to one another by the first adhesion layer; a second adhesion layer which contains a silicone adhesive; and a base section having a function of cooling the electrostatic chuck section.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: April 21, 2020
    Assignee: SUMITOMO OSAKA CEMENT CO., LTD.
    Inventors: Tomomi Ito, Yukio Miura
  • Patent number: 10629364
    Abstract: An inductor includes a body in which is disposed a coil formed as a plurality of coil patterns connected by one or more via(s). Each via includes a first conductive layer and a second conductive layer formed on the first conductive layer, and a distance between portions of coil patterns connected by the via in the body is greater than a distance between other portions of the coil patterns in the body. Methods of forming inductors having vias including first and second conductive layers are also provided.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Se Woong Paeng, Jong Seok Bae, Soo Yeol Kim
  • Patent number: 10631412
    Abstract: Prepregs having a UV curable resin layer located adjacent to a first thermally curable resin layer or sandwiched between first and second thermally curable resin layers wherein the UV curable resin layer is uncured or partially cured as well as methods for preparing laminates using the prepregs wherein the laminate includes at least one UV curable resin encapsulated electrical component.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: April 21, 2020
    Assignee: ISOLA USA CORP.
    Inventor: Roland Schönholz
  • Patent number: 10613545
    Abstract: A passive infra-red guidance system and method for augmenting operation of an autonomous vehicle on a roadway includes at least one forward-looking infra-red imaging sensor mounted on the vehicle in operative communication with an image processor tied into the vehicle's operational system. The system determines the left and right edges of the roadway using thermal imaging, and then determines the centerline of the travel lane in which the vehicle is travelling based on the determined left and right edges of the roadway. The system then compares the determined centerline of the travel lane with the actual position of the vehicle and identifies any adjustment needed for the vehicle's position based on the comparison. The left and right edge determination may comprise identifying a difference between a thermal signature representative of the roadway and a thermal signature representative of a non-roadway portion that is located proximate to the roadway portion.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: April 7, 2020
    Inventor: Arnold Chase
  • Patent number: 10612766
    Abstract: A laminate having an electroluminescent element disposed within the laminate is disclosed. The laminate includes a first paper layer having at least first and second vias through the first paper layer; a first electrically-conductive layer comprising an electrically-conductive material, the first electrically-conductive layer being disposed over the first paper layer; a dielectric layer disposed over the first electrically-conductive layer; a light emissive layer comprising an electroluminescent material, the light emissive layer being disposed over the dielectric layer; a second electrically-conductive layer comprising a translucent electrically-conductive material, the second electrically-conductive layer being disposed over the light emissive layer; an insulating layer disposed over the second electrically-conductive layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: April 7, 2020
    Assignee: THE DILLER CORPORATION
    Inventor: Robert Jacob Kramer
  • Patent number: 10617001
    Abstract: An electronic circuit, including a substrate made of a first polymer having a first glass transition temperature lower than 200° C., the substrate having first and second opposite surfaces; a first layer or first tracks of a second polymer on the first surface; a second layer or second tracks of the second polymer or of a third polymer on the second surface, the second and third polymers being different from the first polymer and having a second glass transition temperature higher than 200° C.; and third electrically-conductive tracks on the first layer or the first tracks.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: April 7, 2020
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Olivier Haon, Abdelkader Aliane, Mohammed Benwadih
  • Patent number: 10616999
    Abstract: A printed circuit board (PCB) incorporates at least one damping layer or section. The at least one damping layer is incorporated in the PCB to absorb vibrations or oscillations that may be conveyed to the PCB. Such vibrations or oscillations may be generated by one or more electrical components coupled to the PCB. The damping layer is disposed to prevent the PCB from audibly vibrating when the electrical components associated with the PCB are caused to vibrate or pulsate under a voltage load.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: April 7, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Brian J. Toleno, Marianne Elizabeth La Ford, Michael Nikkhoo, Igor Markovsky
  • Patent number: 10604640
    Abstract: Disclosed is a resin composition which comprises a compound with at least two DOPO groups or a combination thereof as the flame retardant and an aliphatic long-chain maleimide compound. The resin composition is useful for the preparation of various articles, such as a prepreg, a resin film, a resin film with copper foil, a laminate or a printed circuit board, achieving at least one, more or all properties improved of laminate formability, reliability of multiple laminations, chemical resistance, thermal resistance, dielectric constant, dissipation factor, interlayer bonding strength, storage modulus and so on.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: March 31, 2020
    Assignee: ELITE MATERIAL CO., LTD.
    Inventor: Chen-Yu Hsieh
  • Patent number: 10586748
    Abstract: A printed circuit board (PCB) includes an insulating layer with an upper surface and a lower surface opposite to the upper surface; a first conductive pattern on the upper surface of the insulating layer; a second conductive pattern on the lower surface of the insulating layer; an aluminum pattern that covers at least a portion of an upper surface of the first conductive pattern; and a first passivation layer that covers at least a portion of sides of the first conductive pattern and that prevents diffusion into the first conductive pattern.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: March 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Soo-Jae Park
  • Patent number: 10588222
    Abstract: A carbene-coated metal foil is produced by applying an N-heterocyclic carbene (NHC) compound to one or more surfaces of a metal foil (e.g., an electrodeposited copper foil having a surface that is smooth and non-oxidized). The NHC compound contains a matrix-reactive pendant group that includes at least one of a vinyl-, allyl-, acrylic-, methacrylic-, styrenic-, amine-, amide- and epoxy-containing moiety capable of reacting with a base polymer (e.g., a vinyl-containing resin such as a polyphenylene oxide/triallyl-isocyanurate (PPO/TAIC) composition). The NHC compound may be synthesized by, for example, reacting a halogenated imidazolium salt (e.g., 1,3-bis(4-bromo-2,6-dimethylphenyl)-4,5-dihydro-1H-imidazol-3-ium chloride) and an organostannane having a vinyl-containing moiety (e.g., tributyl(vinyl)stannane) in the presence of a palladium catalyst.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dylan J. Boday, Joseph Kuczynski, Jason T. Wertz, Jing Zhang