Of Silicon Containing (not As Silicon Alloy) Patents (Class 428/446)
  • Patent number: 11365159
    Abstract: Provided are a coated member in which damage of a coating film can be suppressed in a high temperature environment and the coating may be performed at low cost, and a method of manufacturing the same. A coated member includes a bond coat and a top coat sequentially laminated on a substrate made of a Si-based ceramic or a SiC fiber-reinforced SiC matrix composite, wherein the top coat includes a layer composed of a mixed phase of a (Y1-aLn1a)2Si2O7 solid solution (here, Ln1 is any one of Nd, Sm, Eu, and Gd) and Y2SiO5 or a (Y1-bLn1?b)2SiO5 solid solution (here, Ln1? is any one of Nd, Sm, Eu, and Gd), or a mixed phase of a (Y1-cLn2c)2Si2O7 solid solution (here, Ln2 is any one of Sc, Yb, and Lu) and Y2SiO5 or a (Y1-dLn2?d)2SiO5 solid solution (here, Ln2? is any one of Sc, Yb, and Lu).
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: June 21, 2022
    Assignee: MITSUBISHI HEAVY INDUSTRIES AERO ENGINES, LTD.
    Inventors: Mineaki Matsumoto, Takayuki Kurimura, Kosuke Nishikawa, Tadayuki Hanada
  • Patent number: 11331402
    Abstract: The present invention relates to a solid aromatic composition capable of significantly improving the loading rate of fragrance substances, selectively loading fragrance that can be acquired during the aging procedure of blended fragrance substances, maintaining fragrance from the early stage of the loading, and improving the persistence of fragrance to have constant intensity. Furthermore, the solid aromatic composition can resolve the problem of harmfulness to the human body by reducing a powder flying phenomenon, and can be applied to various environments by improving high-temperature stability.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: May 17, 2022
    Assignee: MASSCON CO., LTD.
    Inventors: Yongeui Lee, Min Young Cheong, Chang Bin Lee
  • Patent number: 11320174
    Abstract: The present invention relates to a solar selective coating for a metal substrate comprising at least one absorber layer and at least one semi-absorber layer selected from the structures of AlTiN and AlTiSiN. In preferred embodiments, the solar selective coating according to the present invention is a double layer coating with AlTiN—AlTiN or AlTiSiN—AlTiSiN formation. The process for producing the coating includes a step of treatment of the metal substrate with a reactive magnetron sputtering system.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: May 3, 2022
    Assignee: B-PLAS-BURSA PLASTIK, METAL, INSAAT, ENERJI, MADENCILIK, JEOTERMAL, TURIZM, SIVIL HAVACILIK VE TARIM, SAN. VE TIC. A.S.
    Inventors: Mustafa K. Urgen, M. Kursat Kazmanli, M. Celal Gokcen, Eren Seckin, Serdar S. Ozbay
  • Patent number: 11276759
    Abstract: A scalable process for fabricating graphene/hexagonal boron nitride (h-BN) heterostructures is disclosed herein. The process includes (BN)XHy-radical interfacing with active sites on silicon nitride coated silicon (Si3N4/Si) surfaces for nucleation and growth of large-area, uniform and ultrathin h-BN directly on Si3N4/Si substrates (B/N atomic ratio=1:1.11±0.09). Further, monolayer graphene van der Waals bonded with the produced h-BN surface benefits from h-BN's reduced roughness (3.4 times) in comparison to Si3N4/Si. Because the reduced surface roughness leads to reduction in surface roughness scattering and charge impurity scattering, therefore an enhanced intrinsic charge carrier mobility (3 folds) for graphene on h-BN/Si3N4/Si is found.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: March 15, 2022
    Assignees: GlobalWafers Co., Ltd., Board of Trustees of the University of Illinois
    Inventors: Vikas Berry, Sanjay Behura, Phong Nguyen, Michael R. Seacrist
  • Patent number: 11270880
    Abstract: A method for depositing a silicon-containing film, the method comprising: placing a substrate comprising at least one surface feature into a flowable CVD reactor which is at a temperature of from about ?20° C. to about 400° C.; introducing into the reactor at least one silicon-containing compound having at least one acetoxy group to at least partially react the at least one silicon-containing compound to form a flowable liquid oligomer wherein the flowable liquid oligomer forms a silicon oxide coating on the substrate and at least partially fills at least a portion of the at least one surface feature. Once cured, the silicon oxide coating has a low k and excellent mechanical properties.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: March 8, 2022
    Assignee: Versum Materials US, LLC
    Inventors: Jianheng Li, Raymond Nicholas Vrtis, Robert Gordon Ridgeway, Manchao Xiao, Xinjian Lei
  • Patent number: 11251041
    Abstract: A semiconductor substrate includes a main surface inclined by a first off-angle greater than 0° from a first direction parallel to a crystal plane, with respect to the crystal plane, in a first radial direction of the main surface, and a notch disposed toward the first direction, at an edge of the main surface in the first radial direction.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: February 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In-Ji Lee, Doek-Gil Ko, Yeon-sook Kim
  • Patent number: 11198769
    Abstract: The present invention relates to plastic films with improved laser engraving capability, chemical resistance and mechanical stress, special embodiments of such films in the form of co-extrusion films, layer structures comprising such films, use of such films, as well as security documents, preferably identification documents, containing such films.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: December 14, 2021
    Assignee: Covestro Deutschland AG
    Inventors: Heinz Pudleiner, Georgios Tziovaras, Kira Planken, Stefan Janke, Christoph Köhler
  • Patent number: 11155508
    Abstract: To provide a fluorinated ether compound capable of forming a surface layer excellent in initial water/oil repellency, fingerprint stain removability, abrasion resistance and light resistance; a fluorinated ether composition and a coating liquid containing the fluorinated ether compound; an article having a surface layer excellent in initial water/oil repellency, fingerprint stain removability, abrasion resistance and light resistance and a method for producing it. A fluorinated ether compound having a poly(oxyperfluoroalkylene) chain having a unit (?) which is an oxyperfluoroalkylene unit having 5 or 6 carbon atoms, and a unit (?) which is an oxyperfluoroalkylene unit having at most 4 carbon atoms, and having at least one of a hydrolysable silyl group and a silanol group on at least one terminal of the poly(oxyperfluoroalkylene) chain via a linking group.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: October 26, 2021
    Assignee: AGC Inc.
    Inventors: Taiki Hoshino, Makoto Uno, Masahiro Ito
  • Patent number: 11130194
    Abstract: The friction stir welding tool member according to the present invention is made of a ceramic member in which a shoulder portion and a probe portion are integrally formed, wherein a root portion of the probe portion and an end portion of the shoulder portion have a curved surface shape; and the friction stir welding tool member has a ratio (R1/D) of 0.02 or more and 0.20 or less when a curvature radius of the end portion of the shoulder portion is defined as R1 (mm) and an outer diameter of the shoulder portion is defined as D (mm). In addition, the ceramic member is preferably made of a silicon nitride sintered body having a Vickers hardness of 1400 HV1 or more. According to the above-described configuration, a friction stir welding tool member having excellent durability can be provided.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: September 28, 2021
    Assignees: OSAKA UNIVERSITY, TOSHIBA MATERIALS CO., LTD.
    Inventors: Hidetoshi Fujii, Yoshiaki Morisada, Kai Funaki, Isao Ikeda, Yutaka Abe, Masahiro Kato
  • Patent number: 11124342
    Abstract: The present invention relates to a tubular packaging body formed from a flexible film having a thickness e, the ends of which are butt welded and covered by a plastic reinforcement element located on the inner surface of said tubular body and having a section defined by a width l and a height h, said tubular body being characterized in that all of the following conditions should be met: —h is greater than or equal to e, —the ratio (l·e)/h2 is between 1 and 10.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: September 21, 2021
    Assignee: AISAPACK HOLDING S.A.
    Inventors: Jacques Thomasset, Gerhard Keller
  • Patent number: 11122935
    Abstract: A ceramic deep-frying device capable of withstanding high temperatures and releasing far-infrared energy is made by grinding and mixing mullite, spodumene, energy ceramic material, ball clay, and kaolin clay into clay blank; molding the blank into ceramic green body; and sintering the green body at 1250-1320° C. for 18-24 hours. The device is completely immersed in the oil in a deep-frying vessel while leaving a gap between the device and heating pipe in the vessel or the inner bottom wall of the vessel, for enabling the oil to circulate through the through holes in the device due to temperature difference in the oil, causing the energy ceramic material to release anions and far-infrared rays that decrease van der Waals forces between oil molecules, and hence split, the oil molecules, thereby extending the service life of the oil, shortening the deep-frying time required, and lowering the oil content of deep-fried food.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: September 21, 2021
    Inventors: Chun-Shyong Lee, Sen-Kung Hsu
  • Patent number: 11117806
    Abstract: A silicon carbide-graphite composite is described, including (i) interior bulk graphite material and (ii) exterior silicon carbide matrix material, wherein the interior bulk graphite material and exterior silicon carbide matrix material inter-penetrate one another at an interfacial region therebetween, and wherein graphite is present in inclusions in the exterior silicon carbide matrix material. Such material may be formed by contacting a precursor graphite article with silicon monoxide (SiO) gas under chemical reaction conditions that are effective to convert an exterior portion of the precursor graphite article to a silicon carbide matrix material in which graphite is present in inclusions therein, and wherein the silicon carbide matrix material and interior bulk graphite material interpenetrate one another at an interfacial region therebetween.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: September 14, 2021
    Assignee: ENTEGRIS, INC.
    Inventors: Troy Scoggins, Rex Gerald Sheppard, Abuagela H. Rashed, Jonathan Loyd Burr
  • Patent number: 11090725
    Abstract: The disclosed method includes selecting a suspension ceramic or metal photocurable composition (CPC or MPC); preparing a sacrificial organic material (SOM) forming a photocurable layer destroyed by heating; for manufacturing pieces, on the working tray, forming successive layers of SOM cured by irradiation, the one or more CPC or MPC-based pieces being manufactured by machining a recess in a layer of cured SOM; depositing the CPC or MPC within the recesses; curing the CPC or MPC to obtain a hard horizontal surface level with the adjacent layer of cured SOM, when forming each recess, it is delimited by previously defined patterns, the depth(s) selected in order to ensure the continuity of the one or more pieces to be manufactured; and obtaining one or more green pieces inserted in the SOM, which are subjected to debinding by heating in order to destroy the SOM in which they are trapped.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: August 17, 2021
    Assignee: S.A.S 3DCERAM-SINTO
    Inventors: Richard Gaignon, Christophe Chaput, Marc Nguyen
  • Patent number: 11094557
    Abstract: A silicon wafer having a BMD density of 5×108/cm3 or more and 2.5×1010/cm3 or less in a region of 80 ?m to 285 ?m from the wafer surface when the silicon wafer is heat-treated at a temperature X (° C., 700° C.?X?1000° C.) for a time Y (min) and then subjected to an infrared tomography method in which the laser power is set to 50 mW and the exposure time of a detector is set to 50 msec. The time Y and the temperature X satisfy Y=7.88×1067×X?22.5.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: August 17, 2021
    Assignee: SUMCO CORPORATION
    Inventors: Toshiaki Ono, Shigeru Umeno
  • Patent number: 11072566
    Abstract: A coated substrate is provided that comprises: a substrate; and a barrier coating comprising a compound having the formula: Ln2ABO8, where Ln comprises scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, lutetium, or mixtures thereof; A comprises Si, Ti, Ge, Sn, Ce, Hf, Zr, or a combination thereof; and B comprises Mo, W, or a combination thereof. In one embodiment, B comprises Mo. A gas turbine is also provided that comprises the coated substrate described above.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: July 27, 2021
    Assignee: General Electric Company
    Inventors: Glen Harold Kirby, Thomas Grandfield Howell
  • Patent number: 11062910
    Abstract: Processes for surface treatment of a workpiece are provided. In one example implementation, a method can include performing an organic radical based surface treatment process on a workpiece. The organic radical based surface treatment process can include generating one or more species in a first chamber. The surface treatment process can include mixing one or more hydrocarbon molecules with the species to create a mixture. The mixture can include one or more organic radicals. The surface treatment process can include exposing a semiconductor material on the workpiece to the mixture in a second chamber.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: July 13, 2021
    Assignees: Mattson Technology, Inc., Beijing E-Town Semiconductor Technology Co., Ltd.
    Inventors: Michael X. Yang, Hua Chung, Xinliang Lu
  • Patent number: 11053163
    Abstract: A hydrophobic coating and a method for applying such a coating to a surface of a substrate. The method includes applying a coating composition to the surface and heating the coated surface at a cure temperature from about 300° C. to about 600° C. for a time from about 2 hours to about 48 hours. The coating composition is applied to the surface by an application method selected from the group consisting of flowing, dipping, and spraying. The coating composition comprises a yttrium compound, an additive selected from the group consisting of a cerium compound and a dispersion of yttrium oxide nanoparticles, a water-soluble polymer, and a solvent solution of de-ionized water and a water-soluble alcohol.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: July 6, 2021
    Assignee: GKN Aerospace Transparency Systems, Inc.
    Inventors: Marlowe Moncur, Christopher Rankin
  • Patent number: 11046614
    Abstract: A high purity yttria or ytterbia stabilized zirconia powder wherein a purity of the zirconia is at least 99.5 weight percent purity and with a maximum amount of specified oxide impurities.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: June 29, 2021
    Assignee: OERLIKON METCO (US) INC.
    Inventors: Jacobus Doesburg, Mitchell Dorfman, Matthew Gold, Liangde Xie
  • Patent number: 11008670
    Abstract: A manufacturing method of a SiC ingot includes a crystal growth step of growing a crystal on a principal plane having an offset angle with respect to a {0001} plane, in which, at least in a latter half growth step of the crystal growth step, after the crystal in the crystal growth step grows 7 mm or more from the principal plane, and in which, the crystal is grown by setting an acute angle, between the {0001} plane and an inclined plane which is perpendicular to a cut section cut along an offset direction and passes through both a center of a crystal growth surface and an offset downstream end portion of the crystal growth surface, to be equal to or more than an angle smaller than an offset angle by 2° and equal to or less than 8.6°.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 18, 2021
    Assignee: SHOWA DENKO K.K.
    Inventors: Yohei Fujikawa, Hideyuki Uehigashi
  • Patent number: 10994522
    Abstract: A silicone sheet 1 of the present invention is a silicone sheet that is at least one selected from a silicone gel sheet and a silicone putty sheet. The silicone sheet has a Shore 00 hardness of 75 or less. The silicone sheet is cut in a thickness direction and cut faces 5a-5m and 6a-6f of the silicone sheet are adjacent to each other without gap. The cut faces of the silicone sheet are non-tacky, and the silicone sheet is separable at the cut faces. Preferably, the cut faces have a tackiness of 0.6 N or less based on a tackiness checker. The mounting method of the present invention is a method of mounting the above silicone sheet by pick and place mounting using an automatic mounting machine.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 4, 2021
    Assignee: Fuji Polymer Industries Co., Ltd.
    Inventors: Shingo Ito, Yuta Hatazawa
  • Patent number: 10983396
    Abstract: The present invention relates to a method for producing a liquid crystal panel. The method includes curing a first reactive mesogen layer with ultraviolet light at an illuminance within a range of 40 to 90 mW/cm2. The liquid crystal panel includes a first transparent base material, a TFT layer and a first alignment film stacked in order on the first transparent base material, a second transparent base material, a color filter layer, an in-cell retardation layer, and a second alignment film stacked in order on the second transparent base material, a liquid crystal layer sandwiched between the first alignment film and the second alignment film, an out-cell retardation layer disposed on a side opposite to a color filter layer side of the second transparent base material, and a pair of linearly polarizing plates arranged so as to sandwich the first transparent base material and the out-cell retardation layer and having transmission axes orthogonal to each other.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: April 20, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Koji Murata, Akira Sakai, Yuichi Kawahira, Takako Koide, Masahiro Hasegawa, Kiyoshi Minoura
  • Patent number: 10945499
    Abstract: Proposed is a decorative element containing (a) a transparent gemstone with a faceted surface comprising convex curved regions, (b) a transparent electrically conductive layer applied to said faceted surface comprising convex curved regions, (c) a wavelength-selective layer applied (c1) to the planar side opposite to the faceted curved surface, or (c2) to the photovoltaic cell (d); (d) a photovoltaic cell; and (e) a touch-sensitive electronic circuitry.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: March 16, 2021
    Assignee: D. Swarovski KG
    Inventors: Christof Gapp, Martin Scholz, Annemarie Leber, Mathias Mair, Franz Lexer, Ernst Altenberger
  • Patent number: 10941083
    Abstract: A part coated in a protective coating forms a thermal barrier and includes a ceramic first layer. The protective coating further includes a second layer present on the first layer and including a majority by weight of a first feldspar mineral having a melting temperature higher than or equal to 1010° C. and presenting a thickness greater than or equal to 10 ?m.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: March 9, 2021
    Assignee: SAFRAN AIRCRAFT ENGINES
    Inventors: Pascal Fabrice Bilhe, André Hubert Louis Malie
  • Patent number: 10934462
    Abstract: The invention describes compositions that include amine-containing silsesquioxane or an amine-containing alkyltrialkoxysilane and a thermoplastic elastomer as well as methods of preparation of the compositions that are useful as self-bonding adhesives for various substrates.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: March 2, 2021
    Assignee: Saint-Gobain Performance Plastics Corporatoin
    Inventor: Duan Li Ou
  • Patent number: 10927445
    Abstract: Provided is a surface-coated cutting tool including: a tool body (3) and a hard coating layer on the tool body (3). The hard coating layer has an alternate laminate structure of A (1) and B layers (2). The A layer (1) is a Ti and Al complex nitride layer satisfying a compositional formula: (Ti1-zAlz)N, 0.4?z?0.7. The B layer (2) is a Cr, Al and M complex nitride layer satisfying a compositional formula: (Cr1-x-yAlxMy)N, 0.03?x?0.4 and 0?y?0.05. The value of a ratio tB/tA of the average layer thickness of the B layer (2) to the average layer thickness of the A layer (1) satisfies 0.67 to 2.0. The lattice constant a(?) of crystal grains of the hard coating layer satisfies 4.10?a?4.20. The ratio of I(200) to I(111) satisfies 2.0?I(200)/I(111)?10.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: February 23, 2021
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Shun Sato, Masakuni Takahashi
  • Patent number: 10892334
    Abstract: An n-type SiC single crystal substrate of the present invention is provided which is a substrate doped with both a donor and an acceptor, and has a difference between a donor concentration and an acceptor concentration in an outer peripheral portion which is smaller than a difference between a donor concentration and an acceptor concentration in a central portion, and is smaller than 3.0×1019/cm3.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: January 12, 2021
    Assignee: SHOWA DENKO K.K.
    Inventors: Kazuma Eto, Hiromasa Suo, Tomohisa Kato
  • Patent number: 10886159
    Abstract: A method of processing a wafer includes: preparing a support substrate that can transmit ultraviolet rays having a wavelength of 300 nm or shorter and can support the wafer thereon; integrating a face side of the wafer and the support substrate by sticking the face side of the wafer and the support substrate to each other with an UV-curable resin whose adhesive power can be lowered by ultraviolet rays applied thereto interposed therebetween, thereby integrally combining the wafer and the support substrate with each other; processing a reverse side of the wafer; destroying the UV-curable resin by applying a focused laser beam in an ultraviolet range having a wavelength of 300 nm or shorter from a support substrate side; and peeling off the support substrate from the face side of the wafer.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: January 5, 2021
    Assignee: DISCO CORPORATION
    Inventors: Hiroshi Morikazu, Tasuku Koyanagi
  • Patent number: 10866665
    Abstract: Embodiments of a vehicle interior system are disclosed. In one or more embodiments, the system includes a base with a curved surface, and a display or touch panel disposed on the curved surface. The display includes a cold-bent glass substrate with a thickness of 1.5 mm or less and a first radius of curvature of 20 mm or greater, and a display module and/or touch panel attached to the glass substrate having a second radius of curvature that is within 10% of the first radius of curvature. Methods for forming such systems are also disclosed.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: December 15, 2020
    Assignee: CORNING INCORPORATED
    Inventors: Jordan Thomas Boggs, Michael Timothy Brennan, Atul Kumar, Arpita Mitra, William Michael Seiderman, Yawei Sun, Wendell Porter Weeks
  • Patent number: 10822285
    Abstract: Coating systems are provided for positioning on a surface of a substrate, along with the resulting coated components and methods of their formation. The coating system may include a layer having a compound of the formula: A1?bBbZ1?dDdMO6 where: A is Al, Ga, In, Sc, Y, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Fe, Cr, Co, Mn, Bi, or a mixture thereof; b is 0 to about 0.5; Z is Hf, Ti, or a mixture thereof; D is Zr, Ce, Ge, Si, or a mixture thereof; d is 0 to about 0.5; and M is Ta, Nb, or a mixture thereof.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: November 3, 2020
    Assignee: General Electric Company
    Inventor: Glen Harold Kirby
  • Patent number: 10808142
    Abstract: Provided are a method of preparing a graphene quantum dot, a graphene quantum dot prepared using the method, a hardmask composition including the graphene quantum dot, a method of forming a pattern using the hardmask composition, and a hardmask obtained from the hardmask composition. The method of preparing a graphene quantum dot includes reacting a graphene quantum dot composition and an including a polyaromatic hydrocarbon compound and an organic solvent at an atmospheric pressure and a temperature of about 250° C. The polyaromatic hydrocarbon compound may include at least four aromatic rings.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: October 20, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangwon Kim, Minsu Seol, Hyeonjin Shin, Dongwook Lee, Yunseong Lee, Seongjun Jeong, Alum Jung
  • Patent number: 10741420
    Abstract: A cleaning wafer or substrate for use in cleaning, or in combination with, components of, for example, integrated chip manufacturing apparatus. The cleaning substrate can include a substrate having varying predetermined surface features, such as one or more predetermined adhesive, non-tacky, electrostatic, projection, depression, or other physical sections. The predetermined features can provide for more effective cleaning of the components with which they are used, such as an integrated chip manufacturing apparatus in the place of the integrated chip wafer. The cleaning substrate can be urged into cleaning or other position by vacuum, mechanical, electrostatic, or other forces. The cleaning substrate can adapted to accomplish a variety of functions, including abrading or polishing. The cleaning substrate may be made by a novel method of making, and it may then be used in a novel method of use I combination with chip manufacturing apparatus.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: August 11, 2020
    Assignee: International Test Solutions, Inc.
    Inventors: Alan E. Humphrey, James H. Duvall, Jerry Broz
  • Patent number: 10714338
    Abstract: We describe a method for reducing bow in a composite wafer comprising a silicon wafer and a silicon carbide layer grown on the silicon wafer. The method includes applying nitrogen atoms during the growth process of the silicon carbide layer on the silicon wafer so as to generate a compressive stress within the composite wafer.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: July 14, 2020
    Assignee: ANVIL SEMICONDUCTORS LIMITED
    Inventor: Peter Ward
  • Patent number: 10704148
    Abstract: A laminated film includes a flexible base material, a first thin film layer formed on at least one of surfaces of the base material, and a second thin film layer formed on the first thin film layer, and the first thin film layer contains a silicon atom (Si), an oxygen atom (O) and a carbon atom (C), the second thin film layer contains a silicon atom, an oxygen atom and a nitrogen atom (N), and the first thin film layer and the second thin film layer are formed by using glow discharge plasma.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: July 7, 2020
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Yasuhiro Yamashita, Yutaka Ito, Hideaki Nakajima
  • Patent number: 10676266
    Abstract: A tapping valve with a plastic valve housing for shipping and storage tanks for liquids, which are equipped with an inner tank with a filling socket and a drain socket for connecting the tapping valve, an outer jacket of a metal cage or sheet metal, and a pallet-like metal support frame. The tapping valve is screwed by means of the inlet socket of the valve housing onto a connecting flange, which is designed as a threaded flange, is made of an electrically conductive plastic material, and is welded onto the drain socket of the inner tank. The connecting flange of the valve housing is connected with the support frame or the outer jacket of the shipping and storage tank by an electric grounding conductor.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: June 9, 2020
    Assignee: PROTECHNA S.A.
    Inventor: Udo Schütz
  • Patent number: 10669447
    Abstract: A method for producing a coating on a substrate. The method includes producing a clearcoat directly on the substrate by applying an aqueous clearcoat material directly to the substrate. The method further includes curing the applied clearcoat material, the clearcoat material being a two-component coating composition. Also disclosed are coatings produced according to the method and their uses.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: June 2, 2020
    Assignee: BASF Coatings GmbH
    Inventors: Jens-Henning Noatschk, Eva-Kathrin Schillinger, Simon Winzen
  • Patent number: 10654100
    Abstract: The present disclosure is directed at alloys and method for layer-by-layer deposition of metallic alloys on a substrate. The resulting deposition provides for relatively high hardness metallic parts with associated wear resistance. Applications for the metallic parts include pumps, valves and/or bearings.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: May 19, 2020
    Assignee: The NanoSteel Company, Inc.
    Inventors: Charles D. Tuffile, Harald Lemke
  • Patent number: 10633738
    Abstract: Embodiments described herein relate to a protective coating that protects an underlying chamber component (i.e. the object upon which the coating is being deposited) from corrosion or deterioration within a corrosive environment.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: April 28, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Son T. Nguyen, Michael Fong
  • Patent number: 10629796
    Abstract: A laminate includes, on a substrate, a first buffer layer substantially made of zirconium oxide or stabilized zirconia, a second buffer layer substantially made of yttrium oxide, a metal layer substantially made of at least one among platinum, iridium, palladium, rhodium, vanadium, chromium, iron, molybdenum, tungsten, aluminum, silver, gold, copper, and nickel, and a magnesium oxide layer substantially made of magnesium oxide, in this order.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: April 21, 2020
    Assignee: TDK CORPORATION
    Inventors: Kazuya Maekawa, Makoto Shibata, Katsuyuki Nakada, Yohei Shiokawa, Kazuumi Inubushi
  • Patent number: 10607776
    Abstract: A multilayer ceramic electronic component includes a ceramic body in which dielectric layers and internal electrodes are alternately stacked. The dielectric layers contain at least one dielectric grain having a ratio of a long axis to a short axis that is 3.5 or more. The internal electrodes contain a ceramic component containing a grain growth adjusting ingredient for dielectric grains. Each dielectric layer includes interfacial portions adjacent to the internal electrodes and a central portion disposed between the interfacial portions, and concentrations of the grain growth adjusting ingredient in the interfacial portions and the central portion are different from each other.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: March 31, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Kum Jin Park, Chang Hak Choi, Jong Hoon Yoo, Doo Young Kim, Min Gi Sin, Chi Hwa Lee, Chul Seung Lee, Jong Han Kim
  • Patent number: 10593546
    Abstract: A method of producing graphene or other two-dimensional material such as graphene including heating the substrate held within a reaction chamber to a temperature that is within a decomposition range of a precursor, and that allows two-dimensional crystalline material formation from a species released from the decomposed precursor; establishing a steep temperature gradient (preferably >1000° C. per meter) that extends away from the substrate surface towards an inlet for the precursor; and introducing precursor through the relatively cool inlet and across the temperature gradient towards the substrate surface. The steep temperature gradient ensures that the precursor remains substantially cool until it is proximate the substrate surface thus minimizing decomposition or other reaction of the precursor before it is proximate the substrate surface. The separation between the precursor inlet and the substrate is less than 100 mm.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: March 17, 2020
    Assignee: Paragraf Ltd.
    Inventor: Simon Charles Stewart Thomas
  • Patent number: 10571672
    Abstract: An apparatus for compressive sensing may include a filter array, a detector, and a reconstruction engine. The filter array may be configured to generate a first illumination pattern in response to a first wavelength of light and a second illumination pattern in response to a second wavelength of light. The first illumination pattern and the second illumination pattern may be projected onto an object. The detector may be configured to determine a first intensity of a first light emitted by the object in response to the first illumination pattern and a second intensity of a second light emitted by the object in response to the second illumination pattern. The reconstruction engine may be configured to generate an image of the object based at least on the first intensity, the first illumination pattern, the second intensity, and the second illumination pattern.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: February 25, 2020
    Assignee: The Regents of the University of California
    Inventors: Zhaowei Liu, Eric Huang, Qian Ma
  • Patent number: 10573825
    Abstract: Provided are a compound represented by Formula 1 and an organic light-emitting device including the same: wherein descriptions of Formula 1 are provided in the detailed description of the present specification.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: February 25, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sanghyun Han, Sooyon Kim, Hyejin Jung, Youngkook Kim, Seokhwan Hwang
  • Patent number: 10546769
    Abstract: According to one embodiment, a semiconductor manufacturing method for a stacked body that includes a semiconductor substrate, a supporting substrate containing silicon, and a joining layer arranged between the semiconductor substrate and the supporting substrate to joint the semiconductor substrate and the supporting substrate, in which a surface of the semiconductor substrate opposite to the joining layer is to be ground, includes irradiating the stacked body with electromagnetic wave having energy of 0.11 to 0.14 eV from a side of the supporting substrate, and separating the semiconductor substrate from the supporting substrate.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: January 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuhiko Shirakawa, Kenji Takahashi, Eiji Takano, Masaya Shima
  • Patent number: 10529891
    Abstract: An optoelectronic device that includes a germanium containing buffer layer atop a silicon containing substrate, and a first distributed Bragg reflector stack of III-V semiconductor material layers on the buffer layer. The optoelectronic device further includes an active layer of III-V semiconductor material present on the first distributed Bragg reflector stack, wherein a difference in lattice dimension between the active layer and the first distributed brag reflector stack induces a strain in the active layer. A second distributed Bragg reflector stack of III-V semiconductor material layers having a may be present on the active layer.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana
  • Patent number: 10508361
    Abstract: In a first step, protrusions (42) are formed on a surface of an SiC substrate (40), and the SiC substrate (40) is etched. In a second step, the protrusions (42) of the SiC substrate (40) are epitaxially grown through MSE process, and an epitaxial layer (43a) containing threading screw dislocation, which has been largely grown in the vertical (c-axis) direction as a result of MSE process, is at least partially removed. In a third step, MSE process is performed again on the SiC substrate (40) after the second step, to cause epitaxial layers (43) containing no threading screw dislocation to be grown in the horizontal (a-axis) direction to be connected at the molecular level, so that one monocrystalline 4H—SiC semiconductor wafer (45) having a large area is generated throughout an Si-face or a C-face of the SiC substrate (40).
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: December 17, 2019
    Assignee: KWANSEI GAKUIN EDUCATIONAL FOUNDATION
    Inventors: Tadaaki Kaneko, Yasunori Kutsuma, Koji Ashida
  • Patent number: 10494738
    Abstract: A method of growing crystalline materials on two-dimensional inert materials comprising functionalizing a surface of a two-dimensional inert material, growing a nucleation layer on the functionalized surface, and growing a crystalline material. A crystalline material grown on a two-dimensional inert material made from the process comprising functionalizing a surface of a two-dimensional inert material, growing a nucleation layer on the functionalized surface, and growing a crystalline material.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: December 3, 2019
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Neeraj Nepal, Virginia Wheeler, Charles R. Eddy, Jr., Francis J. Kub, Travis J. Anderson, Michael A. Mastro, Rachael L. Myers-Ward, Sandra C. Hangarter
  • Patent number: 10450650
    Abstract: The present invention relates to a method of manufacturing large area graphene for graphene-based photonics devices such as bolometric graphene detectors, or for use as a saturable absorber in ultra-high bandwidth detectors for producing ultrafast laser pulses. The method includes: growing a first graphene layer on one side of a metal substrate, and a second graphene layer on another side of the metal substrate; coating the first graphene layer with a plurality of resist layers including a low molecular weight polymethylmethacrylate, and a high molecular weight polymethylmethacrylate; removing the second graphene layer and the metal substrate to reveal the first graphene layer; disposing the first graphene layer on an optical substrate; and removing the plurality of resist layers from the first graphene layer to reveal a final graphene layer, which can be used as the basis to manufacture a multilayer graphene structure for graphene detectors.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: October 22, 2019
    Assignee: The United States of America as represented by the Admininstrator of the National Aeronautics and Space Administration
    Inventors: Mahmooda Sultana, Mary J. Li, Anthony W. Yu
  • Patent number: 10429308
    Abstract: A carrier for Raman spectroscopy comprising: a substrate having a first metal surface; a plurality of graphene islands disposed on the substrate, wherein parts of the neighboring graphene islands are not connected and thereby form a plurality of gaps between the graphene islands; and a plurality of second metal particles disposed at the gaps between the graphene islands.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: October 1, 2019
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Yon-Hua Tzeng, Ying-Ren Chen
  • Patent number: 10370240
    Abstract: A layer structure may include a carrier, a two-dimensional layer, and a holding structure. The holding structure is arranged on the carrier and holds the two-dimensional layer on the carrier such that at least a portion of the two-dimensional layer is spaced apart from the carrier. The holding structure includes a holding portion extending from the two-dimensional layer towards the carrier beyond the at least a portion of the two-dimensional layer spaced apart from the carrier.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: August 6, 2019
    Assignee: Infineon Technologies AG
    Inventors: Matthias Koenig, Guenther Ruhl
  • Patent number: 10369595
    Abstract: A semiconductor structure is provided including an electrically-conducting substrate and a layer of a two-dimensional material. The structure further includes a solid organic spacer layer arranged between the electrically-conducting substrate and the layer of the two-dimensional material.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventor: Pio Peter Niraj Nirmalraj