Having Selenium Or Tellurium Elemental Semiconductor Component Patents (Class 438/102)
  • Patent number: 10667060
    Abstract: The present invention provides a sound generation device and a preparation method of a metal plastic part. The sound generation device comprises a metal plastic part. The metal plastic part comprises a plastic part and a metal insert that is combined with the plastic part. An oxidation film that is obtained through metal nanocrystallization and a nanopore that is formed in a surface of the oxidation film and has a pore diameter of 20-1,000 nm are arranged on a surface of the metal insert. The nanopore is filled with a resin composition from which the plastic part is made. As the nanopore is filled with the resin composition from which the plastic part is made, the metal insert and the plastic part are in close fit with each other, which greatly enhances the gluing capability of the metal insert and prevents the metal insert and the plastic part which are formed through injection molding from being separated.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: May 26, 2020
    Assignee: GOERTEK INC.
    Inventors: Qingyi Zhang, Gang Chen, Zhenjun Li, Shuangshuang Fan
  • Patent number: 10651239
    Abstract: A storage device includes: a first conductive layer; a second conductive layer; and a resistance-variable layer disposed between the first conductive layer and the second conductive layer, and including a first chalcogenide containing a first element which is either silicon or germanium. An insulating layer is disposed in a second direction perpendicular to a first direction from the first conductive layer to the second conductive layer with respect to the resistance-variable layer. A first region is disposed between the resistance-variable layer and the insulating layer, and has a third concentration of the first element higher than both a first concentration of the first element in the resistance-variable layer and a second concentration of the first element in the insulating layer.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: May 12, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kazuhiko Yamamoto
  • Patent number: 10573812
    Abstract: Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 10388866
    Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Agostino Pirovano, Umberto M. Meotto
  • Patent number: 10344381
    Abstract: The present invention is in the field of processes for the generation of thin inorganic films on substrates, in particular atomic layer deposition processes. In detail the present invention relates a process comprising bringing a compound of general formula (I) into the gaseous or aerosol state (Fig.) and depositing the compound of general formula (I) from the gaseous or aerosol state onto a solid substrate, wherein R1 and R4 are independent of each other an alkyl group, an aryl group or a trialkylsilyl group, R2, R3, R5 and R6 are independent of each other hydrogen, an alkyl group, an aryl group or a trialkylsilyl group, n is an integer from 1 to 3, M is Ni or Co, X is a ligand which coordinates M, and m is an integer from 0 to 4.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: July 9, 2019
    Assignee: BASF SE
    Inventors: Julia Strautmann, Rocco Paciello, Thomas Schaub, Felix Eickemeyer, Daniel Loeffler, Hagen Wilmer, Udo Radius, Johannes Berthel, Florian Hering
  • Patent number: 10276793
    Abstract: A variable resistance memory device includes a plurality of first conductive lines, each of the first conductive lines extends in a first direction, a plurality of second conductive lines are above the first conductive lines, and each of the second conductive lines extend in a second direction transverse to the first direction. A plurality of first memory cells are at intersections where the first and second conductive lines overlap each other, each of the first memory cells including a first variable resistance structure having a first variable resistance pattern, a first sacrificial pattern and a second variable resistance pattern sequentially stacked in the first direction on a first plane. A plurality of third conductive lines are above the second conductive lines, each of the third conductive lines extend in the first direction, and a plurality of second memory cells are at intersections where the second and the third conductive lines overlap each other.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: April 30, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jae Jung, Youn-Seon Kang
  • Patent number: 10266553
    Abstract: A compound and the use thereof to prepare a functional or telechelic polyolefin is provided. The compound has the following formula (II): Y((CH2)p—B?)m??(II), wherein m=2 or 3; Y being an alkaline earth metal or zinc when m=2, Y being aluminum when m=3; B? being selected from the group comprising N(SiMe3)2; N(SiMe2CH2CH2SiMe2); C6F5; C3F7; C6F13; para-C6H4—NMe2; para-C6H4—O-Me; para-C6H4—N(SiMe3)2; and CH(OCH2CH2O); and p being an integer from 0 to 50.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: April 23, 2019
    Assignees: COMPAGNIE GENERALE DES ETABLISSEMENTS MICHELIN, MICHELIN RECHERCHE ET TECHNIQUE S.A., UNIVERSITE CLAUDE BERNARD LYON 1, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, CPE LYON FORMATION CONTINUE ET RECHERCHE
    Inventors: Guillaume Cortial, Julien Thuilliez, Christophe Boisson, Franck D'Agosto, Sébastien Norsic
  • Patent number: 10269562
    Abstract: The invention provides the use of at least one binary group 15 element compound of the general formula R1R2E-E?R3R4 (I) or R5E(E?R6R7)2 (II) as the educt in a vapor deposition process. In this case, R1, R2, R3 and R4 are independently selected from the group consisting of H, an alkyl radical (C1-C10) and an aryl group, and E and E? are independently selected from the group consisting of N, P, As, Sb and Bi. This use excludes hydrazine and its derivatives. The binary group 15 element compounds according to the invention allow the realization of a reproducible production and/or deposition of multinary, homogeneous and ultrapure 13/15 semiconductors of a defined combination at relatively low process temperatures. This makes it possible to completely waive the use of an organically substituted nitrogen compound such as 1.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 23, 2019
    Assignee: PHILIPPS-UNIVERSITÄT MARBURG
    Inventors: Carsten Von Haenisch, Kerstin Volz, Wolfgang Stolz, Eduard Sterzer, Andreas Beyer, Dominik Keiper, Benjamin Ringler
  • Patent number: 10249491
    Abstract: Atomic Layer Deposition (ALD) is used for heteroepitaxial film growth at reaction temperatures ranging from 80-400° C. The substrate and film materials are preferably matched to take advantage of Domain Matched Epitaxy (DME). A laser annealing system is used to thermally anneal deposition layer after deposition by ALD. In preferred embodiments, a silicon substrate is overlaid with an AlN nucleation layer and laser annealed. Thereafter a GaN device layer is applied over the AlN layer by an ALD process and then laser annealed. In a further example embodiment, a transition layer is applied between the GaN device layer and the AlN nucleation layer. The transition layer comprises one or more different transition material layers each comprising a AlxGa1-xN compound wherein the composition of the transition layer is continuously varied from AlN to GaN.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: April 2, 2019
    Assignee: Ultratech, Inc.
    Inventors: Ganesh Sundaram, Andrew M. Hawryluk, Daniel Stearns
  • Patent number: 10164187
    Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: December 25, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Andrea Redaelli, Agostino Pirovano, Umberto M. Meotto
  • Patent number: 10062801
    Abstract: A method of making a semiconductor device includes forming a semiconductor material stack having a sodium at an atomic concentration greater than 1×1019/cm3, depositing a transparent conductive oxide layer over the semiconductor material stack, such that sodium atoms diffuse from the semiconductor material stack into the transparent conductive oxide layer, and contacting a physically exposed surface of the transparent conductive oxide layer with a fluid to remove sodium from the transparent conductive oxide layer.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: August 28, 2018
    Assignee: BEIJING APOLLO DING RONG SOLAR TECHNOLOGY CO., LTD.
    Inventor: Dmitry Poplavskyy
  • Patent number: 9976228
    Abstract: [Problem] To provide a method for producing a colloidal crystal, wherein the method is easily controlled and is capable of dealing with a wide range of types of colloidal particle. [Solution] The method for producing a colloidal crystal in the present invention is characterized by comprising a preparation step of preparing a colloidal dispersion liquid, in which colloidal particles are dispersed in a liquid comprising an ionic surfactant and a colloidal crystal can be formed due to temperature changes, and a crystallization step of formation of a colloidal crystal by changing the temperature of the colloidal dispersion liquid from a temperature region in which the colloidal crystal is not formed to a temperature region in which the colloidal crystal is formed.
    Type: Grant
    Filed: March 3, 2012
    Date of Patent: May 22, 2018
    Assignees: PUBLIC UNIVERSITY CORPORATION NAGOYA CITY UNIVERSITY, FUJI CHEMICAL CO., LTD.
    Inventors: Junpei Yamanaka, Akiko Toyotama, Masaaki Yamamoto, Sachiko Onda, Tohru Okuzono, Fumio Uchida
  • Patent number: 9960036
    Abstract: Atomic Layer Deposition (ALD) is used for heteroepitaxial film growth at reaction temperatures ranging from 80-400° C. The substrate and film materials are preferably matched to take advantage of Domain Matched Epitaxy (DME). A laser annealing system is used to thermally anneal deposition layer after deposition by ALD. In preferred embodiments, a silicon substrate is overlaid with an AlN nucleation layer and laser annealed. Thereafter a GaN device layer is applied over the AlN layer by an ALD process and then laser annealed. In a further example embodiment, a transition layer is applied between the GaN device layer and the AlN nucleation layer. The transition layer comprises one or more different transition material layers each comprising a AlxGa1-xN compound wherein the composition of the transition layer is continuously varied from AlN to GaN.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: May 1, 2018
    Assignee: Ultratech, Inc.
    Inventors: Ganesh Sundaram, Andrew M. Hawryluk, Daniel Stearns
  • Patent number: 9927706
    Abstract: Provided herein are methods of directed self-assembly (DSA) on atomic layer chemical patterns and related compositions. The atomic layer chemical patterns may be formed from two-dimensional materials such as graphene. The atomic layer chemical patterns provide high resolution, low defect directed self-assembly. For example, DSA on a graphene pattern can be used achieve ten times the resolution of DSA that is achievable on a three-dimensional pattern such as a polymer brush. Assembly of block copolymers on the atomic layer chemical patterns may also facilitate subsequent etch, as the atomic layer chemical patterns are easier to etch than conventional pattern materials.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: March 27, 2018
    Assignees: The University of Chicago, Wisconsin Alumni Research Foundation
    Inventors: Paul Franklin Nealey, Tzu-Hsuan Chang, Shisheng Xiong, Zhenqiang Ma, Michael Scott Arnold, Robert Jacobberger
  • Patent number: 9911727
    Abstract: A memory circuit includes a first memory cell and a second memory adjacent to the first memory cell. The first memory cell includes a first word line strapping line segment electrically coupled with a pass device of the first memory cell; and a second word line strapping line segment. The second memory cell includes a first word line strapping line segment; and a second word line strapping line segment electrically coupled with a pass device of the second memory cell. The first word line strapping line segment of the first memory cell and the first word line strapping line segment of the second memory cell are connected with each other at a first interconnection layer. The second word line strapping line segment of the first memory cell and the second word line strapping line segment of the second memory cell are connected with each other at the first interconnection layer.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9893279
    Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: February 13, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Andrea Redaelli, Agostino Pirovano, Umberto M. Meotto
  • Patent number: 9871196
    Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: January 16, 2018
    Assignee: Ovonyx Memory Technology, LLC
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 9859493
    Abstract: A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device may include a multi-layered insulating layer formed on a semiconductor substrate, on which a lower electrode is formed. The multi-layered insulating layer may include a first hole and a second hole, concentrically formed therein, to expose the lower electrode, wherein a diameter of the first hole is larger than a diameter of the second hole. A variable resistance material layer may be formed in the second hole to contact the lower electrode, and an upper electrode may be formed in the first hole to contact the variable resistance material layer.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: January 2, 2018
    Assignee: SK Hynix Inc.
    Inventors: Min Seok Kim, Hyo Seob Yoon
  • Patent number: 9685609
    Abstract: A variable resistance memory device includes a plurality of first conductive lines, each of the first conductive lines extends in a first direction, a plurality of second conductive lines are above the first conductive lines, and each of the second conductive lines extend in a second direction transverse to the first direction. A plurality of first memory cells are at intersections where the first and second conductive lines overlap each other, each of the first memory cells including a first variable resistance structure having a first variable resistance pattern, a first sacrificial pattern and a second variable resistance pattern sequentially stacked in the first direction on a first plane. A plurality of third conductive lines are above the second conductive lines, each of the third conductive lines extend in the first direction, and a plurality of second memory cells are at intersections where the second and the third conductive lines overlap each other.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: June 20, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jae Jung, Youn-Seon Kang
  • Patent number: 9614154
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes first lines extending in a first direction; second lines extending in a second direction crossing the first direction; insulating patterns interposed between the first and second lines at first intersections of the first and second lines; and variable resistance patterns interposed between the first and the second lines at second intersections of the first and second lines. A central intersection is defined by respective central lines of the first and second lines and corresponds to a coordinate (0, 0). The first intersections are located on first to (n+1)th virtual lines, the (n+1)th virtual line having a polygonal shape in which vertexes correspond to coordinates (?(k?n), 0), (k?n, 0), (0, k?n) and (0, ?(k?n)) where k is a natural number and n is an integer in a range of 0 to (k?1).
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: April 4, 2017
    Assignee: SK HYNIX INC.
    Inventor: Hyung-Dong Lee
  • Patent number: 9614005
    Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: April 4, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Andrea Redaelli, Agostino Pirovano, Umberto M. Meotto
  • Patent number: 9543514
    Abstract: A memory component including first and second electrodes with a memory layer therebetween, the memory layer having first and second memory layers, the first memory layer containing aluminum and a chalcogen element of tellurium, the second memory layer between the first memory layer and the first electrode and containing an aluminum oxide and at least one of a transition metal oxide and a transition metal oxynitride having a lower resistance than the aluminum oxide.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: January 10, 2017
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Kazuhiro Ohba, Shuichiro Yasuda, Tetsuya Mizuguchi, Katsuhisa Aratani, Masayuki Shimuta, Akira Kouchiyama, Mayumi Ogasawara
  • Patent number: 9530645
    Abstract: A photoresist pattern used for forming a pattern of a block copolymer is formed on a substrate, and then an acid solution is supplied and an alkaline solution is further supplied to the photoresist pattern so as to slim and smooth the photoresist pattern. A block copolymer solution is applied to the substrate on which the smoothed photoresist pattern has been formed, to form a film of the block copolymer, and the film is heated.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: December 27, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Makoto Muramatsu, Takahiro Kitano, Tadatoshi Tomita, Keiji Tanouchi
  • Patent number: 9502645
    Abstract: A method for manufacturing a semiconductor device may include the following steps: preparing a substrate; preparing a first insulating layer on the substrate; preparing an electrode in the first insulating layer; preparing a second insulating layer on the first insulating layer; removing (e.g., using a dry etching process or a wet etching process) a portion of the second insulating layer to form a hole that at least partially exposes the electrode; providing a phase change material layer that may cover the electrode; and removing (e.g., using a sputtering process such as an argon sputtering process), a portion of the phase change material layer positioned inside the hole to form a phase change member that may expose a first portion of (a top side of) the electrode and may directly contact a second portion of (the top side of) the electrode.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: November 22, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Jia Xu, Jiadong Ren
  • Patent number: 9450135
    Abstract: The present invention generally provides a method for forming a photovoltaic device including evaporating a source material to form a large molecule processing gas and flowing the large molecule processing gas through a gas distribution showerhead and into a processing area of a processing chamber having a substrate therein. The method includes generating a small molecule processing gas, and reacting the small molecule processing gas with a film already deposited on a substrate surface to form a semiconductor film. Additionally, apparatuses that may use the methods are also provided to enable continuous inline CIGS type solar cell formation.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: September 20, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Byung-sung Kwak, Kaushal K. Singh, Stefan Bangert, Nety M. Krishna
  • Patent number: 9390933
    Abstract: There is a method of selectively etching a silicon oxide film among a silicon nitride film and the silicon oxide film formed on a surface of a substrate to be processed, the method including: under a vacuum atmosphere, intermittently supplying at least one of a first processing gas composed of a hydrogen fluoride gas and an ammonia gas and a second processing gas composed of a compound of nitrogen, hydrogen and fluorine, to the substrate to be processed multiple times.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 12, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kensaku Narushima, Kohichi Satoh, Motoko Nakagomi, Eiichi Komori, Taiki Katou
  • Patent number: 9371338
    Abstract: Disclosed are Si-containing thin film forming precursors, methods of synthesizing the same, and methods of using the same to deposit silicon-containing films using vapor deposition processes for manufacturing semiconductors, photovoltaics, LCD-TFT, flat panel-type devices, refractory materials, or aeronautics.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: June 21, 2016
    Assignee: American Air Liquide, Inc.
    Inventors: Christian Dussarrat, Glenn Kuchenbeiser, Venkateswara R. Pallem
  • Patent number: 9362492
    Abstract: Various methods and devices that involve phase change material (PCM) switches are disclosed. An exemplary integrated circuit comprises an active layer with a plurality of field effect transistor (FET) channels for a plurality of FETs. The integrated circuit also comprises an interconnect layer comprising a plurality of conductive interconnects. The plurality of conductive interconnects couple the plurality of field effect transistors. The integrated circuit also comprises an insulator layer covering at least a portion of the interconnect layer. The integrated circuit also comprises a channel of a radio-frequency (RF) PCM switch. The channel of the RF PCM switch is formed on the insulator layer.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: June 7, 2016
    Assignee: QUALCOMM SWITCH CORP.
    Inventors: Sinan Goktepeli, Michael A. Stuber
  • Patent number: 9337420
    Abstract: A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device may include a multi-layered insulating layer formed on a semiconductor substrate, on which a lower electrode is formed. The multi-layered insulating layer may include a first hole and a second hole, concentrically formed therein, to expose the lower electrode, wherein a diameter of the first hole is larger than a diameter of the second hole. A variable resistance material layer may be formed in the second hole to contact the lower electrode and an upper electrode may be formed in the first hole to contact the variable resistance material layer.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: May 10, 2016
    Assignee: SK Hynix Inc.
    Inventors: Min Seok Kim, Hyo Seob Yoon
  • Patent number: 9312409
    Abstract: An ink for forming a compound semiconductor thin film is provided, which contains a binder includes a compound includes an S atom or an Se atom and metallic compound particles which are both dispersed in an organic solvent. A compound semiconductor thin film is formed by applying or printing the ink for forming a compound semiconductor thin film and heat-treating it. A solar cell is constituted, which has a light-absorbing layer formed of the compound semiconductor thin film.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: April 12, 2016
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Yiwen Zhang, Akira Yamada
  • Patent number: 9236568
    Abstract: A memory device includes an array of electrodes that includes thin film plates of electrode material. Multilayer strips are arranged as bit lines over respective columns in the array of electrodes, including a layer of memory material and a layer of top electrode material. The multilayer strips have a primary body and a protrusion having a width less than that of the primary body and is self-aligned with contact surfaces on the thin film plates. Memory material in the protrusion contacts surfaces on the distal ends of thin film plates of electrodes in the corresponding column in the array. The device can be made using a damascene process in self-aligned forms over the contact surfaces.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: January 12, 2016
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 9231103
    Abstract: A vertical MOSFET transistor is formed in a body of semiconductor material having a surface. The transistor includes a buried conductive region of a first conductivity type; a channel region of a second conductivity type, arranged on top of the buried conductive region; a surface conductive region of the first conductivity type, arranged on top of the channel region and the buried conductive region; a gate insulation region, extending at the sides of and contiguous to the channel region; and a gate region extending at the sides of and contiguous to the gate insulation region.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: January 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Agostino Pirovano
  • Patent number: 9190610
    Abstract: A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: November 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Sheng Liang, Tzyh-Cheang Lee, Fu-Liang Yang
  • Patent number: 9172036
    Abstract: An integrated circuit device including a resistive random access memory (RRAM) cell formed over a substrate. The RRAM cell includes a top electrode having an upper surface. A blocking layer covers a portion of the upper surface. A via extends above the top electrode within a matrix of dielectric. The upper surface of the top electrode includes an area that interfaces with the blocking layer and an area that interfaces with the via. The area of the upper surface that interfaces with the via surrounds the area of the upper surface that interfaces with the blocking layer. The blocking layer is functional during processing to protect the RRAM cell from etch damage while being structured in such a way as to not interfere with contact between the overlying via and the top electrode.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: October 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Kuo-Chi Tu, Chih-Yang Chang, Chin-Chieh Yang, Yu-Wen Liao, Wen-Chun You, Sheng-Hung Shih
  • Patent number: 9166163
    Abstract: Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can created comprising a non-stoichimetric sub-oxide that can be a combination of multiple silicon and/or silicon oxide layers with an aggregate chemical formula of SiOX, where X can be a non-integer greater than zero and less than 2. The sub-oxide can be created in a variety of ways, including various techniques related to growing the sub-oxide, depositing the sub-oxide, or transforming an extant film into the sub-oxide.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: October 20, 2015
    Assignee: Crossbar, Inc.
    Inventors: Harry Yue Gee, Mark Harold Clark, Steven Patrick Maxwell, Sung Hyun Jo, Natividad Vasquez, Jr.
  • Patent number: 9112150
    Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: August 18, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Giorgio Servalli, Carmela Cupeta, Fabio Pellizzer
  • Patent number: 9099299
    Abstract: A method of removing a hard mask used for patterning gate stacks including patterning gate stacks on a substrate, wherein the hard mask is deposited over the gate stacks. The method further includes depositing a dielectric layer on the substrate after the gate stacks are patterned and planarizing a first portion of the dielectric layer. The method further includes removing a second portion of the dielectric layer and the hard mask by using an etching gas and etching the remaining dielectric layer by using a wet etching chemistry.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: August 4, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Shiang-Bau Wang
  • Patent number: 9093599
    Abstract: Vapor deposition apparatus for forming stacked thin films on discrete photovoltaic module substrates conveyed in a continuous non-stop manner through the apparatus are provided. The apparatus includes a first sublimation compartment positioned over a first deposition area of said apparatus, a second sublimation compartment positioned over a second deposition area of said apparatus, and an internal divider positioned therebetween and defining a middle seal member. An actuator is attached to the internal divider and is configured to move the internal divider to control intermixing of first source material vapors and second source material vapors within the first deposition area and the second deposition area. Methods are also generally provided for depositing stacked thin films on a substrate.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: July 28, 2015
    Assignee: First Solar, Inc.
    Inventor: Mark Jeffrey Pavol
  • Patent number: 9065048
    Abstract: Methods of forming a material include exposing a substrate to a first germanium-containing compound and a second, different germanium-containing compound; exposing the substrate to a first antimony-containing compound and a second, different antimony-containing compound; and exposing the substrate to a first tellurium-containing compound and a second, different tellurium-containing compound. Methods of forming chalcogenide materials include exposing a substrate to a first precursor comprising a reactive precursor of a first metal and a co-reactive precursor of the first metal, the reactive precursor and the co-reactive precursor each having at least one ligand coordinated to an atom of the first metal, wherein the at least one ligand of the co-reactive precursor is different from the at least one ligand of the reactive precursor. The substrate is also exposed to a reactive antimony precursor and a co-reactive antimony precursor and to a reactive tellurium precursor and a co-reactive tellurium precursor.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: June 23, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Publication number: 20150147844
    Abstract: A method for fabricating a semiconductor device includes supplying a first source gas including a germanium (Ge) precursor onto a semiconductor substrate for a first time period, and periodically interrupting the supplying of the first source gas for the first time period to form Ge elements on the semiconductor substrate.
    Type: Application
    Filed: February 20, 2014
    Publication date: May 28, 2015
    Applicant: SK HYNIX INC.
    Inventors: Young Seok KWON, Kwon HONG
  • Patent number: 9034688
    Abstract: Precursors for use in depositing antimony-containing films on substrates such as wafers or other microelectronic device substrates, as well as associated processes of making and using such precursors, and source packages of such precursors. The precursors are useful for deposition of Ge2Sb2Te5 chalcogenide thin films in the manufacture of nonvolatile Phase Change Memory (PCM) or for the manufacturing of thermoelectric devices, by deposition techniques such as chemical vapor deposition (CVD) and atomic layer deposition (ALD).
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: May 19, 2015
    Assignee: ENTEGRIS, INC.
    Inventors: Tianniu Chen, William Hunks, Philip S. H. Chen, Chongying Xu, Leah Maylott
  • Patent number: 9035276
    Abstract: A memory device includes a first plurality of memory cells arranged in a first crossbar array, a first thickness of dielectric material overlying the first plurality of memory cells, and a second plurality of memory cells arranged in a second crossbar array overlying the first thickness of dielectric material. The memory device further includes a second thickness of dielectric material overlying the second plurality of memory cells. In a specific embodiment, the memory device further includes a Nth thickness of dielectric material overlying an Nth plurality of memory cells, where N is an integer ranging from 3 to 8.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: May 19, 2015
    Assignee: Crossbar, Inc.
    Inventor: Scott Brad Herner
  • Patent number: 9024291
    Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a bottom structure including a heating electrode, data storage materials, each of the data storage materials formed on the bottom structure in a confined structure perpendicular to the bottom structure, and having a lower diameter smaller than an upper diameter, an upper electrode formed on each of the data storage materials, and an insulation unit formed between adjacent data storage materials.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: May 5, 2015
    Assignee: SK Hynix Inc.
    Inventors: Han Woo Cho, Hyo Seob Yoon, Yong Seok Lee
  • Patent number: 9024283
    Abstract: Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell material, a second memory cell material on the second insulator material, and a third insulator material on the second memory cell material, forming an electrode adjacent a first side of the first memory cell material and a first side of the second memory cell material, and forming an electrode adjacent a second side of the first memory cell material and a second side of the second memory cell material.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: May 5, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Timothy A. Quick, Eugene P. Marsh
  • Patent number: 9018612
    Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: April 28, 2015
    Assignee: SK Hynix Inc.
    Inventors: Young Ho Lee, Keum Bum Lee, Min Young Lee, Hyung Suk Lee, Seung Beom Baek
  • Patent number: 9018613
    Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; and a memory cell block formed on the semiconductor substrate and configured having a plurality of memory cell arrays, each of the memory cell arrays including a plurality of column lines, a plurality of row lines, and a plurality of memory cells disposed at each of intersections of the plurality of column lines and the plurality of row lines, each of the memory cells including a variable resistance element having a transition metal oxide as a material, at least one of the plurality of column lines and the plurality of row lines being a polysilicon wiring line having polysilicon as a material, and the memory cell block including a block film between the variable resistance element of the memory cell and the polysilicon wiring line.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: April 28, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Nojiri, Hiroyuki Fukumizu, Shigeki Kobayashi, Masaki Yamato
  • Patent number: 9018037
    Abstract: Forming a resistive switching layer having a vertical interface can generate defects confined along the interface between two electrodes. The confined defects can form a pre-determined region for filament formation and dissolution, leading to low power resistive switching and low program voltage or current variability. In addition, the filament forming process of the resistive memory device can be omitted due to the existence of the confined defects.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: April 28, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Federico Nardi, Randall J. Higuchi, Robert A. Huertas, Yun Wang
  • Patent number: 9012260
    Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: April 21, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Sergey Barabash, Charlene Chen, Dipankar Pramanik
  • Patent number: 9012970
    Abstract: A memory array including a plurality of memory cells. In one embodiment, each memory cell is coupled to an electrically conductive gate material. A word line is coupled to the gate material at a contact interface level. A pair of pillars is comprised of an insulating material that extends below the contact interface level. Also, a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, forming a pair of pillars comprised of an insulating material and depositing a gate contact between the pair of pillars such that the gate contact electrically couples the gate material at a contact interface level and the insulating material extends below the contact interface level.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. BrightSky, Chung H. Lam, Gen P. Lauer
  • Patent number: RE46636
    Abstract: A nonvolatile memory device group includes: (A) a first insulating layer; (B) a second insulating layer that has a first concavity and a second concavity communicating with the first concavity and having a width larger than that of the first concavity and that is disposed on the first insulating layer; (C) a plurality of electrodes that are disposed in the first insulating layer and the top surface of which is exposed from the bottom surface of the first concavity; (D) an information storage layer that is formed on the side walls and the bottom surfaces of the first concavity and the second concavity; and (E) a conductive material layer that is filled in a space surrounded with the information storage layer in the second concavity.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: December 12, 2017
    Assignee: SONY CORPORATION
    Inventors: Jun Sumino, Motonari Honda