Abstract: A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device may include a multi-layered insulating layer formed on a semiconductor substrate, on which a lower electrode is formed. The multi-layered insulating layer may include a first hole and a second hole, concentrically formed therein, to expose the lower electrode, wherein a diameter of the first hole is larger than a diameter of the second hole. A variable resistance material layer may be formed in the second hole to contact the lower electrode, and an upper electrode may be formed in the first hole to contact the variable resistance material layer.

Abstract: A variable resistance memory device includes a plurality of first conductive lines, each of the first conductive lines extends in a first direction, a plurality of second conductive lines are above the first conductive lines, and each of the second conductive lines extend in a second direction transverse to the first direction. A plurality of first memory cells are at intersections where the first and second conductive lines overlap each other, each of the first memory cells including a first variable resistance structure having a first variable resistance pattern, a first sacrificial pattern and a second variable resistance pattern sequentially stacked in the first direction on a first plane. A plurality of third conductive lines are above the second conductive lines, each of the third conductive lines extend in the first direction, and a plurality of second memory cells are at intersections where the second and the third conductive lines overlap each other.

Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes first lines extending in a first direction; second lines extending in a second direction crossing the first direction; insulating patterns interposed between the first and second lines at first intersections of the first and second lines; and variable resistance patterns interposed between the first and the second lines at second intersections of the first and second lines. A central intersection is defined by respective central lines of the first and second lines and corresponds to a coordinate (0, 0). The first intersections are located on first to (n+1)th virtual lines, the (n+1)th virtual line having a polygonal shape in which vertexes correspond to coordinates (?(k?n), 0), (k?n, 0), (0, k?n) and (0, ?(k?n)) where k is a natural number and n is an integer in a range of 0 to (k?1).

Abstract: A memory component including first and second electrodes with a memory layer therebetween, the memory layer having first and second memory layers, the first memory layer containing aluminum and a chalcogen element of tellurium, the second memory layer between the first memory layer and the first electrode and containing an aluminum oxide and at least one of a transition metal oxide and a transition metal oxynitride having a lower resistance than the aluminum oxide.

Abstract: A photoresist pattern used for forming a pattern of a block copolymer is formed on a substrate, and then an acid solution is supplied and an alkaline solution is further supplied to the photoresist pattern so as to slim and smooth the photoresist pattern. A block copolymer solution is applied to the substrate on which the smoothed photoresist pattern has been formed, to form a film of the block copolymer, and the film is heated.

Abstract: A method for manufacturing a semiconductor device may include the following steps: preparing a substrate; preparing a first insulating layer on the substrate; preparing an electrode in the first insulating layer; preparing a second insulating layer on the first insulating layer; removing (e.g., using a dry etching process or a wet etching process) a portion of the second insulating layer to form a hole that at least partially exposes the electrode; providing a phase change material layer that may cover the electrode; and removing (e.g., using a sputtering process such as an argon sputtering process), a portion of the phase change material layer positioned inside the hole to form a phase change member that may expose a first portion of (a top side of) the electrode and may directly contact a second portion of (the top side of) the electrode.

Abstract: The present invention generally provides a method for forming a photovoltaic device including evaporating a source material to form a large molecule processing gas and flowing the large molecule processing gas through a gas distribution showerhead and into a processing area of a processing chamber having a substrate therein. The method includes generating a small molecule processing gas, and reacting the small molecule processing gas with a film already deposited on a substrate surface to form a semiconductor film. Additionally, apparatuses that may use the methods are also provided to enable continuous inline CIGS type solar cell formation.

Abstract: There is a method of selectively etching a silicon oxide film among a silicon nitride film and the silicon oxide film formed on a surface of a substrate to be processed, the method including: under a vacuum atmosphere, intermittently supplying at least one of a first processing gas composed of a hydrogen fluoride gas and an ammonia gas and a second processing gas composed of a compound of nitrogen, hydrogen and fluorine, to the substrate to be processed multiple times.

Abstract: Disclosed are Si-containing thin film forming precursors, methods of synthesizing the same, and methods of using the same to deposit silicon-containing films using vapor deposition processes for manufacturing semiconductors, photovoltaics, LCD-TFT, flat panel-type devices, refractory materials, or aeronautics.

Abstract: Various methods and devices that involve phase change material (PCM) switches are disclosed. An exemplary integrated circuit comprises an active layer with a plurality of field effect transistor (FET) channels for a plurality of FETs. The integrated circuit also comprises an interconnect layer comprising a plurality of conductive interconnects. The plurality of conductive interconnects couple the plurality of field effect transistors. The integrated circuit also comprises an insulator layer covering at least a portion of the interconnect layer. The integrated circuit also comprises a channel of a radio-frequency (RF) PCM switch. The channel of the RF PCM switch is formed on the insulator layer.

Abstract: A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device may include a multi-layered insulating layer formed on a semiconductor substrate, on which a lower electrode is formed. The multi-layered insulating layer may include a first hole and a second hole, concentrically formed therein, to expose the lower electrode, wherein a diameter of the first hole is larger than a diameter of the second hole. A variable resistance material layer may be formed in the second hole to contact the lower electrode and an upper electrode may be formed in the first hole to contact the variable resistance material layer.

Abstract: An ink for forming a compound semiconductor thin film is provided, which contains a binder includes a compound includes an S atom or an Se atom and metallic compound particles which are both dispersed in an organic solvent. A compound semiconductor thin film is formed by applying or printing the ink for forming a compound semiconductor thin film and heat-treating it. A solar cell is constituted, which has a light-absorbing layer formed of the compound semiconductor thin film.

Abstract: A memory device includes an array of electrodes that includes thin film plates of electrode material. Multilayer strips are arranged as bit lines over respective columns in the array of electrodes, including a layer of memory material and a layer of top electrode material. The multilayer strips have a primary body and a protrusion having a width less than that of the primary body and is self-aligned with contact surfaces on the thin film plates. Memory material in the protrusion contacts surfaces on the distal ends of thin film plates of electrodes in the corresponding column in the array. The device can be made using a damascene process in self-aligned forms over the contact surfaces.

Abstract: A vertical MOSFET transistor is formed in a body of semiconductor material having a surface. The transistor includes a buried conductive region of a first conductivity type; a channel region of a second conductivity type, arranged on top of the buried conductive region; a surface conductive region of the first conductivity type, arranged on top of the channel region and the buried conductive region; a gate insulation region, extending at the sides of and contiguous to the channel region; and a gate region extending at the sides of and contiguous to the gate insulation region.

Abstract: A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size.

Abstract: An integrated circuit device including a resistive random access memory (RRAM) cell formed over a substrate. The RRAM cell includes a top electrode having an upper surface. A blocking layer covers a portion of the upper surface. A via extends above the top electrode within a matrix of dielectric. The upper surface of the top electrode includes an area that interfaces with the blocking layer and an area that interfaces with the via. The area of the upper surface that interfaces with the via surrounds the area of the upper surface that interfaces with the blocking layer. The blocking layer is functional during processing to protect the RRAM cell from etch damage while being structured in such a way as to not interfere with contact between the overlying via and the top electrode.

Abstract: Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can created comprising a non-stoichimetric sub-oxide that can be a combination of multiple silicon and/or silicon oxide layers with an aggregate chemical formula of SiOX, where X can be a non-integer greater than zero and less than 2. The sub-oxide can be created in a variety of ways, including various techniques related to growing the sub-oxide, depositing the sub-oxide, or transforming an extant film into the sub-oxide.

Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.

Abstract: A method of removing a hard mask used for patterning gate stacks including patterning gate stacks on a substrate, wherein the hard mask is deposited over the gate stacks. The method further includes depositing a dielectric layer on the substrate after the gate stacks are patterned and planarizing a first portion of the dielectric layer. The method further includes removing a second portion of the dielectric layer and the hard mask by using an etching gas and etching the remaining dielectric layer by using a wet etching chemistry.

Abstract: Vapor deposition apparatus for forming stacked thin films on discrete photovoltaic module substrates conveyed in a continuous non-stop manner through the apparatus are provided. The apparatus includes a first sublimation compartment positioned over a first deposition area of said apparatus, a second sublimation compartment positioned over a second deposition area of said apparatus, and an internal divider positioned therebetween and defining a middle seal member. An actuator is attached to the internal divider and is configured to move the internal divider to control intermixing of first source material vapors and second source material vapors within the first deposition area and the second deposition area. Methods are also generally provided for depositing stacked thin films on a substrate.

Abstract: Methods of forming a material include exposing a substrate to a first germanium-containing compound and a second, different germanium-containing compound; exposing the substrate to a first antimony-containing compound and a second, different antimony-containing compound; and exposing the substrate to a first tellurium-containing compound and a second, different tellurium-containing compound. Methods of forming chalcogenide materials include exposing a substrate to a first precursor comprising a reactive precursor of a first metal and a co-reactive precursor of the first metal, the reactive precursor and the co-reactive precursor each having at least one ligand coordinated to an atom of the first metal, wherein the at least one ligand of the co-reactive precursor is different from the at least one ligand of the reactive precursor. The substrate is also exposed to a reactive antimony precursor and a co-reactive antimony precursor and to a reactive tellurium precursor and a co-reactive tellurium precursor.

Abstract: A method for fabricating a semiconductor device includes supplying a first source gas including a germanium (Ge) precursor onto a semiconductor substrate for a first time period, and periodically interrupting the supplying of the first source gas for the first time period to form Ge elements on the semiconductor substrate.

Abstract: A memory device includes a first plurality of memory cells arranged in a first crossbar array, a first thickness of dielectric material overlying the first plurality of memory cells, and a second plurality of memory cells arranged in a second crossbar array overlying the first thickness of dielectric material. The memory device further includes a second thickness of dielectric material overlying the second plurality of memory cells. In a specific embodiment, the memory device further includes a Nth thickness of dielectric material overlying an Nth plurality of memory cells, where N is an integer ranging from 3 to 8.

Abstract: Precursors for use in depositing antimony-containing films on substrates such as wafers or other microelectronic device substrates, as well as associated processes of making and using such precursors, and source packages of such precursors. The precursors are useful for deposition of Ge2Sb2Te5 chalcogenide thin films in the manufacture of nonvolatile Phase Change Memory (PCM) or for the manufacturing of thermoelectric devices, by deposition techniques such as chemical vapor deposition (CVD) and atomic layer deposition (ALD).

Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a bottom structure including a heating electrode, data storage materials, each of the data storage materials formed on the bottom structure in a confined structure perpendicular to the bottom structure, and having a lower diameter smaller than an upper diameter, an upper electrode formed on each of the data storage materials, and an insulation unit formed between adjacent data storage materials.

Abstract: Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell material, a second memory cell material on the second insulator material, and a third insulator material on the second memory cell material, forming an electrode adjacent a first side of the first memory cell material and a first side of the second memory cell material, and forming an electrode adjacent a second side of the first memory cell material and a second side of the second memory cell material.

Abstract: Forming a resistive switching layer having a vertical interface can generate defects confined along the interface between two electrodes. The confined defects can form a pre-determined region for filament formation and dissolution, leading to low power resistive switching and low program voltage or current variability. In addition, the filament forming process of the resistive memory device can be omitted due to the existence of the confined defects.

Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; and a memory cell block formed on the semiconductor substrate and configured having a plurality of memory cell arrays, each of the memory cell arrays including a plurality of column lines, a plurality of row lines, and a plurality of memory cells disposed at each of intersections of the plurality of column lines and the plurality of row lines, each of the memory cells including a variable resistance element having a transition metal oxide as a material, at least one of the plurality of column lines and the plurality of row lines being a polysilicon wiring line having polysilicon as a material, and the memory cell block including a block film between the variable resistance element of the memory cell and the polysilicon wiring line.

Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.

Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

Abstract: A nonvolatile memory device contains a resistive switching memory element with improved device switching performance and life and methods for forming the same. The nonvolatile memory device has a first layer on a substrate, a resistive switching layer on the first layer, and a second layer. The resistive switching layer is disposed between the first layer and the second layer and the resistive switching layer comprises a material having the same morphology as the top surface of the first layer. A method of forming a nonvolatile memory element in a ReRAM device includes forming a resistive switching layer on a first layer and forming a second layer, so that the resistive switching layer is disposed between the first layer and the second layer. The resistive switching layer comprises a material formed with the same morphology as the top surface of the first layer.

Abstract: A memory array including a plurality of memory cells. In one embodiment, each memory cell is coupled to an electrically conductive gate material. A word line is coupled to the gate material at a contact interface level. A pair of pillars is comprised of an insulating material that extends below the contact interface level. Also, a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, forming a pair of pillars comprised of an insulating material and depositing a gate contact between the pair of pillars such that the gate contact electrically couples the gate material at a contact interface level and the insulating material extends below the contact interface level.

Abstract: A semiconductor device includes a first semiconductor layer extending in a first direction on a substrate, a plurality of second semiconductor layers spaced apart in the first direction on the first semiconductor layer, and an insulation layer structure surrounding side walls of the first semiconductor layer and the plurality of second semiconductor layers. The first semiconductor layer may have a first conductivity type, and the plurality of second semiconductor layers may have a second conductivity type.

Abstract: A method is provided for fabricating a phase change memory. The method includes providing a semiconductor substrate having a bottom electrode connecting with one or more semiconductor devices, and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a loop-shape electrode in the first dielectric layer, and forming a second dielectric layer having a first opening exposing a portion of the first dielectric layer and a portion of the loop-shape electrode. Further, the method includes forming a phase change layer in the first opening of the second dielectric layer such that a contact area between the phase change layer and the loop-shape electrode may be controlled to achieve desired contact, and forming a top electrode.

Abstract: Provided are resistive random access memory (ReRAM) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in ReRAM cells often need to have at least one inert interface such that substantially no materials pass through this interface. The other (reactive) interface may be used to introduce and remove defects from the resistive switching layers causing the switching. While some electrode materials, such as platinum and doped polysilicon, may form inert interfaces, these materials are often difficult to integrate. To expand electrode material options, a diffusion barrier layer is disposed between an electrode and a resistive switching layer and forms the inert interface with the resistive switching layer. In some embodiments, tantalum nitride and titanium nitride may be used for electrodes separated by such diffusion barrier layers.

Abstract: A method of forming a thin layer and a method of manufacturing a phase change memory device, the method of forming a thin layer including providing a first deposition source onto a substrate, the first deposition source not including tellurium; and providing a second deposition source onto the substrate, the second deposition source including a first tellurium precursor represented by the following Formula 1 and a second tellurium precursor represented by following the Formula 2: Te(CH(CH3)2)2??Formula 1 Ten(CH(CH3)2)2??Formula 2 wherein, in Formula 2, n is an integer greater than or equal to 2.

Abstract: Memory cells and memory cell structures having a number of phase change material gradients, devices utilizing the same, and methods of forming the same are disclosed herein. One example of forming a memory cell includes forming a first electrode material, forming a phase change material gradient on the first electrode material, and forming a second electrode material on the phase change material gradient.

Abstract: Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 ? and about 100 ?, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.

Abstract: Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands. In some embodiments, there may be least two of the chalcogenide bands and at least one of the non-chalcogenide bands. In some embodiments, the memory cells may be between a pair of electrodes; with one of the electrodes being configured as a lance, angled plate, container or beam. In some embodiments, the memory cells may be electrically coupled with select devices, such as, for example, diodes, field effect transistors or bipolar junction transistors.

Abstract: Semiconductor devices, and methods of manufacturing the same, include a field region in a semiconductor substrate to define an active region. An interlayer insulating layer is on the semiconductor substrate. A semiconductor pattern is within a hole vertically extending through the interlayer insulating layer. The semiconductor pattern is in contact with the active region. A barrier region is between the semiconductor pattern and the interlayer insulating layer. The barrier region includes a first buffer dielectric material and a barrier dielectric material. The first buffer dielectric material is between the barrier dielectric material and the semiconductor pattern, and the barrier dielectric material is spaced apart from both the semiconductor pattern and the active region.

Abstract: Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The laterally constricted portions of adjacent memory cells are vertically offset and positioned on opposite sides of the memory device. Also disclosed are memory devices having a plurality of memory cells, with each memory cell including first and second electrodes having different widths. Adjacent memory cells have the first and second electrodes offset on vertically opposing sides of the memory device. Methods of forming the memory devices are also disclosed.

Abstract: Embodiments of the invention include a nonvolatile memory device that contains nonvolatile resistive random access memory device with improved device performance and lifetime. In some embodiments, nonvolatile resistive random access memory device includes a diode, a metal silicon nitride embedded resistor, and a resistive switching layer disposed between a first electrode layer and a second electrode layer. In some embodiments, the method of forming a resistive random access memory device includes forming a diode, forming a metal silicon nitride embedded resistor, forming a first electrode layer, forming a second electrode layer, and forming a resistive switching layer disposed between the first electrode layer and the second electrode layer.

Abstract: A phase change memory cell, an array of the phase change memory cells, and a method for fabricating the phase change memory cells. The phase change memory cell includes a bottom electrode, a heating element, and a heat shield. During programming of the phase change memory cell, the bottom electrode passes current to the phase change memory cell. The heating element is electrically coupled to the bottom electrode and generates heat during the programming of the phase change memory cell. The heat shield is thermally conductive and surrounds at least a portion of the heating element. The heat shield conducts heat generated during programming of the phase change memory cell to the bottom electrode.

Abstract: Provided are apparatus and methods for forming phase change layers, and methods of manufacturing a phase change memory device. A source material is supplied to a reaction chamber, and purges from the chamber. A pressure of the chamber is varied according to the supply of the source material and the purge of the source material.

Abstract: Control elements that can be suitable for nonvolatile memory device applications are disclosed. The control element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The control element can be based on multilayer dielectric stacks. The control element can include a titanium oxide-silicon-titanium oxide multilayer stack. Electrode materials may include one of ruthenium, titanium nitride, or carbon. The control element can include a silicon nitride-silicon-silicon nitride multilayer stack. Electrode materials may include titanium nitride.

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A ReRAM cell includes an embedded resistor and a resistive switching layer connected in series with this resistor. The resistor is configured to prevent over-programming of the cell by limiting electrical currents through the resistive switching layer. Unlike the resistive switching layer, which changes its resistance in order to store data, the embedded resistor maintains a substantially constant resistance during operation of the cell. The embedded resistor is formed from tantalum nitride and silicon nitride. The atomic ratio of tantalum and silicon may be specifically selected to yield resistors with desired densities and resistivities as well as ability to remain amorphous when subjected to various annealing conditions. The embedded resistor may also function as a diffusion barrier layer and prevent migration of components between one of the electrodes and the resistive switching layer.

Abstract: A CIGS film production method is provided which ensures that a CIGS film having a higher conversion efficiency can be produced at lower costs at higher reproducibility even for production of a large-area device. A CIGS solar cell production method is also provided for producing a CIGS solar cell including the CIGS film. The CIGS film production method includes: a stacking step of stacking a layer (A) containing indium, gallium and selenium and a layer (B) containing copper and selenium in a solid phase in this order over a substrate; and a heating step of heating a stacked structure including the layer (A) and the layer (B) to melt a compound of copper and selenium of the layer (B) into a liquid phase to thereby diffuse copper from the layer (B) into the layer (A) to permit crystal growth to provide a CIGS film.

Abstract: A resistive random access memory (ReRAM) includes a first metal layer having a first metal and a metal-oxide layer on the first metal layer. The metal-oxide layer includes the first metal. The ReRAM further includes a second metal layer over the metal-oxide layer and a first continuous conductive barrier layer in physical contact with sidewalls of the first metal layer and of the metal-oxide layer.

Abstract: A nonvolatile memory device group includes: (A) a first insulating layer; (B) a second insulating layer that has a first concavity and a second concavity communicating with the first concavity and having a width larger than that of the first concavity and that is disposed on the first insulating layer; (C) a plurality of electrodes that are disposed in the first insulating layer and the top surface of which is exposed from the bottom surface of the first concavity; (D) an information storage layer that is formed on the side walls and the bottom surfaces of the first concavity and the second concavity; and (E) a conductive material layer that is filled in a space surrounded with the information storage layer in the second concavity.