Having Diamond Semiconductor Component Patents (Class 438/105)
  • Patent number: 10680067
    Abstract: The present disclosure discloses a self-aligned silicon carbide MOSFET device with an optimized P+ region and a manufacturing method thereof. The self-aligned silicon carbide MOSFET device is formed by a plurality of silicon carbide MOSFET device cells connected in parallel, and these silicon carbide MOSFET device cells are arranged evenly. The silicon carbide MOSFET device cell comprises two source electrodes, one gate electrode, one gate oxide layer, two N+ source regions, two P+ contact regions, two P wells, one N? drift layer, one buffer layer, one N+ substrate, one drain electrode and one isolation dielectric layer.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: June 9, 2020
    Assignees: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES, ZHUZHOU CRRC TIMES ELECTRIC CO., LTD.
    Inventors: Yidan Tang, Huajun Shen, Yun Bai, Jingtao Zhou, Chengyue Yang, Xinyu Liu, Chengzhan Li, Guoyou Liu
  • Patent number: 10665798
    Abstract: A method for manufacturing a semiconductor device includes forming a dielectric layer on a substrate, forming a first carbon nanotube (CNT) layer on the dielectric layer at a first portion of the device corresponding to a first doping type, forming a second CNT layer on the dielectric layer at a second portion of the device corresponding to a second doping type, forming a plurality of first contacts on the first CNT layer, and a plurality of second contacts on the second CNT layer, performing a thermal annealing process to create end-bonds between the plurality of the first and second contacts and the first and second CNT layers, respectively, depositing a passivation layer on the plurality of the first and second contacts, and selectively removing a portion of the passivation layer from the plurality of first contacts.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Shu-Jen Han, Jianshi Tang
  • Patent number: 10665799
    Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer on a substrate, forming a carbon nanotube (CNT) layer on the first dielectric layer, forming a second dielectric layer on the carbon nanotube (CNT) layer, patterning a plurality of trenches in the second dielectric layer exposing corresponding portions of the carbon nanotube (CNT) layer, forming a plurality of contacts respectively in the plurality of trenches on the exposed portions of the carbon nanotube (CNT) layer, performing a thermal annealing process to create end-bonds between the plurality of the contacts and the carbon nanotube (CNT) layer, and depositing a passivation layer on the plurality of the contacts and the second dielectric layer.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Shu-Jen Han, Jianshi Tang
  • Patent number: 10453950
    Abstract: In one general aspect, an apparatus can include a silicon carbide (SiC) device can include a gate dielectric, a first doped region having a first conductivity type, a source, a body region of the first conductivity type, and a second doped region having a second conductivity type. The second doped region can have a first portion and a second portion. The first portion can be disposed between the first doped region and the body region and the second portion can be disposed between the first doped region and the gate dielectric. The first portion of the second doped region can have a width less than a width of the first doped region.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: October 22, 2019
    Inventor: Martin Domeij
  • Patent number: 10048204
    Abstract: Described herein are microfluidic devices and methods of detecting an analyte in a sample that includes flowing the sample though a microfluidic device, wherein the presence of the analyte is detected directly from the microfluidic device without the use of an external detector at an outlet of the microfluidic device. In a more specific aspect, detection is performed by incorporating functional nanopillars, such as detector nanopillars and/or light source nanopillars, into a microchannel of a microfluidic device.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: August 14, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yann Astier, Huan Hu, Ning Li, Devendra K. Sadana, Joshua T. Smith, William T. Spratt
  • Patent number: 10036728
    Abstract: An ion detection device has a strip of carbon-based nanomaterial (CNM) film and a chamber enclosing the CNM film. A low bias voltage is applied at the ends of the CNM film strip, and ions present in the chamber are detected by a change in the magnitude of current flowing through the CNM film under the bias. Also provided are methods for fabricating the device, methods for measuring pressure of a gas, and methods for monitoring or quantifying an ionizing radiation using the device.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: July 31, 2018
    Assignee: Northeastern University
    Inventors: Bo Li, Ji Hao, Hyun Young Jung, Yung Joon Jung, Swastik Kar
  • Patent number: 9696222
    Abstract: A UNCD nanowire comprises a first end electrically coupled to a first contact pad which is disposed on a substrate. A second end is electrically coupled to a second contact pad also disposed on the substrate. The UNCD nanowire is doped with a dopant and disposed over the substrate. The UNCD nanowire is movable between a first configuration in which no force is exerted on the UNCD nanowire and a second configuration in which the UNCD nanowire bends about the first end and the second end in response to a force. The UNCD nanowire has a first resistance in the first configuration and a second resistance in the second configuration which is different from the first resistance. The UNCD nanowire is structured to have a gauge factor of at least about 70, for example, in the range of about 70 to about 1,800.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: July 4, 2017
    Assignee: UCHICAGO ARGONNE, LLC
    Inventors: Anirudha V. Sumant, Xinpeng Wang
  • Patent number: 9679804
    Abstract: A method includes forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer, forming a capping layer over the carbon-containing layer, forming a first photo resist over the capping layer, and etching the capping layer and the carbon-containing layer using the first photo resist as a first etching mask. The first photo resist is then removed. A second photo resist is formed over the capping layer. The capping layer and the carbon-containing layer are etched using the second photo resist as a a second etching mask. The second photo resist is removed. A third photo resist under the carbon-containing layer is etched using the carbon-containing layer as etching mask. A dielectric layer underlying the third photo resist is etched to form via openings using the third photo resist as etching mask. The via openings are filled with a conductive material.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Kai Chen, Jung-Hau Shiu, Chia Cheng Chou, Chung-Chi Ko, Tze-Liang Lee, Chih-Hao Chen, Shing-Chyang Pan
  • Patent number: 9608068
    Abstract: A method is provided for forming an integrated circuit. A trench is formed in a substrate. Subsequently, a silicon-germanium feature is formed in the trench, and an etch stop layer is formed on the substrate and on the silicon-germanium feature. Lastly, a silicon device layer is formed on the etch stop layer. The silicon device layer has a tensily-strained region overlying the silicon-germanium feature. Regions of the silicon device layer not overlying the silicon-germanium feature are less strained than the tensily-strained region. The tensily-strained region of the silicon device layer may be further processed into channel features in n-type field effect transistors with improved charge carrier mobilities and device drive currents.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Hong He, Alexander Reznicek
  • Patent number: 9418814
    Abstract: A method of forming a field emitter comprises disposing a first layer on a substrate. The first layer is seeded with nanodiamond particles. The substrate with the first layer disposed thereon is maintained at a first temperature and a first pressure in a mixture of gases which includes nitrogen. The first layer is exposed to a microwave plasma to form a nitrogen doped ultrananocrystalline diamond film on the first layer, which has a percentage of nitrogen in the range of about 0.05 atom % to about 0.5 atom %. The field emitter has about 1012 to about 1014 emitting sites per cm2. A photocathode can also be formed similarly by forming a nitrogen doped ultrananocrystalline diamond film on a substrate similar to the field emitter, and then hydrogen terminating the film. The photocathode is responsive to near ultraviolet light as well as to visible light.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: August 16, 2016
    Assignee: UCHICAGO ARGONNE, LLC
    Inventors: Anirudha V. Sumant, Sergey V. Baryshev, Sergey P. Antipov
  • Patent number: 9263698
    Abstract: A flexible display apparatus includes a flexible substrate, a display layer disposed on one surface of the flexible substrate and including a plurality of pixels, graphene disposed on a surface opposing the one surface of the flexible substrate, and an encapsulation layer covering the display layer.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: February 16, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung-Ho Choi, Hyun-Woo Joo, Myung-Soo Huh
  • Patent number: 9184306
    Abstract: A silicon carbide semiconductor device of the present invention comprises a silicon carbide drift layer formed on a silicon carbide substrate, a P-type region formed in a surface layer of the silicon carbide drift layer, and a Schottky electrode formed above the silicon carbide drift layer correspondingly to a forming portion of the P-type region. The P-type region is formed of a plurality of unit cells arranged therein. Each of the unit cells has at least a first distribution region in which the P-type impurity is distributed at first concentration and a second distribution region in which the P-type impurity is distributed at second concentration higher than the first concentration. With this structure, it is possible to provide a silicon carbide semiconductor device in which a sufficient breakdown voltage can be achieved with less number of ion implantations.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: November 10, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takeshi Kitani, Yoichiro Tarui
  • Patent number: 9040345
    Abstract: A method of laser ablation for electrical contact to a buried electrically conducting layer in diamond comprising polishing a single crystal diamond substrate having a first carbon surface, implanting the diamond with a beam of 180 KeV followed by 150 KeV C+ ions at fluencies of 4×1015 ions/cm2 and 5×1015 ions/cm2 respectively, forming an electrically conducting carbon layer beneath the first carbon surface, and ablating the single crystal diamond which lies between the electrically conducting layer and the first carbon surface.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 26, 2015
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Bradford B. Pate, Matthew P. Ray, Jeffrey W. Baldwin
  • Patent number: 9018640
    Abstract: A silicon carbide power device equipped with termination structure comprises a silicon carbide substrate, a power element structure and a termination structure. The silicon carbide substrate contains a drift layer which has a first conductivity and includes an active zone and a termination zone. The power element structure is located in the active zone. The termination structure is located in the termination zone and has a second conductivity, and includes at least one first doped ring abutting and surrounding the power element structure and at least one second doped ring surrounding the first doped ring. The first doped ring has a first doping concentration smaller than that of the second doped ring and a first doping depth greater than that of the second doped ring, thereby can increase the breakdown voltage of the silicon carbide power device.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: April 28, 2015
    Assignee: Hestia Power Inc.
    Inventors: Chien-Chung Hung, Cheng-Tyng Yen, Lurng-Shehng Lee, Chwan-Ying Lee
  • Publication number: 20150108505
    Abstract: Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The system may include a diamond material having n-type donor atoms and a diamond lattice, wherein 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K. The method of fabricating diamond semiconductors may include the steps of selecting a diamond material having a diamond lattice; introducing a minimal amount of acceptor dopant atoms to the diamond lattice to create ion tracks; introducing substitutional dopant atoms to the diamond lattice through the ion tracks; and annealing the diamond lattice.
    Type: Application
    Filed: December 23, 2014
    Publication date: April 23, 2015
    Inventor: Khan Adam
  • Patent number: 9006027
    Abstract: An electrical device includes a blocking layer disposed on top of a substrate layer, wherein the blocking layer and the substrate layer each are wide bandgap semiconductors, and the blocking layer and the substrate layer form a buried junction in the electrical device. The device comprises a termination feature disposed at a surface of the blocking layer and a filled trench disposed proximate to the termination feature. The filled trench extends through the blocking layer to reach the substrate layer and is configured to direct an electrical potential associated with the buried junction toward the termination feature disposed near the surface of the blocking layer to terminate the buried junction.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: April 14, 2015
    Assignee: General Electric Company
    Inventors: Zachary Matthew Stum, Ahmed Elasser, Stephen Daley Arthur, Stanislav I. Soloviev, Peter Almern Losee
  • Patent number: 9006747
    Abstract: Provided are a technology that simply forms a particular crystal surface such as a {03-38} surface having high carrier mobility in trench sidewalls and a SiC semiconductor element where most of the trench sidewalls appropriate for a channel member are formed from {03-38} surfaces. A trench structure formed in a (0001) surface or an off-oriented surface of a (0001) surface with an offset angle 8° or lower of SiC is provided. The channel member is in the trench structure. At least 90% of the area of the channel member is a {03-38} surface or a surface that a {03-38} surface offset by an angle from ?8° to 8° in the <1-100> direction. Specifically, the trench sidewalls are finished to {03-38} surfaces by applying a thermal etching to a trench with (0001) surfaces of SiC. Thermal etching is conducted in a chlorine atmosphere above 800° C. with nitrogen gas as the carrier.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: April 14, 2015
    Assignee: National University Corporation Nara Institute of Science and Technology
    Inventors: Tomoaki Hatayama, Hidenori Koketsu, Yoshihiro Todokoro
  • Patent number: 8993375
    Abstract: Method for synthesizing a material by chemical vapor deposition (CVD), according to which a plasma is created in a vacuum chamber in the vicinity of a substrate, and according to which a carbon-carrying substance and H2 are introduced into the chamber in order to produce in the chamber a gas comprising substances carrying reactive-carbon atoms in the form of unsaturated molecules or radicals from which the synthesis of said material will be performed, and in that the electromagnetic absorption and inelastic diffusion spectra of the solid material to be synthesized are used to take from these spectra the absorption frequencies that contribute to the reactions that lead to the formation of the solid material to be synthesized, and in that energetic rays are produced in the form of a photon beam carrying quantities of energy determined by each of the frequencies corresponding to said absorption and inelastic diffusion frequencies, said photon beam being injected into the plasma where, for energy states of the so
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: March 31, 2015
    Assignee: Diarotech
    Inventor: Horacio Tellez Oliva
  • Patent number: 8975642
    Abstract: Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: March 10, 2015
    Assignee: Semiconductor Manufacturing International Corp
    Inventors: Neil Zhao, Mieno Fumitake
  • Publication number: 20150060885
    Abstract: A semiconductor device according to an embodiment includes an i-type or a p-type first diamond semiconductor layer, an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer, a mesa structure and an n-type first diamond semiconductor region provided on the side surface. The mesa structure includes the first diamond semiconductor layer, the second diamond semiconductor layer, a top surface with a plane orientation of ±10 degrees or less from a {100} plane, and a side surface inclined by 20 to 90 degrees with respect to a direction of <011>±20 degrees from the {100} plane. The first diamond semiconductor region is in contact with the second diamond semiconductor layer and has an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mariko SUZUKI, Tadashi SAKAI, Chiharu OTA, Kazuto TAKAO, Takashi SHINOHE
  • Publication number: 20150054000
    Abstract: A method for treating a surface of a diamond thin film according to one aspect of the present invention performs one of a first substitution process for substituting part of hydrogen-terminals of a diamond thin film with fluorine-terminals in the absence of a fluorocarbon deposition on the surface of diamond thin film and a second substitution process for substituting part of hydrogen-terminals of a diamond thin film with fluorine-terminals in the presence of the fluorocarbon deposition on the surface of diamond thin film based on required surface properties of the diamond thin film.
    Type: Application
    Filed: August 25, 2014
    Publication date: February 26, 2015
    Applicants: WASEDA UNIVERSITY, YOKOGAWA ELECTRIC CORPORATION
    Inventors: Yukihiro SHINTANI, Toshiyuki SARUYA, Hiroshi KAWARADA
  • Publication number: 20150014707
    Abstract: The invention relates to a method for producing a component comprising a conductive grid insulated from a semiconductor monocrystalline diamond substrate by an insulating region, comprising the following steps: a) oxygenating the surface of the substrate so as to replace the hydrogen surface terminations of the substrate with oxygen surface terminations; and b) forming the insulating region on the surface of the substrate by repeated monatomic layer deposition.
    Type: Application
    Filed: December 20, 2012
    Publication date: January 15, 2015
    Applicant: Universite Joseph Fourier
    Inventors: Gauthier Chicot, Aurélien Marechal, Pierre Muret, Julien Pernot
  • Patent number: 8932904
    Abstract: A semiconductor device including a graphene layer and a method of manufacturing the same are disclosed. A method in which graphene is grown on a catalyst metal by a chemical vapor deposition or the like is known. However, the graphene cannot be used as a channel, since the graphene is in contact with the catalyst metal, which is conductive. There is disclosed a method in which a catalyst film (2) is formed over a substrate (1), a graphene layer (3) is grown originating from the catalyst film (2), an electrode (4) in contact with the graphene layer (3) is formed, and the catalyst film (2) is removed.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: January 13, 2015
    Assignee: Fujitsu Limited
    Inventors: Daiyu Kondo, Shintaro Sato
  • Patent number: 8900918
    Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Phaedon Avouris, Kuan-Neng Chen, Damon Farmer, Yu-Ming Lin
  • Patent number: 8878190
    Abstract: A semiconductor device according to the present embodiment includes a diamond substrate having a surface plane inclined from a (100) plane in a range of 10 degrees to 40 degrees in a direction of <011>±10 degrees, and an n-type diamond semiconductor layer containing phosphorus (P) and formed above the surface plane described above.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: November 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mariko Suzuki, Tadashi Sakai, Naoshi Sakuma, Masayuki Katagiri, Yuichi Yamazaki
  • Publication number: 20140319542
    Abstract: The present invention provides a conducting material comprising a carbon-based material selected from a diamond or an insulating diamond-like carbon, having a hydrogen-terminated surface and a layer of MoO3 coating said surface; as well as a method for the fabrication of such a material. The conducting material of the invention is useful in the fabrication of electronic components, electrodes, sensors, diodes, field effect transistors, and field emission electron sources.
    Type: Application
    Filed: April 24, 2014
    Publication date: October 30, 2014
    Applicant: Technion Research and Development Foundation Ltd.
    Inventors: Rafi KALISH, Moshe TORDJMAN
  • Patent number: 8865519
    Abstract: A method of manufacturing a silicon carbide structure includes forming a silicon carbide layer by depositing silicon carbide on a base plate by chemical vapor deposition, removing the base plate, decreasing electrical conductivity by heat-treating the silicon carbide structure, and removing a thickness of 200 ?m from an upper surface and a lower surface of the silicon carbide structure. In the present invention, silicon carbide is deposited by a CVD method, and the electrical conductivity of the silicon carbide is reduced to the electrical conductivity required for a protection ring of a plasma device through a post-treatment and a post-process. The electrical conductivity may be adjusted even without using separate additives.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: October 21, 2014
    Assignee: Tokai Carbon Korea Co., Ltd.
    Inventors: Joung Il Kim, Jae Seok Lim, Mi-Ra Yoon
  • Patent number: 8866157
    Abstract: A semiconductor device may include a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a source electrode and a drain electrode in contact with the first semiconductor layer or the second semiconductor layer, an opening formed in the second semiconductor layer, an insulating film formed on an inner surface of the opening formed in the second semiconductor layer and above the second semiconductor layer, a gate electrode formed in the opening via the insulating film, and a protective film formed on the insulating film and including an amorphous film containing carbon as a major component.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: October 21, 2014
    Assignee: Fujitsu Limited
    Inventors: Norikazu Nakamura, Shirou Ozaki, Masayuki Takeda, Toyoo Miyajima, Toshihiro Ohki, Masahito Kanamura, Kenji Imanishi, Toshihide Kikkawa, Keiji Watanabe
  • Patent number: 8859420
    Abstract: A method of fabricating an interconnect element may include fabricating a metal layer that overlies a carrier layer and that includes a plurality of metal traces; providing a dielectric element to overlie the metal layer and the carrier layer; providing a plurality of metal posts; and removing the carrier layer to expose the first major surface of the dielectric element and the outer surfaces of the plurality of metal traces.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: October 14, 2014
    Assignee: Invensas Corporation
    Inventors: Kimitaka Endo, Norihito Masuda, Tomokazu Shimada
  • Patent number: 8852998
    Abstract: A method including forming a diamond material on the surface of a substrate; forming a first contact and a separate second contact; and patterning the diamond material to form a nanowire between the first contact and the second contact. An apparatus including a first contact and a separate second contact on a substrate; and a nanowire including a single crystalline or polycrystalline diamond material on the substrate and connected to each of the first contact and the second contact.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: October 7, 2014
    Assignee: Sandia Corporation
    Inventors: Alfredo M. Morales, Richard J. Anderson, Nancy Y. C. Yang, Jack L. Skinner, Michael J. Rye
  • Patent number: 8847238
    Abstract: A semiconductor layer 102 having a drift region 132, a body region 103, and a source region 104 provided at a position next to the body region 103; an epitaxial layer 106 in contact with the body region; and a gate insulating film 107 provided on the epitaxial layer are formed on a principal surface of a semiconductor substrate 101. The epitaxial layer includes an interface epitaxial layer 106i in contact with the body region, a first epitaxial layer 106a on the interface epitaxial layer 106i, and a second epitaxial layer 106b on the first epitaxial layer 106a. An impurity concentration of the interface epitaxial layer is higher than an impurity concentration of the first epitaxial layer, and lower than an impurity concentration of the second epitaxial layer.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: September 30, 2014
    Assignee: Panasonic Corporation
    Inventors: Tsutomu Kiyosawa, Masao Uchida, Nobuyuki Horikawa, Koutarou Tanaka, Kazuhiro Kagawa, Yasuyuki Yanase, Takashi Hasegawa
  • Publication number: 20140264385
    Abstract: A method is provided for fabricating a wafer of semiconductor material intended for use for the integration of electronic and/or optical and/or optoelectronic devices. The method comprises: providing a starting wafer of crystalline silicon (205); on the starting wafer of crystalline silicon, epitaxially growing a buffer layer (210) consisting of a sub-stoichiometric alloy of silicon and germanium; epitaxially growing on the buffer layer a layer (225) of a semiconductor material having an energy gap greater than that of the crystalline silicon constituting the starting wafer, wherein the layer of semiconductor material having an energy gap greater than that of the crystalline silicon is grown so to have a thickness capable of constituting a substrate for the integration therein of electronic and/or optical and/or optoelectronic devices.
    Type: Application
    Filed: July 25, 2012
    Publication date: September 18, 2014
    Applicant: Consiglio Nazionale delle Ricerche
    Inventors: Camarda Massimo, Andrea Severino, Francesco La Via
  • Publication number: 20140264319
    Abstract: An organic material with a porous interpenetrating network and an amount of inorganic material at least partially distributed within the porosity of the organic material is disclosed. A method of producing the organic-inorganic thin films and devices therefrom comprises seeding with nanoparticles and depositing an amorphous material on the nanoparticles.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: THE BOEING COMPANY
    Inventor: The Boeing Company
  • Patent number: 8835892
    Abstract: Methods in accordance with this invention form a microelectronic structure by forming a carbon nano-tube (“CNT”) layer, and forming a boron nitride layer (“BN liner”) above the CNT layer, wherein the BN liner comprises: (1) a first portion disposed above and in contact with the CNT layer; and/or (2) a second portion disposed in and/or around one or more carbon nano-tubes in the CNT layer. Numerous other aspects are provided.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: September 16, 2014
    Assignee: SanDisk 3D LLC
    Inventor: Wipul Pemsiri Jayasekara
  • Patent number: 8822315
    Abstract: A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: September 2, 2014
    Assignee: Cree, Inc.
    Inventors: Davis Andrew McClure, Alexander Suvorov, John Adam Edmond, David Beardsley Slater, Jr.
  • Publication number: 20140242750
    Abstract: The present invention provides a polishing slurry capable of polishing even high-hardness materials such as silicon carbide and gallium nitride at a high polishing speed. The present invention is a polishing slurry including a slurry containing a manganese oxide particle and a manganate ion for polishing high-hardness materials having a Mohs hardness of 8 or higher. In the present invention, the manganese oxide particle in the slurry is preferably 1.0 mass % or more; the manganese oxide is preferably manganese dioxide; and the manganate ion is preferably permanganate ion. The polishing slurry according to the present invention enables even high-hardness hardly-machinable materials such as silicon carbide and gallium nitride to be polished smoothly at a high speed.
    Type: Application
    Filed: October 12, 2012
    Publication date: August 28, 2014
    Inventors: Ryuichi Sato, Yohei Maruyama, Atsushi Koike
  • Patent number: 8815641
    Abstract: A method and structure for a semiconductor device including a thin nitride layer formed between a diamond SOI layer and device silicon layer to block diffusion of ions and improve lifetime of the device silicon.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: August 26, 2014
    Assignee: Soitec
    Inventors: Rick C. Jerome, Francois Hebert, Craig McLachlan, Kevin Hoopingarner
  • Publication number: 20140231825
    Abstract: Semiconductor devices and methods of making thereof are provided. In one aspect, for example, a method for making a semiconductor device can include polishing a working surface of a diamond layer to a substantially flat surface, depositing a buffer layer on the working surface of the diamond layer, and depositing a semiconductor layer on the buffer layer. In one specific aspect, the c-axis of the buffer layer is oriented perpendicular to the working surface of the diamond layer.
    Type: Application
    Filed: September 11, 2013
    Publication date: August 21, 2014
    Inventor: Chien-Min Sung
  • Patent number: 8809916
    Abstract: A pH sensor may include a reference electrode including a p-channel field effect transistor (FET) whose gate includes a diamond surface having a hydrogen ion insensitive terminal, and a working electrode.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: August 19, 2014
    Assignee: Yokogawa Electric Corporation
    Inventors: Yukihiro Shintani, Kazuma Takenaka
  • Patent number: 8796071
    Abstract: The present invention related to a method for manufacturing a thermal dissipation substrate and a thermal dissipation substrate. The method includes steps of: (a) providing a substrate body having a surface; (b) forming a plurality of concave regions on the surface; and (c) filling the plurality of concave regions with a plurality of diamond materials. The thermal dissipation substrate includes: a substrate having a surface at a first horizontal; a plurality of regions formed on the surface at a second horizontal; and a plurality of diamond materials having a relatively high thermal coefficient and disposed on the plurality of regions.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: August 5, 2014
    Assignee: National Chiao Tung University
    Inventors: YewChung Sermon Wu, Tai-Min Chang, Yu Chia Chiu, Jen-Li Hu
  • Patent number: 8765523
    Abstract: A method for manufacturing a semiconductor device includes the steps of preparing a substrate made of silicon carbide and having an n type region formed to include a main surface, forming a p type region in a region including the main surface, forming an oxide film on the main surface across the n type region and the p type region, by heating the substrate having the p type region formed therein at a temperature of 1250° C. or more, removing the oxide film to expose at least a part of the main surface, and forming a Schottky electrode in contact with the main surface that has been exposed by removing the oxide film.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: July 1, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda
  • Patent number: 8765524
    Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: July 1, 2014
    Assignee: General Electric Company
    Inventors: Avinash Srikrishnan Kashyap, David Mulford Shaddock, Emad Andarawis Andarawis, Peter Micah Sandvik, Stephen Daley Arthur, Vinayak Tilak
  • Patent number: 8753911
    Abstract: LED devices incorporating diamond materials and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: June 17, 2014
    Assignee: RiteDia Corporation
    Inventor: Chien-Min Sung
  • Publication number: 20140159055
    Abstract: A method of manufacturing a composite substrate for a semiconductor device, the method comprising: depositing silicon on a surface of a synthetic diamond wafer; and treating the synthetic diamond wafer to transform the deposited silicon into silicon carbide thus forming a layer of silicon carbide on the surface of the synthetic diamond wafer, wherein the synthetic diamond wafer is selected from one of: a single crystal diamond wafer; and a polycrystalline CVD diamond wafer having a nucleation face and a growth face wherein the nucleation face comprises smaller diamond grains than the growth face, and wherein if the synthetic diamond wafer is a polycrystalline CVD diamond wafer then the silicon carbide layer is formed on the growth face of the polycrystalline CVD diamond wafer.
    Type: Application
    Filed: December 5, 2013
    Publication date: June 12, 2014
    Inventors: Richard Stuart Balmer, Timothy Peter Mollart, Christopher John Howard Wort
  • Patent number: 8735907
    Abstract: In a semiconductor diamond device, there is provided an ohmic electrode that is chemically and thermally stable and has an excellent low contact resistance and high heat resistance. A nickel-chromium alloy, or a nickel-chromium compound, containing Ni and Cr such as Ni6Cr2 or Ni72Cr18Si10, which is chemically and thermally stable, is formed on a semiconductor diamond by a sputtering process and so forth, to thereby obtain the semiconductor diamond device provided with an excellent ohmic electrode. If heat treatment is applied after forming the nickel-chromium alloy or compound, it is improved in characteristics.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: May 27, 2014
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Takatoshi Yamada, Somu Kumaragurubaran, Shinichi Shikata
  • Patent number: 8637360
    Abstract: Exemplary embodiments provide structures and methods for power devices with integrated clamp structures. The integration of clamp structures can protect the power device, e.g., from electrical overstress (EOS). In one embodiment, active devices can be formed over a substrate, while a clamp structure can be integrated outside the active regions of the power device, for example, under the active regions and/or inside the substrate. Integrating clamp structure outside active regions of power devices can maximize the active area for a given die size and improve robustness of the clamped device since the current will spread in the substrate by this integration.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: January 28, 2014
    Assignee: Intersil Americas Inc.
    Inventor: Francois Hebert
  • Patent number: 8624263
    Abstract: The present invention is contemplated for providing a diamond semiconductor device where an impurity-doped diamond semiconductor is buried in a selected area, and a method of manufacturing the same. That is, a diamond semiconductor device having an impurity-doped diamond area selectively buried in a recessed portion formed in a diamond substrate; and a method of manufacturing a diamond semiconductor device, including the steps of selectively forming an recessed portion on the {100}-facet diamond semiconductor substrate, wherein the bottom face of the recessed portion is surrounded by the {100} facet and the side face of the recessed portion is surrounded by the {110} facet, and forming an impurity-doped diamond area by epitaxially growing diamond in the <111> direction while doping with impurities and burying the recessed portion.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: January 7, 2014
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Hiromitsu Kato, Toshiharu Makino, Masahiko Ogura, Hideyo Okushi, Satoshi Yamasaki
  • Publication number: 20130344651
    Abstract: A discharge surface treatment apparatus supplies an electrode material to a surface of a treatment target member by generating pulsating discharges across an inter-electrode gap to form a coating of the electrode material, and includes a switching element that turns application of a voltage from a power source to the inter-electrode gap on/off, a capacitance element that is connected to the switching element in parallel with the inter-electrode gap, an inductance element that is connected in series between both of the switching element and the capacitance element and the inter-electrode gap, and a control unit that includes a function of periodically performing on/off so that an induced electromotive force generated in the inductance element due to a change in the current of discharge generated across the inter-electrode gap can be used as a voltage that induces the next discharge
    Type: Application
    Filed: June 26, 2012
    Publication date: December 26, 2013
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yoshikazu Nakano, Akihiro Goto
  • Patent number: 8609461
    Abstract: Various embodiments provide methods for forming a diamond heat spreader and integrating the diamond heat spreader with a heat source without generating voids at the interface. In one embodiment, a semiconductor layer can be epitaxially formed on a diamond substrate having a desirably low surface root mean square (RMS) roughness. The semiconductor epi-layer can be used as an interface layer for bonding the diamond substrate to the heat source to provide efficient heat spreading.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: December 17, 2013
    Assignee: STC.UNM
    Inventors: Ganesh Balakrishnan, Jerome V. Moloney, Victor Hasson
  • Patent number: 8598593
    Abstract: A chip includes an integrated circuit and a carbonic layer. The carbonic layer includes a graphite-like carbon, wherein a lateral conducting path through the graphite-like carbon electrically connects two circuit elements of the integrated circuit.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: December 3, 2013
    Assignee: Infineon Technologies AG
    Inventor: Uwe Hoeckele