Abstract: By widening a terrace on a crystal surface on a bottom face of a recess by step flow caused by heating, a flat face is formed on the bottom face of the recess, a two-dimensional material layer made of a two-dimensional material is formed on the formed flat face, and then a device made of the two-dimensional material layer is produced.

Abstract: An integrated circuit includes a resistive material layer formed on a substrate, a metal layer formed on the resistive material layer, a bipolar transistor formed on the substrate, and a resistive element formed on the substrate. The bipolar transistor includes, as a sub-layer, the metal layer formed in a first region, and also includes a collector layer formed on the sub-collector layer. The resistive element is constituted by the resistive material layer formed in a second region.

Abstract: A surgical system including a combination instrument for breaking of tabs of a reduction connector and providing a counter torque for a driver is disclosed. The combination instrument may have an elongated rigid structure and include an internal shaft and a magazine portion configured to store at least one tab of a reduction connector. The combination instrument may further include a cut-out portion configured to retain the at least one tab within the magazine portion. In some embodiments, the driver may be configured to be inserted into the internal shaft of the combination instrument. In some embodiments, the driver is rotatable within the internal shaft of the combination instrument and configured to drive a set screw within the reduction connector. Disclosed drivers may be manual drivers or powered drivers. Some embodiments, may include a collar or a cap from which the broken off tabs may be ejected.

Abstract: A voltage tunable solar-blind UV detector using a EG/SiC heterojunction based Schottky emitter bipolar phototransistor with EG grown on p-SiC epi-layer using a chemically accelerated selective etching process of Si using TFS precursor.

Abstract: The following relates generally to a magnetic imaging sensor configured to capture vector magnetometry data. One disclosed aspect involves: using a green pumping laser to excite nitrogen vacancy (NV) centers of a diamond crystal; and, through a filter stacked between the diamond crystal and a pixilated image sensor, passing red light caused by the excitation to the pixilated image sensor.

Abstract: Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K, and Wherein the n-type donor atoms are introduced to the lattice through ion tracks.

Abstract: A system is provided. The system includes a 3D printer, which includes a first dispenser and a second dispenser. The first dispenser is configured to apply conductive material to a surface, and the second dispenser is configured to apply conductive diamonds to a surface. The conductive material includes a mixture of an elastomer and at least one of nickel and silver, and the conductive diamonds are between 1 and 10 microns in size.

Abstract: In a first aspect, the present disclosure relates to a method for forming a diamond membrane, comprising: providing a substrate having an amorphous dielectric layer thereon, the amorphous dielectric layer comprising an exposed surface, the exposed surface having an isoelectric point of less than 7, preferably at most 6; seeding diamond nanoparticles onto the exposed surface; growing a diamond layer from the seeded diamond nanoparticles; and removing a portion of the substrate from underneath the diamond layer, the removed portion extending at least up to the amorphous dielectric layer, thereby forming the diamond membrane over the removed portion.

Abstract: Disclosed is an apparatus and method for inspecting a component of a gas turbine engine, which includes a sleeve configured to surround a component of a gas turbine engine, the sleeve including: a pair of opposing wall members being secured to each other at at least one of a pair of opposite ends; an internal cavity located between the pair of opposing wall members, wherein the internal cavity extends from one end of the sleeve to an opposite end of the sleeve; and a plurality of orifices extending through the pair of opposing wall members, and wherein a probe is inserted in each orifice in one of the pair of opposing wall members to determine the state of the internal cavities of a gas turbine component and determine the structural integrity of the component.

Abstract: Methods are disclosed that selectively deposit a protective material on the top regions of patterned photoresist layers, such patterned EUV photoresist layers, to provide a protective cap that reduces erosion damage during etch processes used for pattern transfer. Some deposition of the protective material on the sidewalls of the patterned photoresist layer is acceptable, and any deposition of the protective material on the underlying layer below the patterned photoresist layer is preferably thinner than the deposition at the top of the photoresist pattern. Further, the selective deposition of protective caps can be implemented, for example, through the application of high-rotation speeds to spatial atomic layer deposition (ALD) techniques. The selective deposition of protective caps increases the flexibility of options to improve etch resistance for various processes/materials.

Abstract: The present disclosure discloses a self-aligned silicon carbide MOSFET device with an optimized P+ region and a manufacturing method thereof. The self-aligned silicon carbide MOSFET device is formed by a plurality of silicon carbide MOSFET device cells connected in parallel, and these silicon carbide MOSFET device cells are arranged evenly. The silicon carbide MOSFET device cell comprises two source electrodes, one gate electrode, one gate oxide layer, two N+ source regions, two P+ contact regions, two P wells, one N? drift layer, one buffer layer, one N+ substrate, one drain electrode and one isolation dielectric layer.

Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer on a substrate, forming a carbon nanotube (CNT) layer on the first dielectric layer, forming a second dielectric layer on the carbon nanotube (CNT) layer, patterning a plurality of trenches in the second dielectric layer exposing corresponding portions of the carbon nanotube (CNT) layer, forming a plurality of contacts respectively in the plurality of trenches on the exposed portions of the carbon nanotube (CNT) layer, performing a thermal annealing process to create end-bonds between the plurality of the contacts and the carbon nanotube (CNT) layer, and depositing a passivation layer on the plurality of the contacts and the second dielectric layer.

Abstract: A method for manufacturing a semiconductor device includes forming a dielectric layer on a substrate, forming a first carbon nanotube (CNT) layer on the dielectric layer at a first portion of the device corresponding to a first doping type, forming a second CNT layer on the dielectric layer at a second portion of the device corresponding to a second doping type, forming a plurality of first contacts on the first CNT layer, and a plurality of second contacts on the second CNT layer, performing a thermal annealing process to create end-bonds between the plurality of the first and second contacts and the first and second CNT layers, respectively, depositing a passivation layer on the plurality of the first and second contacts, and selectively removing a portion of the passivation layer from the plurality of first contacts.

Abstract: In one general aspect, an apparatus can include a silicon carbide (SiC) device can include a gate dielectric, a first doped region having a first conductivity type, a source, a body region of the first conductivity type, and a second doped region having a second conductivity type. The second doped region can have a first portion and a second portion. The first portion can be disposed between the first doped region and the body region and the second portion can be disposed between the first doped region and the gate dielectric. The first portion of the second doped region can have a width less than a width of the first doped region.

Abstract: Described herein are microfluidic devices and methods of detecting an analyte in a sample that includes flowing the sample though a microfluidic device, wherein the presence of the analyte is detected directly from the microfluidic device without the use of an external detector at an outlet of the microfluidic device. In a more specific aspect, detection is performed by incorporating functional nanopillars, such as detector nanopillars and/or light source nanopillars, into a microchannel of a microfluidic device.

Abstract: An ion detection device has a strip of carbon-based nanomaterial (CNM) film and a chamber enclosing the CNM film. A low bias voltage is applied at the ends of the CNM film strip, and ions present in the chamber are detected by a change in the magnitude of current flowing through the CNM film under the bias. Also provided are methods for fabricating the device, methods for measuring pressure of a gas, and methods for monitoring or quantifying an ionizing radiation using the device.

Abstract: A UNCD nanowire comprises a first end electrically coupled to a first contact pad which is disposed on a substrate. A second end is electrically coupled to a second contact pad also disposed on the substrate. The UNCD nanowire is doped with a dopant and disposed over the substrate. The UNCD nanowire is movable between a first configuration in which no force is exerted on the UNCD nanowire and a second configuration in which the UNCD nanowire bends about the first end and the second end in response to a force. The UNCD nanowire has a first resistance in the first configuration and a second resistance in the second configuration which is different from the first resistance. The UNCD nanowire is structured to have a gauge factor of at least about 70, for example, in the range of about 70 to about 1,800.

Abstract: A method includes forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer, forming a capping layer over the carbon-containing layer, forming a first photo resist over the capping layer, and etching the capping layer and the carbon-containing layer using the first photo resist as a first etching mask. The first photo resist is then removed. A second photo resist is formed over the capping layer. The capping layer and the carbon-containing layer are etched using the second photo resist as a a second etching mask. The second photo resist is removed. A third photo resist under the carbon-containing layer is etched using the carbon-containing layer as etching mask. A dielectric layer underlying the third photo resist is etched to form via openings using the third photo resist as etching mask. The via openings are filled with a conductive material.

Abstract: A method is provided for forming an integrated circuit. A trench is formed in a substrate. Subsequently, a silicon-germanium feature is formed in the trench, and an etch stop layer is formed on the substrate and on the silicon-germanium feature. Lastly, a silicon device layer is formed on the etch stop layer. The silicon device layer has a tensily-strained region overlying the silicon-germanium feature. Regions of the silicon device layer not overlying the silicon-germanium feature are less strained than the tensily-strained region. The tensily-strained region of the silicon device layer may be further processed into channel features in n-type field effect transistors with improved charge carrier mobilities and device drive currents.

Abstract: A method of forming a field emitter comprises disposing a first layer on a substrate. The first layer is seeded with nanodiamond particles. The substrate with the first layer disposed thereon is maintained at a first temperature and a first pressure in a mixture of gases which includes nitrogen. The first layer is exposed to a microwave plasma to form a nitrogen doped ultrananocrystalline diamond film on the first layer, which has a percentage of nitrogen in the range of about 0.05 atom % to about 0.5 atom %. The field emitter has about 1012 to about 1014 emitting sites per cm2. A photocathode can also be formed similarly by forming a nitrogen doped ultrananocrystalline diamond film on a substrate similar to the field emitter, and then hydrogen terminating the film. The photocathode is responsive to near ultraviolet light as well as to visible light.

Abstract: A flexible display apparatus includes a flexible substrate, a display layer disposed on one surface of the flexible substrate and including a plurality of pixels, graphene disposed on a surface opposing the one surface of the flexible substrate, and an encapsulation layer covering the display layer.

Abstract: A silicon carbide semiconductor device of the present invention comprises a silicon carbide drift layer formed on a silicon carbide substrate, a P-type region formed in a surface layer of the silicon carbide drift layer, and a Schottky electrode formed above the silicon carbide drift layer correspondingly to a forming portion of the P-type region. The P-type region is formed of a plurality of unit cells arranged therein. Each of the unit cells has at least a first distribution region in which the P-type impurity is distributed at first concentration and a second distribution region in which the P-type impurity is distributed at second concentration higher than the first concentration. With this structure, it is possible to provide a silicon carbide semiconductor device in which a sufficient breakdown voltage can be achieved with less number of ion implantations.

Abstract: A method of laser ablation for electrical contact to a buried electrically conducting layer in diamond comprising polishing a single crystal diamond substrate having a first carbon surface, implanting the diamond with a beam of 180 KeV followed by 150 KeV C+ ions at fluencies of 4×1015 ions/cm2 and 5×1015 ions/cm2 respectively, forming an electrically conducting carbon layer beneath the first carbon surface, and ablating the single crystal diamond which lies between the electrically conducting layer and the first carbon surface.

Abstract: A silicon carbide power device equipped with termination structure comprises a silicon carbide substrate, a power element structure and a termination structure. The silicon carbide substrate contains a drift layer which has a first conductivity and includes an active zone and a termination zone. The power element structure is located in the active zone. The termination structure is located in the termination zone and has a second conductivity, and includes at least one first doped ring abutting and surrounding the power element structure and at least one second doped ring surrounding the first doped ring. The first doped ring has a first doping concentration smaller than that of the second doped ring and a first doping depth greater than that of the second doped ring, thereby can increase the breakdown voltage of the silicon carbide power device.

Abstract: Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The system may include a diamond material having n-type donor atoms and a diamond lattice, wherein 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K. The method of fabricating diamond semiconductors may include the steps of selecting a diamond material having a diamond lattice; introducing a minimal amount of acceptor dopant atoms to the diamond lattice to create ion tracks; introducing substitutional dopant atoms to the diamond lattice through the ion tracks; and annealing the diamond lattice.

Abstract: An electrical device includes a blocking layer disposed on top of a substrate layer, wherein the blocking layer and the substrate layer each are wide bandgap semiconductors, and the blocking layer and the substrate layer form a buried junction in the electrical device. The device comprises a termination feature disposed at a surface of the blocking layer and a filled trench disposed proximate to the termination feature. The filled trench extends through the blocking layer to reach the substrate layer and is configured to direct an electrical potential associated with the buried junction toward the termination feature disposed near the surface of the blocking layer to terminate the buried junction.

Abstract: Provided are a technology that simply forms a particular crystal surface such as a {03-38} surface having high carrier mobility in trench sidewalls and a SiC semiconductor element where most of the trench sidewalls appropriate for a channel member are formed from {03-38} surfaces. A trench structure formed in a (0001) surface or an off-oriented surface of a (0001) surface with an offset angle 8° or lower of SiC is provided. The channel member is in the trench structure. At least 90% of the area of the channel member is a {03-38} surface or a surface that a {03-38} surface offset by an angle from ?8° to 8° in the <1-100> direction. Specifically, the trench sidewalls are finished to {03-38} surfaces by applying a thermal etching to a trench with (0001) surfaces of SiC. Thermal etching is conducted in a chlorine atmosphere above 800° C. with nitrogen gas as the carrier.

Abstract: Method for synthesizing a material by chemical vapor deposition (CVD), according to which a plasma is created in a vacuum chamber in the vicinity of a substrate, and according to which a carbon-carrying substance and H2 are introduced into the chamber in order to produce in the chamber a gas comprising substances carrying reactive-carbon atoms in the form of unsaturated molecules or radicals from which the synthesis of said material will be performed, and in that the electromagnetic absorption and inelastic diffusion spectra of the solid material to be synthesized are used to take from these spectra the absorption frequencies that contribute to the reactions that lead to the formation of the solid material to be synthesized, and in that energetic rays are produced in the form of a photon beam carrying quantities of energy determined by each of the frequencies corresponding to said absorption and inelastic diffusion frequencies, said photon beam being injected into the plasma where, for energy states of the so

Abstract: Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate.

Abstract: A semiconductor device according to an embodiment includes an i-type or a p-type first diamond semiconductor layer, an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer, a mesa structure and an n-type first diamond semiconductor region provided on the side surface. The mesa structure includes the first diamond semiconductor layer, the second diamond semiconductor layer, a top surface with a plane orientation of ±10 degrees or less from a {100} plane, and a side surface inclined by 20 to 90 degrees with respect to a direction of <011>±20 degrees from the {100} plane. The first diamond semiconductor region is in contact with the second diamond semiconductor layer and has an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer.

Abstract: A method for treating a surface of a diamond thin film according to one aspect of the present invention performs one of a first substitution process for substituting part of hydrogen-terminals of a diamond thin film with fluorine-terminals in the absence of a fluorocarbon deposition on the surface of diamond thin film and a second substitution process for substituting part of hydrogen-terminals of a diamond thin film with fluorine-terminals in the presence of the fluorocarbon deposition on the surface of diamond thin film based on required surface properties of the diamond thin film.

Abstract: The invention relates to a method for producing a component comprising a conductive grid insulated from a semiconductor monocrystalline diamond substrate by an insulating region, comprising the following steps: a) oxygenating the surface of the substrate so as to replace the hydrogen surface terminations of the substrate with oxygen surface terminations; and b) forming the insulating region on the surface of the substrate by repeated monatomic layer deposition.

Abstract: A semiconductor device including a graphene layer and a method of manufacturing the same are disclosed. A method in which graphene is grown on a catalyst metal by a chemical vapor deposition or the like is known. However, the graphene cannot be used as a channel, since the graphene is in contact with the catalyst metal, which is conductive. There is disclosed a method in which a catalyst film (2) is formed over a substrate (1), a graphene layer (3) is grown originating from the catalyst film (2), an electrode (4) in contact with the graphene layer (3) is formed, and the catalyst film (2) is removed.

Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.

Abstract: A semiconductor device according to the present embodiment includes a diamond substrate having a surface plane inclined from a (100) plane in a range of 10 degrees to 40 degrees in a direction of <011>±10 degrees, and an n-type diamond semiconductor layer containing phosphorus (P) and formed above the surface plane described above.

Abstract: The present invention provides a conducting material comprising a carbon-based material selected from a diamond or an insulating diamond-like carbon, having a hydrogen-terminated surface and a layer of MoO3 coating said surface; as well as a method for the fabrication of such a material. The conducting material of the invention is useful in the fabrication of electronic components, electrodes, sensors, diodes, field effect transistors, and field emission electron sources.

Abstract: A method of manufacturing a silicon carbide structure includes forming a silicon carbide layer by depositing silicon carbide on a base plate by chemical vapor deposition, removing the base plate, decreasing electrical conductivity by heat-treating the silicon carbide structure, and removing a thickness of 200 ?m from an upper surface and a lower surface of the silicon carbide structure. In the present invention, silicon carbide is deposited by a CVD method, and the electrical conductivity of the silicon carbide is reduced to the electrical conductivity required for a protection ring of a plasma device through a post-treatment and a post-process. The electrical conductivity may be adjusted even without using separate additives.

Abstract: A semiconductor device may include a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a source electrode and a drain electrode in contact with the first semiconductor layer or the second semiconductor layer, an opening formed in the second semiconductor layer, an insulating film formed on an inner surface of the opening formed in the second semiconductor layer and above the second semiconductor layer, a gate electrode formed in the opening via the insulating film, and a protective film formed on the insulating film and including an amorphous film containing carbon as a major component.

Abstract: A method of fabricating an interconnect element may include fabricating a metal layer that overlies a carrier layer and that includes a plurality of metal traces; providing a dielectric element to overlie the metal layer and the carrier layer; providing a plurality of metal posts; and removing the carrier layer to expose the first major surface of the dielectric element and the outer surfaces of the plurality of metal traces.

Abstract: A method including forming a diamond material on the surface of a substrate; forming a first contact and a separate second contact; and patterning the diamond material to form a nanowire between the first contact and the second contact. An apparatus including a first contact and a separate second contact on a substrate; and a nanowire including a single crystalline or polycrystalline diamond material on the substrate and connected to each of the first contact and the second contact.

Abstract: A semiconductor layer 102 having a drift region 132, a body region 103, and a source region 104 provided at a position next to the body region 103; an epitaxial layer 106 in contact with the body region; and a gate insulating film 107 provided on the epitaxial layer are formed on a principal surface of a semiconductor substrate 101. The epitaxial layer includes an interface epitaxial layer 106i in contact with the body region, a first epitaxial layer 106a on the interface epitaxial layer 106i, and a second epitaxial layer 106b on the first epitaxial layer 106a. An impurity concentration of the interface epitaxial layer is higher than an impurity concentration of the first epitaxial layer, and lower than an impurity concentration of the second epitaxial layer.

Abstract: An organic material with a porous interpenetrating network and an amount of inorganic material at least partially distributed within the porosity of the organic material is disclosed. A method of producing the organic-inorganic thin films and devices therefrom comprises seeding with nanoparticles and depositing an amorphous material on the nanoparticles.

Abstract: A method is provided for fabricating a wafer of semiconductor material intended for use for the integration of electronic and/or optical and/or optoelectronic devices. The method comprises: providing a starting wafer of crystalline silicon (205); on the starting wafer of crystalline silicon, epitaxially growing a buffer layer (210) consisting of a sub-stoichiometric alloy of silicon and germanium; epitaxially growing on the buffer layer a layer (225) of a semiconductor material having an energy gap greater than that of the crystalline silicon constituting the starting wafer, wherein the layer of semiconductor material having an energy gap greater than that of the crystalline silicon is grown so to have a thickness capable of constituting a substrate for the integration therein of electronic and/or optical and/or optoelectronic devices.

Abstract: Methods in accordance with this invention form a microelectronic structure by forming a carbon nano-tube (“CNT”) layer, and forming a boron nitride layer (“BN liner”) above the CNT layer, wherein the BN liner comprises: (1) a first portion disposed above and in contact with the CNT layer; and/or (2) a second portion disposed in and/or around one or more carbon nano-tubes in the CNT layer. Numerous other aspects are provided.

Abstract: A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.

Abstract: The present invention provides a polishing slurry capable of polishing even high-hardness materials such as silicon carbide and gallium nitride at a high polishing speed. The present invention is a polishing slurry including a slurry containing a manganese oxide particle and a manganate ion for polishing high-hardness materials having a Mohs hardness of 8 or higher. In the present invention, the manganese oxide particle in the slurry is preferably 1.0 mass % or more; the manganese oxide is preferably manganese dioxide; and the manganate ion is preferably permanganate ion. The polishing slurry according to the present invention enables even high-hardness hardly-machinable materials such as silicon carbide and gallium nitride to be polished smoothly at a high speed.

Abstract: A method and structure for a semiconductor device including a thin nitride layer formed between a diamond SOI layer and device silicon layer to block diffusion of ions and improve lifetime of the device silicon.

Abstract: Semiconductor devices and methods of making thereof are provided. In one aspect, for example, a method for making a semiconductor device can include polishing a working surface of a diamond layer to a substantially flat surface, depositing a buffer layer on the working surface of the diamond layer, and depositing a semiconductor layer on the buffer layer. In one specific aspect, the c-axis of the buffer layer is oriented perpendicular to the working surface of the diamond layer.

Abstract: A pH sensor may include a reference electrode including a p-channel field effect transistor (FET) whose gate includes a diamond surface having a hydrogen ion insensitive terminal, and a working electrode.

Abstract: The present invention related to a method for manufacturing a thermal dissipation substrate and a thermal dissipation substrate. The method includes steps of: (a) providing a substrate body having a surface; (b) forming a plurality of concave regions on the surface; and (c) filling the plurality of concave regions with a plurality of diamond materials. The thermal dissipation substrate includes: a substrate having a surface at a first horizontal; a plurality of regions formed on the surface at a second horizontal; and a plurality of diamond materials having a relatively high thermal coefficient and disposed on the plurality of regions.