Abstract: A wafer fabrication outcome, such as wafer yield or wafer lifetime, is predicted by excluding uncontrollable but measurable internal/external noises of a DOE system, and by rendering relations between wafer design variables and wafer outcome outputs to be more causal, as well as the relations between variances for each of the wafer design variables and the wafer outcome outputs. With the aid of a wafer fabrication outcome predicting model formed by the more causal relations, precision of predicting wafer outcomes can be raised, and performance of wafer fabrication can be thus raised as a result.

Abstract: A method for treating a semiconductor wafer having a basic doping is disclosed. The method includes determining a doping concentration of the basic doping, and adapting the basic doping of the semiconductor wafer by postdoping. The postdoping includes at least one of the following methods: a proton implantation and a subsequent thermal process for producing hydrogen induced donors, and a neutron irradiation. In this case, at least one of the following parameters is dependent on the determined doping concentration of the basic doping: an implantation dose of the proton implantation, a temperature of the thermal process, and an irradiation dose of the neutron irradiation.

Abstract: Disclosed are a lead frame and a method for manufacturing the same. The lead frame includes a copper substrate and a rough copper layer having surface roughness of 110 nm to 300 nm on a surface of the copper substrate.

Abstract: The invention is directed to apparatus and chips comprising a large scale chemical field effect transistor arrays that include an array of sample-retaining regions capable of retaining a chemical or biological sample from a sample fluid for analysis. In one aspect such transistor arrays have a pitch of 10 ?m or less and each sample-retaining region is positioned on at least one chemical field effect transistor which is configured to generate at least one output signal related to a characteristic of a chemical or biological sample in such sample-retaining region.

Abstract: A method of forming a semiconductor device includes forming a first transistor and a second transistor on a substrate, monitoring processes of forming the first and second transistors to find an error and performing an additional ion implantation process to form a low-concentration dopant region or a halo region on the first transistor or the second transistor corresponding to a found error.

Abstract: Semiconductor devices are described that are configured to have a state of operation defined by a connection between at least one inner bump assembly and a selected outer bump assembly. In an implementation, the semiconductor device, which may be a wafer-level (chip-scale) package semiconductor device, includes an integrated circuit chip, a plurality of outer bump assemblies disposed on the chip, and one or more inner bump assemblies disposed on the chip so that the inner bump assemblies are at least partially surrounded by the outer bump assemblies. At least one of the inner bump assemblies is configured to be connected to a selected outer bump assembly to cause the integrated circuit chip to have a desired state of operation.

Abstract: A display device includes a substrate, gate lines extended in a first direction on the substrate, data lines extended in a second direction substantially perpendicular to the first direction on the substrate, and pixels connected to the gate and data lines. Each pixel includes a transistor having one end connected to a data line, and a gate electrode connected to a corresponding gate line, a liquid crystal layer disposed in a tunnel-shaped cavity, first and second electrodes for applying an electric field to the liquid crystal layer. The first electrode of each pixel is connected to another end of the transistor, a second electrode of each pixel overlaps the first electrode of one of its adjacent pixels, and the first electrode of each pixel overlaps a second electrode of another one of its adjacent pixels.

Abstract: A method and apparatus for compensating a bias voltage at the wafer by measuring RF voltage signals in RF driven plasma including at least an electrostatic, chuck (ESC), a capacitive divider, a signal processing and signal conditioning network is disclosed. The bias compensation device includes a capacitive divider to detect the RF voltage at the ESC, a signal conditioning network for the purpose of filtering specific RF signals of interests, and a signal processing unit for computing the DC wafer potential from the filtered RF signals.

Abstract: A first embodiment relates to a semiconductor component. The semiconductor component has a semiconductor body with a bottom side and a top side spaced distant from the bottom side in a vertical direction. In the vertical direction, the semiconductor body has a certain thickness. The semiconductor component further has a crack sensor configured to detect a crack in the semiconductor body. The crack sensor extends into the semiconductor body. A distance between the crack sensor and the bottom side is less than the thickness of the semiconductor body.

Abstract: The resistivity of a silicon boule may vary along its length, thereby making a uniform ion implantation process sub-optimal. A system and method for measuring a resistivity of a substrate, and processing the substrate based on that measured resistivity is disclosed. The system includes a resistivity measurement system, a controller and an ion implanting system, where the controller configures the ion implantation process based on the measured resistivity of the substrate.

Abstract: A structure is provided in which the back gate regions are physically separated from one another as opposed to using reversed biased pn junction diodes. In the present disclosure, the back gate regions can be formed first through a buried dielectric material of an extremely thin semiconductor-on-insulator (ETSOI) substrate. After dopant activation, standard device fabrication processes can be performed. A semiconductor base layer portion of the ETSOI substrate can then be removed from the original ETSOI to expose a surface of the back gates.

Abstract: After a substrate implanted with impurities is heated to a preheating temperature, the front surface of the substrate is heated to a target temperature by irradiating the front surface of the substrate with a flash of light. Further, the flash irradiation is continued to maintain the temperature of the front surface near the target temperature for a predetermined time period. At this time, a flash irradiation time period in the flash heating step is made longer than a heat conduction time period required for heat conduction from the front surface of the substrate to the back surface thereof, and a difference in temperature between the front and back surfaces of the substrate is controlled to be always not more than one-half of an increased temperature from the preheating temperature to the target temperature during the flash irradiation.

Abstract: A method of testing an array-based semiconductor device for defects during fabrication of the semiconductor device detects defects in said entities forming the semiconductor device at an intermediate stage in the fabrication of multiple types of entities forming the semiconductor device; determines whether the detected defects exceed preselected thresholds for the types of entities in which said detects are detected; if the detected defects do not exceed said preselected thresholds, continues the fabrication of the semiconductor device; and if the detected defects exceed said preselected thresholds, identifies the types of defects detected, repairs the identified defects, and continues the fabrication of the semiconductor device.

Abstract: A method for separating a multiple number of semiconductor devices or semiconductor integrated circuits from a wafer on which the multiple number of semiconductor devices or semiconductor integrated circuits are formed is provided. The method includes: forming, on a surface of the wafer, a mask layer through which a line-shaped pattern to be removed for separating the semiconductor devices or semiconductor integrated circuits is exposed; and etching the exposed pattern to a depth equal to or larger than about ? of a thickness of the wafer. The line-shaped pattern is formed so as to prevent a test device formed on a gap between the semiconductor devices or semiconductor integrated circuits from remaining on separated semiconductor devices or semiconductor integrated circuits.

Abstract: Techniques for quantifying ?Dfin in FINFET technology are provided. In one aspect, a method for quantifying ?Dfin between a pair of long channel FINFET devices includes the steps of: (a) obtaining Vth values for each of the long channel FINFET devices in the pair; (b) determining a ?Vth for the pair of long channel FINFET devices; and (c) using the ?Vth to determine the ?Dfin between the pair of long channel FINFET devices, wherein the ?Vth is a function of a difference in a Qbody and a gate capacitance between the pair of long channel FINFET devices, and wherein the Qbody is a function of Dfin and Nch for each of the long channel FINFET devices in the pair, and as such the ?Vth is proportional to the ?Dfin between the pair of long channel FINFET devices.

Abstract: Methods for sensing a mechanical stress and methods of making stress sensor integrated circuits. The sensing methods include transferring the mechanical stress from the object to one or more nanowires in a stress sensor or stress sensor circuit and permitting the nanowires to change in length in response to the mechanical stress. An electrical characteristic of the stress sensor or stress sensor circuit, which has a variation correlated with changes in the magnitude of the mechanical stress, is measured and then assessed to determine the stress magnitude. The manufacture methods include electrically connecting nanowire field effect transistors having, as channel regions, one or more nanowires of either a different crystalline orientation or a different body width for the individual nanowires so that an offset output voltage results when mechanical strain is applied to the nanowires.

Abstract: A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.

Abstract: A method for producing a light emitting diode device includes the steps of preparing a board mounted with a light emitting diode; preparing a hemispherical lens molding die; preparing a light emitting diode encapsulating material which includes a light emitting diode encapsulating layer and a phosphor layer laminated thereon, and in which both layers are prepared from a resin before final curing; and disposing the light emitting diode encapsulating material between the board and the lens molding die so that the phosphor layer is opposed to the lens molding die to be compressively molded, so that the light emitting diode is directly encapsulated by the hemispherical light emitting diode encapsulating layer and the phosphor layer is disposed on the hemispherical surface thereof.

Abstract: A sensor manufacturing method and a microphone structure produced by using the same. Wherein, thermal oxidation method is used to form a sacrifice layer of an insulation layer on a silicon-on-insulator (SOI) substrate or a silicon substrate, to fill patterned via in said substrate. Next, form a conduction wiring layer on the insulation layer. Since the conduction wiring layer is provided with holes, thus etching gas can be led in through said hole, to remove filling in the patterned via, to obtain an MEMS sensor. Or after etching of the conduction wiring layer, deep reactive-ion etching is used to etch the silicon substrate into patterned via, to connect the substrate electrically to a circuit chip. The manufacturing process is simple and the technology is stable and mature, thus the conduction wiring layer and the insulation layer are used to realize electrical isolation.

Abstract: A semiconductor device includes: a semiconductor substrate including an active element formation face on which an active element is formed; detection electrodes detecting a remaining amount of ink by being wet in the ink; an antenna transmitting and receiving information; a storage circuit storing information relating to the ink; and a control circuit controlling the detection electrodes, the antenna, and the storage circuit.

Abstract: An ion implantation apparatus according to an embodiment includes an ion implantation unit, a position detection unit, a charge supply unit, a current value detection unit, and a determination unit. The ion implantation unit scans the surface of a substrate with an ion beam containing positively charged ions and implants the ions into the substrate. The position detection unit detects the scan position of the ion beam on the substrate. The charge supply unit generates a plasma, emits electrons contained in the plasma, and supplies the electrons to the substrate. The current value detection unit detects a current value that changes in accordance with the amount of electrons emitted by the charge supply unit. The determination unit determines the charge build-up state of the substrate based on a change in the current value, the change being accompanied by a change in the scan position.

Abstract: A system and method for improving the prompt dose radiation response of mixed-signal integrated circuits is disclosed. An internal analog circuit inside a mixed-signal integrated circuit generates an internal analog reference voltage that has been used for various purposes in the integrated circuit. At least one external capacitor is added either internal or external to a device package of the integrated circuit. The external capacitor reduces any change in the internal reference voltage due to prompt dose radiation by stabilizing the internal reference voltage and thus improves prompt dose radiation response of mixed-signal integrated circuits. A much greater value of capacitance may be provided without increase in dielectric rupture suceptability or decrease in manufacturing yield which may be associated with added on-chip capacitance. This increased capacitance primarily reduce the amount of disturbance caused to the internal node during a prompt dose radiation event.

Abstract: Apparatuses and methods of forming a memory cell is described. In one such method, a forming charge applied to a memory cell, such as a Resistive RAM (RRAM) memory cell, is monitored to determine the progress of the forming the cell. If the cell is consuming charge too slowly, a higher voltage can be applied. If the cell is consuming charge too quickly, a lower voltage can be applied. The charge may be monitored by charging a capacitor to a certain level, then monitoring the discharge rate of the capacitor though the cell. The monitoring may use comparators to measure the charge. The monitoring may also use an analog to digital converter to perform the monitoring.

Abstract: A method for controlling an electrical property of a passive device during a fabrication of an integrated component includes providing a substrate, manufacturing the passive device on the substrate, measuring the electrical property of the passive device to obtain a measuring result, determining at least one layout pattern corresponding to at least one later manufacturing process by the measuring result for adjusting the electrical property of the passive device, and continuing the rest of the fabrication including the at least one later manufacturing process of the integrated component.

Abstract: A method for designing a power distribution network of a circuit system includes the following steps: determining positions of a plurality of power source nodes; estimating a current distribution condition of the circuit system; and creating a first part of the power distribution network according to at least the positions of the power source nodes.

Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Abstract: Methods and apparatus relating to FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.

Abstract: A focus through a projection lens is corrected to prevent the occurrence of a dimensional error in a pattern due to defocusing. At least one automatic focus correction mark is formed over each of chip patterns formed in a reticle used for exposure. Using one of the automatic focus correction marks located in the center portion of an actual device region, automatic correction of the focus of exposure light is performed. In this manner, a variation in the focus of the exposure light through the center portion of the projection lens, which is more likely to reach a high temperature than an end portion of the projection lens, is detected and corrected.

Abstract: Methods and apparatus relating to FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a pillar on a base layer, forming a insulating layer on the base layer to cover the pillar by using GCIB method, where a lowermost portion of an upper surface of the insulating layer is lower than an upper surface of the pillar, and polishing the insulating layer and the pillar to expose a head of the pillar by using CMP method, where an end point of the polishing is the lowermost portion of the upper surface of the insulating layer.

Abstract: Methods and apparatus relating to FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.

Abstract: A two-transistor (2T) pixel comprises a chemically-sensitive transistor (ChemFET) and a selection device which is a non-chemically sensitive transistor. A plurality of the 2T pixels may form an array, having a number of rows and a number of columns. The ChemFET can be configured in a source follower or common source readout mode. Both the ChemFET and the non-chemically sensitive transistor can be NMOS or PMOS device.

Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Abstract: Improvement of key electrical specifications of vertical semiconductor devices, usually found in the class of devices known as discrete semiconductors, has a direct impact on the performance achievement and power efficiency of the systems in which these devices are used. Imprecise vertical device specifications cause system builders to either screen incoming devices for their required specification targets or to design their system with lower performance or lower efficiency than desired. Disclosed is an architecture and method for achieving a desired target specification for a vertical semiconductor device. Precise trimming of threshold voltage improves targeting of both on-resistance and switching time. Precise trimming of gate resistance also improves targeting of switching time. Precise trimming of a device's effective width improves targeting of both on-resistance and current-carrying capability.

Abstract: Methods and apparatus relating to FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.

Abstract: A semiconductor device includes an isolation layer formed on a semiconductor substrate; an active region defined by the isolation layer; at least one gate line formed to overlap with the active region; at least one first active tab formed on a first interface of the active region which overlaps with the gate line; and a first gate tab formed on a second interface facing away from the first interface in such a way as to project from the gate line.

Abstract: Systems and methods for performing semiconductor laser annealing using dual loop control are disclosed. The first control loop operates at a first frequency and controls the output of the laser and controls the 1/f laser noise. The second control loop also controls the amount of output power in the laser and operates at second frequency lower than the first frequency. The second control loop measures the thermal emission of the wafer over an area the size of one or more die so that within-die emissivity variations are average out when determining the measured annealing temperature. The measured annealing temperature and an annealing temperature set point are used to generate the control signal for the second control loop.

Abstract: An automatic analyzer detects voltage applied across electrodes, and judges whether voltage value falls within set voltage range. When the detected voltage value is lower than minimum value of set voltage range, the analyzer calculates the deficient amount of base solution based on the detected voltage value, controls a valve to supply the deficient amount of base solution, then, performs operation control of the valve so as to keep the prescribed amount of plating solution in plating solution tank, and discharges plating solution. When the detected voltage value is higher than maximum value of set voltage range, the analyzer calculates the excess amount of base solution based on the detected voltage value, controls a valve, and supplies pure water into the tank so that the base solution concentration falls within prescribed range to dilute plating solution, then controls a valve, and discharges plating solution so as to keep prescribed amount.

Abstract: A method for calibrating a high frequency measuring device so as to accurately measure plasma processing parameters within a chamber. A calibration parameter is calculated from a first set of three reference loads measured by a high frequency measurement device. A second calibration parameter is calculated from S parameters measured between a connection point where the high-frequency measuring device is connected and the inside of the chamber of a plasma processing device. A second set of three reference loads, which include the impedance previously calculated and encompass a range narrower than that encompassed by the first set of three reference loads, is measured with the reference loads in the chamber.

Abstract: Methods are provided for fine tuning substrate resistivity. The method includes measuring a resistivity of a substrate after an annealing process, and fine tuning a subsequent annealing process to achieve a target resistivity of the substrate. The fine tuning is based on the measured resistivity.

Abstract: [Problems] There are provided a chip separation method and a chip transfer method using features of dry etching. [Means for Solving the Problems] In the chip separation method, a multiple number of semiconductor devices or semiconductor integrated circuits are separated from a wafer 100 on which the multiple number of semiconductor devices or semiconductor integrated circuits are formed. The method includes forming, on a surface of the wafer 100, a mask layer through which a line-shaped pattern to be removed for separating the semiconductor devices or semiconductor integrated circuits is exposed; and etching the exposed pattern to a depth equal to or larger than about ? of a thickness of the wafer. One group of separated semiconductor devices or semiconductor integrated circuits has a distinguishable shape from another group of separated semiconductor devices or semiconductor integrated circuits.

Abstract: A method for controlling an electrical property of a passive device during a fabrication of an integrated component includes providing a substrate, manufacturing the passive device on the substrate, measuring the electrical property of the passive device to obtain a measuring result, determining at least one layout pattern corresponding to at least one later manufacturing process by the measuring result for adjusting the electrical property of the passive device, and continuing the rest of the fabrication including the at least one later manufacturing process of the integrated component.

Abstract: A method forms an electrical connection between a first metal layer and a second metal layer. The second metal layer is above the first metal layer. A first via is formed between the first metal layer and the second metal layer. A first measure of a number of vacancies expected to reach the first via is obtained. A second via in at least one of the first metal layer and the second metal layer is formed if the measure of vacancies exceeds a first predetermined number.

Abstract: A method of polishing a wafer having a Ru film and a Ta film or TaN film beneath the Ru film is provided. This polishing method includes: polishing the Ru film by bringing the wafer into sliding contact with a polishing pad; measuring a thickness of the Ru film by a film thickness sensor while polishing the Ru film; calculating a derivative value of an output value of the film thickness sensor; detecting a predetermined point of change in the derivative value; and determining a removal point of the Ru film from a point of time when the point of change is detected.

Abstract: Some implementations provide a semiconductor package that includes a first die and a second die adjacent to the first die. The second die is capable of heating the first die. The semiconductor package also includes a leakage sensor configured to measure a leakage current of the first die. The semiconductor package also includes a thermal management unit coupled to the leakage sensor. The thermal management unit configured to control a temperature of the first die based, on the leakage current of the first die.

Abstract: An integrated circuit includes four electronic components, a buried UTBOX layer under and plumb with the electronic components, and two pairs of oppositely doped ground planes plumb with corresponding components under the layer. A first isolation trench mutually isolates the ground planes from corresponding wells made plumb and in contact with the ground planes and exhibiting the first doping type. Bias electrodes contact respective wells and ground planes. One pair of electrodes is for connecting to a first bias voltage and the other pair is for connecting to a second bias voltage. Also included are a semiconductor substrate exhibiting the first type of doping and a deeply buried well exhibiting the second type of doping. The deeply buried well contacts the other wells and separates them from the substrate. Finally, a control electrode couples to the deeply buried well.

Abstract: A semiconductor substrate having a surface is prepared. An electrical conductor film is formed on a region including the surface of the semiconductor substrate. The step of forming the electrical conductor film includes the steps of measuring, at a point of time when the electrical conductor film is partially formed, a characteristic related to at least one of alternating current loss and alternating current electrical conductivity of the electrical conductor film partially formed, and adjusting a film formation condition for forming the electrical conductor film based on the characteristic. Thereby, a surface roughness of the film being formed can be fed back to the film formation condition.

Abstract: An ion implantation system and method are disclosed in which glitches in voltage are minimized by modifications to the power system of the implanter. These power supply modifications include faster response time, output filtering, improved glitch detection and removal of voltage blanking. By minimizing glitches, it is possible to produce solar cells with acceptable dose uniformity without having to pause the scan each time a voltage glitch is detected. For example, by shortening the duration of a voltage to about 20-40 milliseconds, dose uniformity within about 3% can be maintained.

Abstract: A method for selective bump formation on a wafer includes performing a wafer test on the wafer. Known good dies (KGDs) on the wafer are identified based on the wafer test performed. Solder bumps are formed on the KGDs.

Abstract: A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell.