Including Control Responsive To Sensed Condition Patents (Class 438/5)
  • Patent number: 10330728
    Abstract: A method for minimizing a test set for optimal coverage is disclosed. The method includes generating a first test set which is both an empty and minimal test set. Then, generating a second test set with a predetermined number of tests. Further, partitioning the second test set into a control test set and an experiment test set. Subsequently, providing a list of tests for coverage by merging the control test set with the first test set to form a merged list of sets.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: June 25, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mrinal Bose, James Longino, Laxmi Narayana Yakkala
  • Patent number: 10331050
    Abstract: Lithography systems and methods are provided with enhanced performance based on broader utilization of the integrated metrology tool in the printing tool to handle the metrology measurements in the system in a more sophisticated and optimized way. Additional operation channels are disclosed, enabling the integrated metrology tool to monitor and/or allocate metrology measurements thereby and by a standalone metrology tool with respect to specified temporal limitations of the printing tool; to adjust and optimize the metrology measurement recipes; to provide better process control to optimize process parameters of the printing tool; as well as to group process parameters of the printing tool according to a metrology measurements landscape.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: June 25, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Eran Amit, Roie Volkovich, Liran Yerushalmi
  • Patent number: 10287707
    Abstract: A film growth apparatus according to one aspect of the present disclosure includes: a reactor configured to perform film growth processing on a substrate; an exhaust configured to discharge an exhaust gas from the reactor to the outside; a first valve including a valving element, the first valve provided in a pipe connecting the reactor with the exhaust and configured to control a pressure of the reactor by a position of the valving element; a valving element driver configured to cause the valving element to operate; and a valve controller including a closed position storage configured to store a closed position of the valving element, an opening degree controller configured to control the position of the valving element operated by the valving element driver, and a closed position shifter configured to detect a load of the valving element driver and shift the closed position in a case where the load exceeds a predetermined reference value.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: May 14, 2019
    Assignee: NuFlare Technology, Inc.
    Inventors: Yoshitaka Ishikawa, Hideshi Takahashi
  • Patent number: 10269663
    Abstract: An apparatus of a wafer processing apparatus includes at least one memory and logic, at least a portion of which is implemented in circuitry of the wafer processing apparatus including at least one processor coupled to the at least one memory. The logic may provide a 3D model of a surface of a wafer, the wafer defining a wafer plane; and modify a surface feature in a Z-direction along the surface of the wafer based on at least one of: an X-critical dimension (CD) extending along an X-direction of the wafer plane, and a Y-CD extending along a Y direction of the wafer plane.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: April 23, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Morgan D. Evans, Tristan Ma, Kevin Anglin, Motoya Okazaki, Johannes M. van Meer
  • Patent number: 10263001
    Abstract: A method of forming semiconductor memory device including following steps. Firstly, a substrate having a memory cell region and a peripheral region is provided, and a first semiconductor layer is formed on the substrate within the periphery region. Next, an insulating layer and a second semiconductor layer are formed on the substrate, and the second semiconductor layer covers the substrate, the first semiconductor layer and the insulating layer. Then, a sacrificial layer is formed on the second semiconductor layer, wherein top surfaces of the sacrificial layer within the memory cell region and the periphery region are coplanar. Following these, a removing process is performed to remove the sacrificial layer, the second semiconductor layer and the insulating layer, to expose the first semiconductor layer. After that, a top surface of the first semiconductor layer is leveled with a top surface of the second semiconductor layer.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: April 16, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Ming Huang, Chien-Cheng Tsai
  • Patent number: 10236199
    Abstract: A substrate processing method comprises: an execution step of executing the first processing for the plurality of substrates, and executing the second processing for the substrates having undergone the first processing; a recovery step of recovering the plurality of substrates having undergone the first processing and the second processing to the retraction chamber; a conditioning step of, after completion of the first processing for the last substrate among the plurality of substrates, loading a dummy substrate into the first processing chamber, executing the third processing for the dummy substrate, and unloading the dummy substrate from the first processing chamber; and a second execution step of, after the dummy substrate is unloaded from the first processing chamber in the conditioning step, loading the substrates recovered in the recovery step into the first processing chamber, and executing the third processing for the substrates loaded into the first processing chamber.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: March 19, 2019
    Assignee: CANON ANELVA CORPORATION
    Inventors: Kiyoshi Ehara, Mitsuo Suzuki
  • Patent number: 10224202
    Abstract: A catalyst is imparted selectively to a plateable material portion 32 by performing a catalyst imparting processing on a substrate W having a non-plateable material portion 31 and the plateable material portion 32 formed on a surface thereof. Then, a hard mask layer 35 is formed selectively on the plateable material portion 32 by performing a plating processing on the substrate W. The non-plateable material portion 31 is made of SiO2 as a main component, and the plateable material portion 32 is made of a material including, as a main component, a material containing at least one of a OCHx group and a NHx group, a metal material containing Si as a main component, a material containing carbon as a main component or a catalyst metal material.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: March 5, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Mitsuaki Iwashita, Takeshi Nagao, Nobutaka Mizutani, Takashi Tanaka, Koichi Yatsuda, Kazutoshi Iwai, Yuichiro Inatomi
  • Patent number: 10224187
    Abstract: A partial unclamping detection system is provided and includes a light emission circuit, a spectrometer, and a system controller. The light emission circuit is configured to emit light at an area of a substrate while the substrate is electrostatically clamped to an electrostatic chuck of a substrate processing system. The spectrometer is configured to detect light reflected off the substrate and generate a first output signal based on the detected light. The system controller is configured to: detect changes in the first output signal; detect changes in a flow rate of a gas supplied to a backside of the substrate; and based on both the changes in the first output signal and the changes in the flow rate, determine whether a partial unclamping event of the substrate has occurred.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: March 5, 2019
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Dmitry Opaits, Benny Wu, Jorge Luque
  • Patent number: 10191112
    Abstract: Disclosed are embodiments of a method that provides for pre-production run development of a fail signature database, which stores fail signatures for systematic defects and corresponding root causes. The fail signatures in the database is subsequently accessed and used for a variety of purposes. For example, the fail signatures are evaluated and, based on the results of the evaluation, actions are taken to prevent specific systematic defects from occurring during production runs and/or to allow for early detection of specific systematic defects during production runs. In some embodiments, following production runs, new fail signatures from failing production chips are developed and compared against the fail signatures in the fail signature database. In some embodiments, when a signature match indicates that a particular production chip has a same systematic defect with a same root cause as a particular prototype chip in-line advanced process control (APC) is performed.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Rao Desineni, Atul Chittora, Yan Pan, Sherwin Fernandes, Thomas Herrmann
  • Patent number: 10186461
    Abstract: A semiconductor device manufacturing method includes setting a local target thickness of any one of a semiconductor wafer and a film formed on the semiconductor wafer as a material to be etched by calculating a local thickness based on a thickness of the material to be etched at an end point detection position, and subtracting a predetermined relative etch amount from the local thickness to determine the local target thickness, and etching the material to be etched while monitoring the thickness thereof at the end point detection position, and ending the etching when the thickness of the material to be etched at the end point detection position is determined to become the local target thickness or less.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: January 22, 2019
    Assignee: Mistubishi Electric Corporation
    Inventor: Hiroshi Tanaka
  • Patent number: 10186513
    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes bit lines, a transistor, a dielectric layer, plugs and a capping layer. The bit lines are disposed on a substrate within a cell region thereof, and the transistor is disposed on the substrate within a periphery region. The plugs are disposed in the dielectric layer, within the cell region and the periphery region respectively. The capping layer is disposed on the dielectric layer, and the capping layer disposed within the periphery region is between those plugs. That is, a portion of the dielectric layer is therefore between the capping layer and the transistor.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: January 22, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • Patent number: 10168692
    Abstract: The embodiments described herein relate to methods, systems, and computer program products for improving the product quality of product lots produced on a production line. A quality value for each product lot is determined, and a quality benchmark is established. Each product lot is classified based on the quality benchmark. Product lots that have a quality value meeting the quality benchmark are classified as quality lots, and product lots having a quality value failing to meet the quality benchmark are classified as failing lots. Tools used in the production of the product lots are identified, which includes identifying a set of quality tools and a set of failing tools. Routing of additional product lots is directed by shifting production at least substantially to the set of quality tools.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Mark T. Lam, Ooi T. Ong
  • Patent number: 10163607
    Abstract: A method for controlling the temperature of a mounting table in a plasma processing apparatus, includes: calculating a first heat input amount according to high frequency power applied in a given process, wherein the first heat input amount is calculated based on a data table, the data table being generated by measuring temperatures so as to find a first relationship between the high frequency power applied in the plasma processing apparatus and the heat input amount to the mounting table; controlling, based on an operation map, the temperature of at least one of the first heating mechanism and the cooling mechanism so that a first temperature difference between the cooling mechanism and the first heating mechanism is within a controllable range corresponding to the first heat input amount, wherein the temperature of the first heating mechanism is controllable upon the first temperature difference falling within the controllable.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: December 25, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Keigo Toyoda, Hiroshi Tsujimoto
  • Patent number: 10153206
    Abstract: According to one embodiment, a dicing method is provided. The dicing method includes detecting a first distance between a first portion of a substrate and a first substrate information detection unit. The method also includes detecting a second distance between a second portion of the substrate a second substrate information detection unit, the second portion different from the first portion. Distance information is calculated between the substrate and a processing lens, which is located farther from the second substrate information detection unit than from the first substrate information detection unit, based on the detected first distance and the detected second distance, and he substrate is irradiated with laser light from the processing lens based on the distance information.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: December 11, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsutomu Fujita, Takanobu Ono
  • Patent number: 10102090
    Abstract: A method and system are provided for chip testing. The method includes ascertaining a baseline for a functioning chip with no stress history by performing a non-destructive test procedure on the functioning chip. The method further includes repeating the test procedure on a chip under test using a threshold derived from the baseline as a reference point to determine a stress history of the chip under test. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto, ranking each pattern based on at least one preceding available pattern to provide a plurality of pattern ranks, and calculating a sum by summing the pattern ranks. The sum calculated by the ascertaining step is designated as the baseline, and the sum calculated by the repeating step is compared to the threshold to determine the stress history of the chip under test.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: October 16, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith A. Jenkins, Barry P. Linder, Emily A. Ray, Raphael P. Robertazzi, Peilin Song, James H. Stathis, Kevin G. Stawiasz, Franco Stellari, Alan J. Weger, Emmanuel Yashchin
  • Patent number: 10037963
    Abstract: A package structure and method of forming the same includes: a first package including: a first die; a via adjacent the first die; a molding compound encapsulating the via and at least laterally encapsulating the first die around a perimeter of the first die; and a first redistribution structure extending over the first die and the molding compound; a first integrated passive device (IPD) attached to the first redistribution structure, the first IPD disposed proximate the perimeter of the first die; a second IPD attached to the first redistribution structure, the second IPD disposed distal the perimeter of the first die; and an underfill disposed between the first IPD and the first redistribution structure, the second IPD being free of the underfill.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Chen-Hua Yu, Hsien-Wei Chen, Der-Chyang Yeh
  • Patent number: 9984943
    Abstract: In a system for aligning at least two semiconductor structures for coupling, an alignment device includes a mounting structure having at least first and second opposing portions. The alignment device also includes a first mounting portion movably coupled to the first portion of the mounting structure, the first mounting portion configured to couple to a first surface of a first semiconductor structure. The alignment device additionally includes a second mounting portion movably coupled to the second portion of the mounting structure, the second mounting portion configured to couple to a second surface of a second semiconductor structure. The alignment device further includes one or more imaging devices disposed above at least one of the first and second mounting portions of the alignment device, the imaging devices configured to capture and/or or detect alignment marks in at least the first semiconductor structure.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: May 29, 2018
    Assignee: Massachusetts Institute of Technology
    Inventors: Keith Warner, Richard P. D'Onofrio, Donna-Ruth W. Yost
  • Patent number: 9922886
    Abstract: Embodiments of the invention include a method for forming a FinFET device and the resulting structure. A semiconductor device including a substrate, a silicon-germanium fin formed on the substrate, a dummy gate formed on the fin, and a first set of spacers formed on the exposed sidewalls of the dummy gate is provided. Xenon is implanted into the exposed portions of the fin. A second set of spacers are formed on the exposed sidewalls of the first set of spacer. A dopant is implanted into the exposed portions of the fin. The semiconductor device is thermally annealed, such that the dopants diffuse into the adjacent portions of the fin. The dummy gate is replaced with a gate structure.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Kam-Leung Lee, Alexander Reznicek
  • Patent number: 9922942
    Abstract: A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Isaac Lauer, Tenko Yamashita, Jeffrey W. Sleight
  • Patent number: 9915940
    Abstract: A method and system for linking sensor data to metrology data and metrology data to sensor data is described herein. In one embodiment, a user selection of metrology data for a product is received, related process tool fault detection summary for the selected metrology data for the product is presented, a user selection of a process tool from the process tool fault detection summary is received, and related fault detection details for the selected process tool are presented.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: March 13, 2018
    Assignee: Applied Materials, LLC
    Inventors: Brad Schulze, Joseph Dox
  • Patent number: 9881804
    Abstract: This disclosure relates to a plasma processing system and methods for high precision etching of microelectronic substrates. The system may include a plasma chamber that may generate plasma to remove monolayer(s) of the substrate. The plasma process may include a two-step process that uses a first plasma to form a thin adsorption layer on the surface of the microelectronic substrate. The adsorbed layer may be removed when the system transitions to a second plasma or moves the substrate to a different location within the first plasma that has a higher ion energy. In one specific embodiment, the transition between the first and second plasma may be enabled by changing the position of the substrate relative to the source electrode with no or relatively small changes in plasma process conditions.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: January 30, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Jianping Zhao, Merritt Funk
  • Patent number: 9773674
    Abstract: A method of etching a layer including at least one pattern that has flanks is provided, including at least one step of modifying the layer by putting the layer in presence with a plasma into which CxHy is introduced and which includes ions heavier than hydrogen; and wherein the plasma creates a bombardment of ions with a hydrogen base coming from the CxHy, the bombardment being anisotropic according to a main direction of implantation parallel to the flanks and so as to modify portions of the layer that are inclined with respect to the main direction and so as to retain unmodified portions on the flanks, wherein chemical species of the plasma form a carbon film on the flanks; and at least one step of removing the modified layer to be etched using a selective etching of modified portions of the layer with respect to the carbon film.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: September 26, 2017
    Assignee: COMMISARIAT A L'ENERGIE ATOMIQUE AUX ENERGIES ALTERNATIVES
    Inventor: Nicolas Posseme
  • Patent number: 9748088
    Abstract: A method includes processing each of a plurality of lots with at least one first equipment and moving some of the plurality of lots to a first storage. For each of a plurality of second equipments, an expected dispatch time of one or more next lots for processing by the second equipment is determined. Each of the lots in the first storage is assigned to one of the plurality of second equipments on the basis of at least the determined expected dispatch times and moved to one of a plurality of second storages that is associated with one of the plurality of second equipments to which the respective lot was assigned. For each of the plurality of second equipments, each of the lots in the second storage associated with the second equipment is moved to the second equipment and are processed with the second equipment.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: August 29, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Gero Grau, Steffen Kalisch, Joerg Weigang, William John Fosnight, Chinmay Oza, Detlef Pabst
  • Patent number: 9691715
    Abstract: A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: June 27, 2017
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Isaac Lauer, Tenko Yamashita, Jeffrey W. Sleight
  • Patent number: 9646864
    Abstract: A substrate processing system includes a plurality of processing chambers configured to perform a predetermined processing with respect to substrates, a transfer device configured to transfer the substrates to the processing chambers in a predetermined order, and a delivery unit configured to deliver the substrates between the delivery unit and the transfer device. The substrate processing system configured to sequentially process the substrates by repeating an operation in a predetermined transfer order. The substrate processing system includes a transfer order setting unit and a transfer control unit configured to switch the first transfer order to the second transfer order.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: May 9, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Daisuke Morisawa
  • Patent number: 9632499
    Abstract: Disclosed herein are methods and systems for semiconductor fabrication. In one embodiment, a method for fabricating semiconductors utilizing a semiconductor fabrication system includes performing a semiconductor fabrication process on a first lot of unprocessed semiconductor substrates with a semiconductor fabrication equipment unit to form a first lot of processed substrates and communicating processing data regarding the first lot of processed substrates from the semiconductor fabrication equipment unit to a just-in-time (JIT) module of the semiconductor fabrication system.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: April 25, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Chinmay Oza, Gero Grau, William Fosnight, Detlef Pabst
  • Patent number: 9634088
    Abstract: A method of forming a semiconductor device is disclosed including providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer, and forming a transistor device on the silicon-on-insulator substrate including providing a gate structure on the semiconductor layer having a gate electrode and a first cap layer on the gate electrode, growing an oxide liner on the transistor device having a first part covering the gate structure and a second part covering the semiconductor layer, forming a second cap layer on the oxide liner, at least partially removing the second part of the oxide liner underneath the second cap layer and the first part of the oxide liner, and epitaxially forming raised source/drain regions on the semiconductor layer.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: April 25, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hans-Juergen Thees, Peter Baars
  • Patent number: 9627369
    Abstract: A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends from a top surface of the polymer region into the polymer region, wherein each of the conductive features is exposed through one of the plurality of openings. The plurality of openings includes a first opening having a first horizontal size, and a second opening having a second horizontal size different from the first horizontal size.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Chun-Cheng Lin, Yu-Peng Tsai, Hsiu-Jen Lin, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9620335
    Abstract: A processing apparatus may include a plasma source coupled to a plasma chamber to generate a plasma in the plasma chamber, an extraction plate having an aperture disposed along a side of the plasma chamber; a deflection electrode disposed proximate the aperture and configured to define a pair of plasma menisci when the plasma is present in the plasma chamber; and a deflection electrode power supply to apply a bias voltage to the deflection electrode with respect to the plasma, wherein a first bias voltage applied to the deflection electrode is configured to generate a first angle of incidence for ions extracted through the aperture from the plasma, and a second bias voltage applied to the deflection electrode is configured to generate a second angle of incidence of ions extracted through the aperture from the plasma, the second angle of incidence being different from the first angle of incidence.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: April 11, 2017
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Costel Biloiu, Nini Munoz, Ludovic Godet, Anthony Renau
  • Patent number: 9569345
    Abstract: Localizing errors by: (i) running the testcase on a software model version of a processor to yield first testcase-run results in the form of a first set of values respectively stored in the set of data storage locations; (ii) creating a resource dependency information set based on the instructions of the testcase; (iii) running the testcase on a hardware version of the processor to yield second testcase-run results in the form of a second set of values respectively stored in the set of data storage locations; (iv) determining a set of miscompare data storage location(s), including at least a first miscompare data storage location, by comparing the first set of values and the second set of values; and (v) creating an initial dynamic slice of the data flow.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: February 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Ophir Friedler, Wisam Kadry, Amir Nahir, Vitali Sokhin
  • Patent number: 9513470
    Abstract: Systems and methods for imaging a target are provided. A system includes a detector and a substantially bitelecentric lens assembly positioned between the detector and the target. A first optical assembly is configured to focus light received from the substantially bitelecentric lens assembly onto the detector. The substantially bitelecentric lens assembly and the first optical assembly are configured to produce a collimated light space between the substantially bitelecentric lens assembly and the first optical assembly. A second optical assembly is positioned within the collimated light space.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: December 6, 2016
    Assignee: Vanderbilt University
    Inventor: Charles David Weaver
  • Patent number: 9478433
    Abstract: Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: October 25, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Qingjun Zhou, Jungmin Ko, Tom Choi, Sean Kang, Jeremiah Pender, Srinivas D. Nemani, Ying Zhang
  • Patent number: 9466734
    Abstract: To provide a semiconductor device having a vertical JFET excellent in off-state performance without reducing a production yield. A gate region quadrangular in the cross-section along a channel width direction is formed below a source region by impurity ion implantation. By first etching, the source region over the upper surface of the gate region is removed to separate therebetween. Then, the upper surface of the gate region is processed by second etching having an etching rate lower at the side surface than at the center of the gate region. The resulting gate region has a lower surface parallel to the substrate surface and an upper surface below a boundary between the source region and the channel formation region and having, in the cross-section along the channel width direction, a downward slope from the side surface to the center. As a result, a channel length with reduced variations can be obtained.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: October 11, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Arai, Yasuaki Kagotoshi, Kenichi Hisada
  • Patent number: 9412563
    Abstract: An RF plasma source has a resonator with its shorted end joined to the processing chamber ceiling and inductively coupled to two arrays of radial toroidal channels in the ceiling, the resonator having two radial zones and the two arrays of toroidal channels lying in respective ones of the radial zones.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: August 9, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Kartik Ramaswamy, Kenneth S. Collins, Shahid Rauf, Steven Lane, Yang Yang, Lawrence Wong
  • Patent number: 9400436
    Abstract: A detection device that detects a mark provided on the back side of an object, the detection device includes a first detection unit configured to detect the mark from a surface side of the object; a second detection unit configured to detect a surface position of the object; and a processing unit. The processing unit determines a thickness of the object based on a difference between a first focus position acquired with reference to the position of the mark detected by the first detection unit and a second focus position acquired with reference to the surface position detected by the second detection unit.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: July 26, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hironori Maeda
  • Patent number: 9326429
    Abstract: Cooling apparatuses are provided to facilitate active control of thermal and fluid dynamic performance of a coolant-cooled cold plate. The cooling apparatus includes the cold plate and a controller. The cold plate couples to one or more electronic components to be cooled, and includes an adjustable physical configuration. The controller dynamically varies the adjustable physical configuration of the cold plate based on a monitored variable associated with the cold plate or the electronic component(s) being cooled by the cold plate. By dynamically varying the physical configuration, the thermal and fluid dynamic performance of the cold plate are adjusted to, for example, optimally cool the electronic component(s), and at the same time, reduce cooling power consumption used in cooling the electronic component(s). The physical configuration can be adjusted by providing one or more adjustable plates within the cold plate, the positioning of which may be adjusted based on the monitored variable.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: April 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy J. Chainer, Pritish R. Parida
  • Patent number: 9293301
    Abstract: A processing apparatus may include a plasma source coupled to a plasma chamber to generate a plasma in the plasma chamber, an extraction plate having an aperture disposed along a side of the plasma chamber; a deflection electrode disposed proximate the aperture and configured to define a pair of plasma menisci when the plasma is present in the plasma chamber; and a deflection electrode power supply to apply a bias voltage to the deflection electrode with respect to the plasma, wherein a first bias voltage applied to the deflection electrode is configured to generate a first angle of incidence for ions extracted through the aperture from the plasma, and a second bias voltage applied to the deflection electrode is configured to generate a second angle of incidence of ions extracted through the aperture from the plasma, the second angle of incidence being different from the first angle of incidence.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: March 22, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Costel Biloiu, Nini Munoz, Ludovic Godet, Anthony Renau
  • Patent number: 9285249
    Abstract: One embodiment is directed towards a physics package of an atomic sensor. The physics package includes a frame composed of metal and including a plurality of slender support members extending between one another in a three dimensional structure. The support members define boundaries between adjacent apertures defined in the frame. The plurality of support members include a plurality of mounting surfaces adjacent to the apertures. The physics package also includes a plurality of panes attached to the mounting surfaces of the frame. The plurality of panes cover the apertures such that the frame and the plurality of panes define a vacuum chamber and provide three light paths that cross within the vacuum chamber at 90 degree angles with respect to one another. The physics package also includes a chamber evacuation structure for evacuating the vacuum chamber.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: March 15, 2016
    Assignee: Honeywell International Inc.
    Inventors: Christina Marie Schober, Jennifer S. Strabley, James A. Vescera, Kenneth Salit, Delmer L. Smith, Terry Dean Stark, Chad Langness, Karl D. Nelson
  • Patent number: 9236466
    Abstract: A circuit can include at least one pair of deeply depleted channel (DDC) transistors having sources commonly coupled to a same current path; and a bias circuit configured to provide bias currents to the drains of the DDC transistors; wherein each DDC transistor includes a source and drain doped to a first conductivity type, a substantially undoped channel region, and a highly doped screening region of the first conductivity type formed below the channel region.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: January 12, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Sang-Soo Lee, Heetae Ahn, Augustine Kuo
  • Patent number: 9153020
    Abstract: Provided are a semiconductor device defect inspection method and system thereof, with which predetermined hot spots are inspected using a SEM, and with which the frequency of defects occurring at the hot spot is estimated statistically and with reliability. An inspection point is designated in design data by the defect type. A plurality of pre-designated inspection points is selected by the defect type from the designated inspection points. The plurality of pre-designated inspection points by defect type thus selected are image captured by the inspection points. A defect ratio, which is a ratio of the plural inspection points which are image captured by the defect type to the plural defects detected, and a reliability interval of the defect ratio which is computed by the defect type is compared with a preset reference value. A defect type having a defect occurrence ratio which exceeds the reference value is derived.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: October 6, 2015
    Assignee: Hitachi High-Technologies Corporation
    Inventor: Yuji Takagi
  • Patent number: 9110386
    Abstract: A method comprises providing a semiconductor substrate having at least one layer of a material over the substrate. A sound is applied to the substrate, such that a sound wave is reflected by a top surface of the layer of material The sound wave is detected using a sensor. A topography of the top surface is determined based on the detected sound wave. The determined topography is used to control an immersion lithography process.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: August 18, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jen-Pan Wang, Chien-Hsuan Liu, Ching-Hsien Chen, Chao-Chi Chen
  • Patent number: 9075944
    Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: July 7, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Timothy A. Brunner, Stephen E. Greco, Bernhard R. Liegl, Hua Xiang
  • Patent number: 9059039
    Abstract: A bonding layer of the first wafer article is thermally treated and a bonding layer of a second wafer article is thermally treated in accordance with first and second process parameters, respectively prior to bonding the first wafer article with the second wafer article. First and second grid distortion in the first and second wafer articles is measured and a difference is determined between the first and second grid distortions. A prediction is made for maintaining the difference within a prescribed tolerance. At least one of the first process parameters and the second process parameters can be conditionally varied in accordance with the prediction. The thermally treating of the first wafer article and the thermally treating of the second wafer article can then be performed with respect to another pair of the first and second wafer articles prior to bonding the another pair of wafer articles to one another through their respective bonding layers.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Douglas C. La Tulipe, Jr., Wei Lin, Spyridon Skordas, Kevin R. Winstel
  • Publication number: 20150145146
    Abstract: Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.
    Type: Application
    Filed: February 3, 2015
    Publication date: May 28, 2015
    Inventors: Hongqi Li, Anurag Jindal, Irina Vasilyeva
  • Patent number: 9040465
    Abstract: A combination of deposition processes can be used to evaluate layer properties using a combinatorial workflow. The processes can include a base ALD process and another process, such as a PVD process. The high productivity combinatorial technique can provide an evaluation of the material properties for given ALD base layer and PVD additional elements. An ALD process can then be developed to provide the desired layers, replacing the ALD and PVD combination.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: May 26, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Prashant B Phatak, Venkat Ananthan, Wayne R French
  • Patent number: 9041209
    Abstract: In a disclosed embodiment, a method for tiling selected vias in a semiconductor device having a plurality of vias comprises generating a layout database for the semiconductor device; creating zones around the plurality of vias; measuring density of covering metal in each zone; selecting a low density zone as being a zone that has a metal density less than a threshold metal density; and adding at least one tiling feature on a metal layer above the plurality of vias in the low density zone so that metal density of the low density zone increases to at least the same as the threshold metal density.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: May 26, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Douglas M. Reber, Lawrence N. Herr
  • Patent number: 9040313
    Abstract: A method of manufacturing an organic light-emitting display device is provided. An alignment master member is loaded on a moving unit. An organic layer deposition assembly is pre-aligned to the alignment master member. After the pre-aligning of the organic layer deposition assembly, a substrate is loaded on the moving unit. The organic layer deposition assembly is aligned to the substrate positioned as is after the loading of the substrate. An organic layer is formed on the substrate while the moving unit is moving along the moving direction. While the moving unit is moving along the moving direction, the organic layer deposition assembly is adjusted so that an interval between the organic layer deposition assembly and part of the substrate is maintained as substantially constant. The part of the substrate receives a deposition material emitted from the organic layer deposition assembly to form the organic layer.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: May 26, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jong-Won Hong
  • Publication number: 20150140689
    Abstract: According to one embodiment, there is provided a substrate bonding method. The substrate bonding method includes disposing a first substrate and a second substrate to face each other. The substrate bonding method includes controlling the first substrate and the second substrate to have a temperature difference. The substrate bonding method includes, in a state where the first substrate and the second substrate are controlled to have the temperature difference, bonding the first substrate to the second substrate by bringing the first substrate into contact with the second substrate while deforming the first substrate so that a central portion of the first substrate is projected toward the second substrate. The central portion of the first substrate is on an inner side of a peripheral portion of the first substrate.
    Type: Application
    Filed: March 5, 2014
    Publication date: May 21, 2015
    Inventor: Mitsuyoshi ENDO
  • Publication number: 20150140690
    Abstract: There is provided an etching method for a semiconductor product. The semiconductor product having, on a substrate, an SiO2 layer, and an Si layer with a free surface and directly stacked on the SiO2 layer is prepared. The Si layer is etched. Etching is performed while supplying an etching solution from a side of the free surface using high-concentration fluonitric acid as the etching solution, and etching is continued by switching to fluonitric acid having a concentration lower than that of the fluonitric acid immediately before or after at least part of a surface of the SiO2 layer immediately under the Si layer is exposed.
    Type: Application
    Filed: December 9, 2014
    Publication date: May 21, 2015
    Applicant: TOHOKU UNIVERSITY
    Inventors: Takeshi Sakai, Tatsuro Yoshida, Kazuhiro Yoshikawa, Shigetoshi Sugawa
  • Publication number: 20150140688
    Abstract: A multiple-sample-holder polishing setup for cross-section sample preparation and a method of making a device using the same are presented. The multiple-sample-holder polishing setup includes a frame. The frame has a hollow center, one or more long and short rods and a recess for accommodating a polishing head. The setup includes one or more sample holders. The sample holder is to be attached to the one or more long and short rods of the frame. A paddle is affixed to each sample holder. A sample is attached to the paddle. The sample is coated with a thin epoxy layer prior to polishing thereby allowing for easy inspection for site of interests as well as quick material removal.
    Type: Application
    Filed: November 20, 2013
    Publication date: May 21, 2015
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Tsu Hau NG, Zhihong MAI, Mohammed Khalid Bin DAWOOD, Pik Kee TAN, Yamin HUANG, Jeffrey Chor-Keung LAM