Abstract: The present invention is generally directed to an advanced process control of the manufacture of memory devices, and a system for accomplishing same. In one illustrative embodiment, the method comprises performing at least one process operation to form at least one layer of an oxide-nitride-oxide stack of a memory cell, the stack being comprised of a first layer of oxide positioned above a first layer of polysilicon, a layer of silicon nitride positioned above the first layer of oxide, and a second layer of oxide positioned above the layer of silicon nitride. The method further comprises measuring at least one characteristic of at least one of the first layer of polysilicon, the first oxide layer, the layer of silicon nitride, and the second layer of oxide and adjusting at least one parameter of at least one process operation used to form at least one of the first oxide layer, the layer of silicon nitride and the second oxide layer if the measured at least one characteristic is not within acceptable limits.

Abstract: A method for fabricating a semiconductor integrated circuit device of the present invention forms an insulating film on a semiconductor wafer and forms a mask pattern containing a functional element or a wire on the formed insulating film. Dimensions of the mask pattern are changed in accordance with an amount of process variation occurring in the thickness or dielectric constant of the insulating film during the formation of the insulating film.

Abstract: A new test structure to locate bridging defects in a conductive layer of an integrated circuit device is achieved. The test structure comprises a line comprising a conductive layer overlying a substrate. The line is coupled to ground. A plurality of rectangles comprises the conductive layer. The rectangles are not connected to the line or to other rectangles. Near edges of the rectangles and of the line are parallel. The rectangles are floating. The test structure is used with a passive voltage contrast test in a scanning electron microscope. A test structure and method to measure critical dimensions is disclosed.

Abstract: Disclosed is a technique capable of enhancing the degree of freedom in the layout of a rerouting layer in a wafer level CSP in which defect repairing is performed by cutting a fuse. More specifically, after the defect repairing is performed by irradiating a laser beam to a fuse, an organic passivation layer (photo-sensitive polyimide layer) is filled in a fuse opening. Thereafter, a rerouting layer, a bump land, an uppermost wiring layer, and a solder bump are formed on the organic passivation layer. In the following steps of the defect repairing, the baking process to cure an elastomer layer and the uppermost protection layer is conducted at a temperature below 260° C. in order to prevent the variance of the refresh times of memory cells.

Abstract: An interposer, located between an integrated circuit having power, ground and signal connections and a ceramic substrate having power, ground and signal connections, that includes an oxide layer formed on a polished surface of a silicon substrate, a thin film dielectric capacitor formed on the oxide layer, a plurality of metallized that electrically connect to either of the electrodes of the thin film dielectric capacitor, and vias than conduct power, ground and signals between a the ceramic substrate and the integrated circuit. The interposer connects the metallized vias to the integrated circuit by solder connections and also connects the vias conducting power, ground and signals from the ceramic substrate to the interposer by solder connections.

Abstract: This invention relates to a method of depositing dielectric on a semiconductor substrate to form part of a capacitor. The method includes reactive sputtering a metal oxide layer from a target of metal onto the substrate wherein the support is biased to induce a DC voltage across the depositing dielectric as it forms. The voltage may be in the range of 200-300V.

Abstract: A method of detecting endpoint of a plasma etching system that measures the DC voltage drop across both the sheath and the film being etched. When the film is nearly removed, a drop in voltage indicates thinning of the film which detects endpoint for etching before optical emission techniques. The voltage drop is measured across resistors within the matching network.

Abstract: A system for WAT (Wafer Acceptance Test) configuration. The system comprises an input/output device, a storage device, and a processor. The input/output device receives a first WAT model and qualification criteria. The storage device stores a preset WAT model and qualification criteria. The processor modifies the preset WAT model according to the first WAT model to generate a second WAT model, and modifies the preset qualification criteria according to the first qualification criteria to generate second qualification criteria.

Abstract: A method for automated monitoring and controlling of a semiconductor wafer plasma process including performing a plasma process in a plasma processing system to treat a semiconductor process wafer according to a first plasma process recipe; collecting plasma process parameters including at least an RF power and a plasma process time at pre-determined time intervals; and, storing the plasma process parameters including pre-process plasma processing system parameters according to a selectively queryable database to create a plasma process history such that upon abortion of the plasma process the plasma process history may be selectively retrieved to determine a second plasma process recipe to complete the plasma process.

Abstract: A measuring method of the contact resistance of a probe includes bringing a plurality of probes including a first and second probes into contact with a plurality of electrode pads that is disposed on a semiconductor device to be electrically tested and connected each other with a conductive wiring; connecting a power supply to at least one predetermined first probe of the plurality of probes and supplying a current or a voltage from the first probe through the electrode pad and the wiring to the second probe to the semiconductor device; measuring the contact resistance between the electrode pad and the probe based on the current or the voltage supplied to the semiconductor device; judging whether the measured contact resistance is equal to or more than a predetermined value or not; and when the contact resistance is equal to or more than the predetermined value, the probes are cleansed.

Abstract: A method for preparing a semiconductor wafer for whole wafer backside inspection is disclosed. The frontside of the wafer is covered with a protective frontside substrate and the backside portion of the wafer is thinned using conventional techniques. The whole wafer backside is then polished and a backside substrate, preferably of transparent material is juxtaposed to the backside of the wafer, such as with an adhesive or with a frame. The frontside substrate is then removed, exposing electronic devices for device inspection. The backside of the wafer is maintained open or available to backside inspection such as emission microscopy techniques used to detect defects which emit light.

Abstract: A device and a method for determining the extent of an at least locally lateral undercut of a structured surface layer on a sacrificial layer. The structured surface layer for this purpose locally has at least one passive electronic component, using which a physical measured quantity can be determined, which is proportional to the extent of the lateral undercut. The method for generating this device proposes, initially on the structured surface layer in a first etching method, to provide the surface layer at least locally with a structuring having trenches and, in a second etching method, proceeding from the trenches, to undertake at least locally a lateral undercut of the structured surface layer. In this context, in the first etching method on the surface layer, locally at least one passive electronic component is additionally delineated out, which in response to a subsequent undercutting of the surface layer is also undercut.

Abstract: Under the first embodiment of the invention, back-end etching is applied to the specimen that needs to be inspected. Its surface is cleaned and mounted on a glass surface with the surface of the poly gate silicide that needs to be inspected being in contact with the surface of the glass. The exposed surface of the sample that is to be examined contains silicon, this silicon is removed. The gate oxide is then removed followed by the removal of the remaining poly of the gate structure. The second embodiment of the invention addresses poly gate inspection by enhanced (top surface of the gate electrode) gas etching of the gate electrode to remove gate oxide and silicon remains from the environment of the silicide. The specimen is etched back to the contact layer using a conventional Chemical Mechanical Polishing (CMP) process. The polished surface of the specimen is next exposed to XeF2, which selectively removes the oxide while the silicide remains in place.

Abstract: A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the dice with the temporary test package bases, and an automated robot arm system is employed to retrieve and assemble the dice with the various package components. The invention has particular utility in the burn-in and other pre-packaging testing of dice to establish known good dice (KGD).

Abstract: An RF power supply system (200) for use with an electrode (60) in a plasma reactor system (10) capable of supporting a plasma (32) with a plasma load impedance (ZR), wherein the electrode comprises a plurality of electrode segments (62a,62b, . . . , 62n). The system comprises a master oscillator (210), and a plurality of RF power supply subsystems (220a, 220b, . . . 220n) each electronically connected thereto, and to respective ones of the electrode segments. Each RF power supply subsystem includes a phase shifter (224), an amplifier/power supply (230), a circulator (236), a directional coupler (242), and a match network (MN/L). The latter has a match network impedance. The system further includes a control system (184) electronically connected to each RF power supply subsystem.

Abstract: Defects in manufacturing of IC devices are analyzed by testing the devices for defects using results of LSSD technology to find at least one failing pattern that contains incorrect values. The failing latches are used as a starting point to trace back through combinational logic feeding the failing latches, until controllable latches are encountered. A decision is then made to continue the back tracing or not depending on whether the latter latches were clocked during the application of one of the failing patterns or not.

Abstract: The present invention relates to a process for etching a metal layer system. The metal layer system includes a first aluminum-containing layer, a second aluminum-containing layer, and an interlayer arranged between the two aluminum-containing layers. The interlayer consists of a material that is suitable for end-point detection. The etching process includes a first etching step, in which the upper aluminum-containing layer is etched using a first etching angle, and a second etching step, in which the lower aluminum-containing layer is etched using a second etching angle. The process switches between the first etching step and the second etching step as soon as the end-point detection has detected that the interlayer has been reached. Accordingly, the interlayer is arranged at a location at which it is intended for the process to switch from the first etching step to the second etching step.

Abstract: A method of fabricating an electric circuit, including first and second working processes of performing respective first and second working operations on a circuit substrate, where3in the first working process includes a first substrate-identifying step of obtaining substrate identifying information identifying the substrate on which the first working operation is to be performed, a specific-information obtaining step of recognizing a specific-information providing portion of the substrate, to obtain specific information indicating at least one specific characteristic of the substrate, a first working step of performing the first working operation on the basis of the obtained specific information, and a specific-information storing step of storing the specific information in relation to the substrate identifying information, and the second working process includes a second substrate-identifying step of obtaining the substrate identifying information identifying the substrate on which the second working operat

Abstract: In certain embodiments a plasma is supplied from a plasma chamber 10 into a reaction chamber 18 of a plasma CVD apparatus. An electrode 22 is disposed in the reaction chamber 18. A semiconductor wafer on which a thin film is to be formed is placed on the electrode 22. A radio-frequency wave is generated by a radio-frequency wave generator 28 and supplied to the electrode 22 via a radio-frequency matching network 30, a blocking capacitor 32, and an RF probe 34 so as to control the plasma in the plasma chamber 10. A judgment device 38 is electrically connected to the RF probe 34. The voltage and current are be measured by the RF probe and the judgment device 38 is used to judge the state of the plasma in the plasma chamber 10.

Abstract: Disclosed are methods and apparatus for detecting defects in a partially fabricated semiconductor device with self-aligned contacts. The self-aligned contacts are formed from a first layer with a plurality of contact portions, a second layer with a plurality of conductive lines that are each aligned proximate to an associated underlying contact portion, and a third insulating layer formed over the conductive lines and their proximate underlying contact portions. The third insulating layer has a plurality of vias formed therein that are each formed alongside a one of the conductive lines and over its proximate underlying contact portion. A charged particle beam is scanned over a portion of the vias to form a voltage contrast image of each via. When a minority of the vias in the image have a significantly different brightness level than a majority of the vias, it is then determined that the minority of vias have defects.

Abstract: An integrated circuit device has a device main body 1 having a predetermined circuit function of providing an output corresponding to an input thereto, and is provided with a power supply section 4 for receiving through a coil 3 electromagnetic wave energy applied from outside to generate predetermined internal electric power required to operate the integrated circuit device. The integrated circuit device further includes a calibration data acquisition circuit (operation control section 5) for detecting the output of the device main body 1 operated in a predetermined operating environment to obtain calibration data on the device main body, and a nonvolatile memory 6 for storing the calibration data.

Abstract: A multi-step etching process for a lead overlay structure such as a thin-film magnetic head structure using secondary ion mass spectroscopy (SIMS) whereby high selectivity of a lead material or other high conductivity metal layer is realized versus that of a metallic mask material and stopping layer. The first step includes patterning the mask layer using IBE or RIE. Advantageously, a photoresist layer is present over a portion of the mask layer and is left in place to be removed in a subsequent step. The second step includes etching the high conductivity metal layer using CAIBE or RIBE with an inert/reactive gas mixture and using SIMS to detect when the stopping layer is reached.

Abstract: A method of measuring the stress migration of vias, and a the structure, the method comprising the following steps. A metal line having a middle and opposing first and second ends is formed. First and second opposing pads electrically connected to the respective opposing first and second ends of the metal line through respective first and second step-width line structures are formed. A third pad connected to the metal line proximate its first end by a first via through a first metal structure is formed. A fourth pad connected to the metal line proximate its second end by a second via through a second metal structure is formed. The first and second vias are equidistant from the respective first and second ends of the metal line. The stress migration of the first via is determined by measuring the: sheet resistance between the first pad and the third pad; and/or the stress migration of the second via is determined by measuring the sheet resistance between the fourth pad and the second pad.

Abstract: A method of predicting the effect of blob test in GSP sample testing is disclosed.

Abstract: A mirror device having an optical system of an exposure apparatus for transferring a reticle pattern onto a wafer includes a mirror, a mirror holding portion, a temperature adjustment unit, a control management database, and a timing control unit. The mirror reflects exposure light, and the mirror holding portion holds the mirror. The temperature adjustment unit adjusts a temperature of the mirror and the mirror holding portion. The control management database stores data corresponding to a controlling rule of the temperature adjustment unit necessary to keep the mirror figure constant for an incidence condition of the reflected exposure light. The timing control unit controls the temperature adjustment unit corresponding to the incidence condition of the exposure light. The timing control unit controls the temperature adjustment unit based on the stored data of the control management database to keep the mirror figure constant.

Abstract: The present invention provides, in one embodiment, a method method of monitoring a process for forming a nitridated oxide gate dielectric. A nitrided oxide dielectric layer is formed on a test substrate (110). The nitrided oxide dielectric layer is exposed to an etch process (120). A change in a property of the nitrided oxide dielectric layer is measured as a function of the etch process (130). Other embodiments advantageously incorporate the method into methods for making semiconductor devices and integrated circuits.

Abstract: A method for controlling a gap in an electrically conducting solid state structure provided with a gap. The structure is exposed to a fabrication process environment conditions of which are selected to alter an extent of the gap. During exposure of the structure to the process environment, a voltage bias is applied across the gap. Electron tunneling current across the gap is measured during the process environment exposure and the process environment is controlled during process environment exposure based on tunneling current measurement. A method for controlling the gap between electrically conducting electrodes provided on a support structure. Each electrode has an electrode tip separated from other electrode tips by a gap. The electrodes are exposed to a flux of ions causing transport of material of the electrodes to corresponding electrode tips, locally adding material of the electrodes to electrode tips in the gap.

Abstract: A method and apparatus for operating a matching network within a plasma enhanced semiconductor wafer processing system that uses pulsed power to facilitate plasma processing.

Abstract: Disclosed is a method for the electrochemical oxidation of a semiconductor layer. In an electrochemical oxidation treatment for the production process of an electron source 10 (field-emission type electron source) as one of electronic devices, a control section 37 determines a voltage increment due to the resistance of an electrolytic solution B in advance, based on a detected voltage from a resistance detect section 35. Then, the control section 37 controls a current source to supply a constant current so as to initiate an oxidation treatment for a semiconductor layer formed on an object 30. The control section 37 corrects a detected voltage from a voltage detect section 36 by subtracting the voltage increment therefrom. When the corrected voltage reaches a given upper voltage value, the control section 37 is operable to discontinue the output of the current source 32 and terminate the oxidation treatment.

Abstract: A testing apparatus for determining the etch bias associated with a semiconductor-processing step includes a substrate, a first cathode finger with a first width on the substrate, a second cathode finger with a second width on the substrate, and a cathode large area on the substrate wherein the cathode large area has a third width W″ and a length L″ that are both substantially larger than either of the first and second widths.

Abstract: A method for testing tunnel oxide on a memory-related structure. In one method embodiment, the present invention accesses a memory-related structure during a manufacturing process. Next, the present embodiment applies a constant voltage to a gate of the memory-related structure. The present embodiment then measures a first gate current for the memory-related structure when the constant voltage is initially applied, to obtain a first value. Next, the present embodiment measures a second gate current for the memory-related structure a period of time after the constant voltage is initially applied to obtain a second value. A calculation of ratio of the second value to the first value is then performed. The present embodiment then generates a graph of the first value and the ratio of the second value to the first value as a function of time, wherein a decrease in the graph signifies stress induced electron trapping behavior of the tunnel oxide.

Abstract: The present invention relates to a tool for analyzing by priority a defect having a high possibility of causing an electrical failure when inspecting a particle and a pattern defect in a piece of work which constitutes an electronic device such as a semiconductor integrated circuit, and relates to a system therefor. On the basis of the result of comparison between defect information which is the result of inspection by an inspection tool and layout data stored in an auxiliary storage device, or on the basis of the result of reinspection by comparison between a defect and a wiring pattern as a background by an inspection processing operation unit, an object to be reviewed is selected using review conditions stored in the auxiliary storage device.

Abstract: A method of fabricating a semiconductor device characterized in that the method includes the steps of forming basic structures of unit FETs on each of ‘m’ active layer regions more than the number of designed unit FETs and determining the number ‘n’ of desired basic structures on the basis of a drain current value of the semiconductor device predicted from a measured value of the drain current characteristics of one of the basic structures. The contact holes for electrical connections to electrodes of each of the unit FETs are formed for only the regions on ‘n’ basic structures in an inter-layer insulating film. In this manner, there is provided a method of fabricating a semiconductor device, the method being capable of improving degraded characteristics after the characteristics of TEG-FET have been measured.

Abstract: Disclosed is a method for the electrochemical oxidation of a semiconductor layer. In an electrochemical oxidation treatment for the production process of an electron source 10 (field-emission type electron source) as one of electronic devices, a control section 37 determines a voltage increment due to the resistance of an electrolytic solution B in advance, based on a detected voltage from a resistance detect section 35. Then, the control section 37 controls a current source to supply a constant current so as to initiate an oxidation treatment for a semiconductor layer formed on an object 30. The control section 37 corrects a detected voltage from a voltage detect section 36 by subtracting the voltage increment therefrom. When the corrected voltage reaches a given upper voltage value, the control section 37 is operable to discontinue the output of the current source 32 and terminate the oxidation treatment.

Abstract: A system and method of generating RF includes a supply voltage source, an oscillator, an output amplifier, a load network, a peak voltage detector and a comparator circuit. The oscillator has a control signal input and an RF signal output. The output amplifier is coupled to the oscillator output. The load network is coupled between an output of the output amplifier and an output of the RF generator. The peak voltage detector is coupled across the output amplifier. The comparator circuit includes a first input coupled to the supply voltage source, a second input coupled to an output of the peak voltage detector, and a comparator output coupled to the oscillator control signal input.

Abstract: A system and method of cleaning a substrate includes a megasonic chamber that includes a transducer and a substrate. The transducer is being oriented toward the substrate. A variable distance d separates the transducer and the substrate. The system also includes a dynamically adjustable RF generator that has an output coupled to the transducer.

Abstract: A system and method of providing RF to a transducer includes an oscillator, an RF generator, and a voltage phase detector. The oscillator has a frequency control input and an RF signal output. The RF generator has an input coupled to the oscillator RF signal output and an RF generator output coupled to the transducer. The voltage phase detector includes a first phase input coupled to the RF signal output of the oscillator, a second phase input coupled to the RF generator output, and a frequency control signal output coupled to the oscillator frequency control voltage input.

Abstract: In a method apparatus for measuring the temperature of a semiconductor substrate during processing thereof in a processing chamber, a resonant circuit formed on the substrate surface is energized by an electromagnetic field radiation device, and disturbances in the electromagnetic field are detected to determine the resonant frequency of the resonant circuit. The temperature of the substrate is determined as a function of the resonant frequency. The substrate is moved into and out of processing chamber by a transfer arm, and the radiation device is disposed on the transfer arm or mounted on the processing chamber. Multiple resonant circuits may be provided, which are energized by movement of the transfer arm, without transferring the substrate.

Abstract: A method and an apparatus for dynamic targeting for a process control system. A process step is performed upon a first workpiece in a batch based upon a process target setting. The process target setting comprises at least one parameter relating to a target characteristic of the first workpiece. Manufacturing data relating to processing of the first workpiece is acquired. The manufacturing data comprises at least one of a metrology data relating to the processed first workpiece and a tool state data relating to the tool state of a processing tool. Electrical data relating to the processed first workpiece is acquired at least partially during processing of a second workpiece in the batch. The process target setting is adjusted dynamically based upon a correlation of the electrical data with the manufacturing data.

Abstract: An integrated circuit design is provided capable of operating in multiple insertion orientations. In particular, the inventive circuit design includes an integrated circuit package having a plurality of contact elements extending from the integrated circuit package and arranged symmetrically thereon for enabling the integrated circuit to be inserted on a circuit board in at least two discrete orientations. A plurality of the contact elements are designated as orientation pins, the orientation pins being arranged such that, upon integrated circuit package power up, the orientation pins transmit orientation signals indicative of the integrated circuit packages insertion orientation in the circuit board. A plurality of multiplexer devices are provided for routing signals between the contact elements and integrated circuit functional circuitry in response to the orientation signals from the orientation pins.

Abstract: A chip module element having an array of capacitors, a planar interconnect structure coupled to the array of capacitors, and a multilayer circuit structure coupled to the planar interconnect structure. The planar interconnect structure includes a plurality of conductive elements (e.g., z-connections and conductive posts) electrically communicating the capacitors and the multilayer circuit structure. A plurality of conductive pins is coupled to the multilayer circuit structure. The array of capacitors is capable of being charged by providing an electrical current which passes from the pins, through the multilayer circuit structure, through the conductive elements, and to the capacitors. A method for making a chip module element comprising forming an array of capacitors, electrically testing the capacitors in the array to determine which capacitors are defective and which are acceptable, and storing data of the defective capacitors in an information storage medium.

Abstract: An alignment apparatus which generates driving forces with six degrees of freedom between stator coils and movable element magnets to implement high-accuracy position and posture control has movable element magnets (114) which are arrayed in a plate-like plane of the movable element in accordance with an array cycle and are magnetized in predetermined directions, stator coils (116) which are arrayed at intervals corresponding to the array cycle, and a current controller which supplies to each pair of adjacent ones of stator coils control currents having phase differences to generate driving forces for driving the movable element between the movable element magnets and stator coils facing the movable element magnets.

Abstract: The present invention is a system for creating a signature of a substrate manufactured in a semiconductor or data storage fabrication facility. A central processing unit is configured to receive external sensor data from a plurality of equipment-types located within the facility and integrate the external sensor data, by combining the data into a unitary whole, to create the signature for the substrate. Additionally, the present invention is a method for creating a signature of the substrate by selecting a substrate from the facility process line, receiving external sensor data associated with the substrate from a plurality of equipment-types, and integrating the external sensor data associated with the substrate to create the signature of the substrate. The created substrate signature may also be compared with other substrate signatures to electronically diagnose a process, equipment associated with the process, or a processed substrate.

Abstract: The present invention is a system for creating a signature of a substrate manufactured in a semiconductor or data storage fabrication facility. A central processing unit is configured to receive external sensor data from a plurality of equipment-types located within the facility and integrate the external sensor data, by combining the data into a unitary whole, to create the signature for the substrate. Additionally, the present invention is a method for creating a signature of the substrate by selecting a substrate from the facility process line, receiving external sensor data associated with the substrate from a plurality of equipment-types, and integrating the external sensor data associated with the substrate to create the signature of the substrate. The created substrate signature may also be compared with other substrate signatures to electronically diagnose a process, equipment associated with the process, or a processed substrate.

Abstract: A method for electrically contacting a rear side of a semiconductor substrate when processing the semiconductor substrate includes the step of placing the semiconductor substrate with a substrate rear side on a substrate holder such that an electrically conductive contact layer formed of a semiconductor material is disposed between the semiconductor substrate and the substrate holder.

Abstract: A transfer recording material allowing the production of customized holographic images is described. The transfer recording material comprises a multilayer structure on a carrier forming a plurality of panels. A portion of the multilayer structure corresponding to a panel comprises an embossable layer (holographic layer) wherein each pixel is configured to reflect incoming light at a predetermined angle #1. Each pixel corresponding to the embossable layer of an adjacent panel is configured to reflect incoming light at a different predetermined angle #2. The transfer recording material can have as many panels as desired by a particular application, each of the layers having an embossable layer with pixels configured to reflect incoming light at a certain angle #. The transfer material is therefore formed by a plurality of spaced-apart panels each of which comprises an embossable holographic layer reflecting light at a predetermined angle different from that of other panels.

Abstract: A front-end-of-line piece of a semiconductor die is manufactured in a first manufacturing line. A back-end-of-line piece of a semiconductor die is manufactured using a second manufacturing line, which will typically be different than the first manufacturing line. The front-end-of-line piece and the back-end-of-line piece are combined during a joining process to form a semiconductor die. The semiconductor die is subsequently tested to determine if the semiconductor die is a functional semiconductor die.

Abstract: A method of repairing organic light-emitting element pixels for repairing an organic light-emitting element having a substantial short circuit portion or portions. The method includes an electrical testing step and an insulator-forming step. The organic light-emitting element includes an anode substrate, an organic functional layer and a cathode. In this case, a current or voltage is applied to the anode substrate and the cathode of the organic light-emitting element respectively in the electrical testing step, so that the short circuit portion or portions of the organic light-emitting element are transformed to an open circuit portion or portions. In the insulator-forming step, an insulator is formed at the open circuit portion or portions of the organic light-emitting element. The invention also discloses a method of repairing organic light-emitting element pixels, which further includes an electrical detection step.

Abstract: Multi-chip module systems and method of fabrication thereof wherein the equivalent of a failed die of a multi-chip module (MCM) is added to the module in a vacancy position previously constructed with appropriate electrical connections. A variety of different dice may be attached to the same vacancy position of an MCM by means of adapters, wherein each adapter has the same footprint, but different adapters are capable of accommodating different numbers and types of dice.

Abstract: A method and system can compensate for anneal non-uniformities by implanting dopant in a pattern to provide higher dopant concentrations where the anneal non-uniformities result in lower active dopant concentrations. A pattern for the anneal non-uniformities may be determined by annealing a wafer having a uniform dopant distribution and measuring properties of the wafer after annealing, e.g., by obtaining a sheet resistance map of the wafer. In one embodiment, the non-uniformities may be measured by measuring temperature variations during annealing.