Including Adhesive Bonding Step Patents (Class 438/118)
  • Patent number: 10361068
    Abstract: A method of forming a feature in a void, the method including filling the void having at least one sloped wall with a polymeric material; forming a layer of photoresist over the polymeric material; forming a gap in the layer of photoresist; and etching the polymeric material exposed by the gap in the layer of photoresist to form a feature.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: July 23, 2019
    Assignee: Seagate Technology LLC
    Inventors: Sridhar Dubbaka, Sriram Viswanathan, Christina Hutchinson
  • Patent number: 10347508
    Abstract: A method includes applying a die attach material to a die pad of an integrated circuit. The die attach material is employed as a bonding material to the die pad. The method includes mounting an integrated circuit die to the die pad of the integrated circuit via the die attach material. The method includes printing an adhesion deposition material on the die attach material appearing at the interface of the integrated circuit die and the die pad of the integrated circuit to mitigate delamination between the integrated circuit die and the die pad.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: July 9, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yong Lin, Rongwei Zhang, Benjamin Stassen Cook, Abram Castro
  • Patent number: 10334725
    Abstract: A system for assembling electronic circuits on an electrically non-conductive surface or substrate. The system incorporates electronic components integrated into electronic component modules. The electronic component modules include identification markings on the top surfaces and electronic contact pads on the bottom surfaces. Electrical interconnects between discrete electronic component modules is achieved through the use of electrically conductive traces placed on the substrate surface. The bottom surfaces of the electronic component modules are coated with an adhesive so the electronic component modules can be mounted onto the substrate. The electronic component modules are affixed to the substrate such that the electronic component modules contact pads make electrical contact with the appropriate electrically conductive traces.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: June 25, 2019
    Inventor: Richard A. Marasas, Jr.
  • Patent number: 10297485
    Abstract: A semiconductor device is provided comprising a support, an adhesive resin layer, an insulating layer, a redistribution layer, a chip layer, and a mold resin layer. The adhesive resin layer consists of a resin layer (A) comprising a photo-decomposable resin containing a fused ring in its main chain and a resin layer (B) comprising a non-silicone base thermoplastic resin and having a storage elastic modulus E? of 1-500 MPa at 25° C. and a tensile break strength of 5-50 MPa. The semiconductor device is easy to fabricate and has thermal process resistance, the support is easily separated, and a semiconductor package is efficiently produced.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: May 21, 2019
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Hiroyuki Yasuda, Michihiro Sugo, Hideto Kato, Kazunori Kondo
  • Patent number: 10217686
    Abstract: The present disclosure relates to an air-cavity package, which includes a bottom substrate, a top substrate, a perimeter wall, a bottom electronic component, a top electronic component, and an external electronic component. The perimeter wall extends from a periphery of a lower side of the top substrate to a periphery of an upper side of the bottom substrate to form a cavity. The bottom electronic component is mounted on the upper side of the bottom substrate and exposed to the cavity. The top electronic component is mounted on the lower side of the top substrate and exposed to the cavity. And the external electronic component is mounted on an upper side of the top substrate, which is opposite the lower side of the top substrate and not exposed to the cavity.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: February 26, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Walid M. Meliane, Kevin J. Anderson, Tarak A. Railkar
  • Patent number: 10209478
    Abstract: A filter unit that is used by being detachably mounted on a lens barrel constituting an imaging device is configured so as to include a discoidal filter body, an annular filter frame that receives the filter body, an adhesion film that is formed between the filter frame and the filter body and that is formed of an elastic adhesion, and a decorative annular frame received at a portion that is inside the filter frame and that is, when mounted on the lens barrel, on the imaging object side with respect to the filter body. The filter body and the filter frame are in noncontact with each other by forming the adhesion film between the filter frame and the filter body, and by disposing the decorative annular frame, the adhesion film is hidden under the appearance of the filter unit when the filter unit is mounted on the lens barrel.
    Type: Grant
    Filed: September 7, 2015
    Date of Patent: February 19, 2019
    Assignee: Kenko Tokina Co., Ltd.
    Inventor: Eiji Okado
  • Patent number: 10186458
    Abstract: A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: January 22, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Karl Mayer, Evelyn Napetschnig, Michael Pinczolits, Michael Sternad, Michael Roesner
  • Patent number: 10186503
    Abstract: The module is implemented on a circuit board, the module including a wiring board; an electronic component implemented on a first surface of the wiring board; an external connection electrode formed on a second surface of the wiring board; a solder bump connected to the external connection electrode; a bare chip implemented facedown on the second surface of the wiring board; and a resin covering a surface and a side surface of the bare chip and a side surface of the solder bump on the second surface of the wiring board, wherein a reverse surface of the bare chip and a connection surface of the solder bump are exposed from the resin such that the reverse surface of the bare chip and the connection surface of the solder bump are on a same plane, and wherein the module is implemented on the circuit board so that the reverse surface of the bare chip and the connection surface of the solder bump face the circuit board.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: January 22, 2019
    Assignee: MITSUMI ELECTRIC CO., LTD.
    Inventors: Makoto Kitazume, Toshiki Komiyama
  • Patent number: 10170299
    Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.
    Type: Grant
    Filed: June 18, 2016
    Date of Patent: January 1, 2019
    Assignee: Applied Materials, Inc.
    Inventors: He Ren, Mehul B. Naik, Yong Cao, Yana Cheng, Weifeng Ye
  • Patent number: 10131826
    Abstract: An adhesive film for a semiconductor chip with a through electrode, which is used for stacking multiple semiconductor chips each with a through electrode on a semiconductor wafer, which can favorably connect the through electrodes while suppressing formation of voids, and which can reduce the length of burrs protruding around the semiconductor chips. An adhesive film for a semiconductor chip with a through electrode, to be used for stacking multiple semiconductor chips each with a through electrode on a semiconductor wafer, the adhesive film having a minimum melt viscosity of 50 to 2500 Pa·s and a thixotropic index at 140° C. of 8 or lower.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: November 20, 2018
    Assignee: SEKISUI CHEMICAL CO., LTD.
    Inventors: Mai Nagata, Kohei Takeda, Toshio Enami
  • Patent number: 10103298
    Abstract: A light emitting diode (LED) module which includes: a substrate; a resist including a plurality of layers above the substrate; and an LED element mounted above the substrate. The plurality of layers includes a second layer that is an uppermost layer and a first layer that is an underlying layer. The second layer that is the uppermost layer includes fluorine as a component.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: October 16, 2018
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Naoki Tagami, Masumi Abe, Hisaki Fujitani, Kosuke Takehara, Toshiaki Kurachi
  • Patent number: 10090177
    Abstract: Systems and methods for releasing semiconductor dies during pick and place operations are disclosed. In one embodiment, a system for handling semiconductor dies comprises a support member positioned to carry at least one semiconductor die releasably attached to a support substrate. The system further includes a picking device having a pick head coupleable to a vacuum source and positioned to releasably attach to the semiconductor die at a pick station. The system still further includes a cooling member coupleable to a cold fluid source and configured to direct a cold fluid supplied by the cold fluid source toward the support substrate at the pick station. The cold fluid cools a die attach region of the substrate where the semiconductor die is attached to the substrate to facilitate removal of the semiconductor die.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: October 2, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jeremy E. Minnich, Benjamin L. McClain, Travis M. Jensen
  • Patent number: 10079175
    Abstract: Insulating a via in a semiconductor substrate, including: depositing, in the via, a dielectric layer; depositing, in the via, a barrier layer; allowing the barrier layer to oxidize; and depositing, in the via, a conducting layer.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Jennifer A. Oakley, Kevin S. Petrarca, Nicole R. Reardon, Andrew H. Simon
  • Patent number: 10068853
    Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an active surface, a plurality of sidewalls connected to the active surface, and a plurality of pads distributed on the active surface. The insulating encapsulation encapsulates the active surface and the sidewalls of the integrated circuit. The insulating encapsulation includes a plurality of first contact openings and a plurality of through holes, and the pads are exposed by the first contact openings. The redistribution circuit structure includes a redistribution conductive layer, wherein the redistribution conductive layer is disposed on the insulating encapsulation and is distributed in the first contact openings and the through holes. The redistribution conductive layer is electrically connected to the pads through the first contact openings. A method of fabricating the integrated fan-out package is also provided.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: September 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hsiang Hu, Hung-Jui Kuo, Yi-Wen Wu
  • Patent number: 10049985
    Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a dielectric layer and providing electrical connection to source/drain epitaxial regions surrounding a set of fins, the contact line including: a first portion of the contact line electrically isolated from a second portion of the contact line by a contact line spacer, wherein the first portion and the second portion each include a liner layer and a metal, the liner layer separating the metal from the dielectric layer and the source/drain epitaxial regions, and wherein the metal is directly in contact with the contact line spacer.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: August 14, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Veeraraghavan S. Basker, Keith H. Tabakman, Patrick D. Carpenter, Guillaume Bouche, Michael V. Aquilino
  • Patent number: 10014537
    Abstract: The present disclosure is directed to a method and system for dynamically controlling seal decompression. The method includes monitoring a set of parameters associated with an operation of a seal, wherein the set of parameters includes a maximum pressure subjected to the seal and an exposure time at the maximum pressure, calculating a target pressure ramp down rate based on at least one of the maximum pressure and the exposure time, and decreasing a pressure about the seal at a decompression rate that is based on the target pressure ramp down rate.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: July 3, 2018
    Assignee: Nuvera Fuel Cells, LLC
    Inventor: Scott Blanchet
  • Patent number: 10008405
    Abstract: An embodiment of the present invention relates to an expansion method comprising: a step (I) of preparing a laminate having a semiconductor wafer in which modified sections have been formed along intended cutting lines, a die bonding film and a dicing tape, a step (IIA) of expanding the dicing tape with the laminate in a cooled state, a step (IIB) of loosening the expanded dicing tape, and a step (IIC) of expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening the spaces between the chips.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: June 26, 2018
    Assignee: HITACHI CHEMICAL COMPANY, LTD
    Inventors: Yukihiro Iwanaga, Kouji Suzumura, Tatsuya Sakuta
  • Patent number: 10002811
    Abstract: An electronic component package includes a wiring part including an insulating layer, a conductive pattern formed on the insulating layer, and a conductive via connected to the conductive pattern through the insulating layer, an electronic component disposed on the wiring part, a frame disposed on the wiring part and having a through hole accommodating the electronic component, an adhesive layer bonding the wiring part and the frame to each other, and an encapsulant filling at least a portion of the through hole.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: June 19, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young Gwan Ko, Sung Won Jeong
  • Patent number: 9977147
    Abstract: An optical module includes a carrier, a light-emitting component disposed over the carrier, an optical sensor disposed over the carrier, a housing, and a lens. The housing is disposed over the carrier and encircles the light-emitting component and the optical sensor. The housing defines a first accommodation space including a first aperture and a second aperture below the first aperture. The housing includes a first sidewall surrounding the first aperture, a second sidewall surrounding the second aperture, and a first support portion where a bottom end of the first sidewall and a top end of the second sidewall meet. The lens is located in the first aperture and is supported by the first support portion. One of the light-emitting component or the optical sensor is located in the first accommodation space.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 22, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ruei-Bin Ma, Ying-Chung Chen, Lu-Ming Lai
  • Patent number: 9932473
    Abstract: An encapsulating resin composition contains a thermosetting resin component, a curing accelerator, an inorganic filler, an ion trapping agent, and an aromatic monocarboxylic acid having one or more electron-withdrawing functional groups selected from a nitro group and a cyano group. The encapsulating resin composition is solid at 25° C., and has a sulfur content, measured by X-ray fluorescence analysis, of 0.1 mass % or less in terms of SO3.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: April 3, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Emi Iwatani, Kazuto Ogawa, Kota Ishikawa, Takayuki Tsuji
  • Patent number: 9917070
    Abstract: A method for arranging electronic components that includes a plurality of electronic components pasted onto a first front face of a carrier having a bonding layer. The front face and/or the electronic components being provided with a plurality of bonding points and the diameter of and distance between the bonding points are selected such that each of the plurality of electronic components is attached by at least three bonding points to the carrier having the bonding layer. The method also includes arranging at least one portion of the plurality of the components on a switching element carrier and connecting the components to the carrier. The method also includes detaching a component from the carrier having a bonding layer, using a solvent or a mechanical force that separates the carrier having a bonding layer and the switching element carrier from one another.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: March 13, 2018
    Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
    Inventors: Hans-Hermann Oppermann, Kai Zoschke, Lena Goullon
  • Patent number: 9911711
    Abstract: A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: March 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Christopher D. Muzzy, Wolfgang Sauter
  • Patent number: 9902875
    Abstract: A composition for forming a coating type BPSG film, containing one or more silicic acid skeletal structures represented by formula (1), one or more phosphoric acid skeletal structures represented by formula (2), one or more boric acid skeletal structures represented by formula (3), and one or more silicon skeletal structures represented by formula (4), wherein the composition contains a coupling between units in formula (4). The composition is capable of forming a BPSG film that has excellent adhesiveness in fine patterning, can be easily wet etched by a removing liquid which does not cause damage to a semiconductor substrate and a coating type organic film or a CVD film mainly consisting of carbon which is required in the patterning process, can maintain the peelability even after dry etching, and can suppress generation of particles by forming it in the coating process.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: February 27, 2018
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Seiichiro Tachibana, Yoshinori Taneda, Rie Kikuchi, Tsutomu Ogihara
  • Patent number: 9897796
    Abstract: This disclosure provides systems, methods and apparatus for displaying images. A display apparatus includes display elements formed on a transparent substrate. An elevated aperture layer (EAL) is fabricated over the display elements. An opposing substrate is coupled to the transparent substrate, with the display elements and the EAL positioned between the two substrates. To prevent the opposing substrate from coming into contact with the EAL and potentially damaging the EAL or the display elements, a spacer is built from the same materials used to form the display elements and the EAL. The spacer extends to a distance above the transparent substrate beyond upper surface of the EAL and encapsulates layers of polymer material used in creating a mold for the EAL.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: February 20, 2018
    Assignee: SnapTrack, Inc.
    Inventor: Teruo Sasagawa
  • Patent number: 9878401
    Abstract: Embodiments are directed to the formation micro-scale or millimeter scale structures or methods of making such structures wherein the structures are formed from at least one sheet structural material and may include additional sheet structural materials or deposited structural materials wherein all or a portion of the patterning of the structural materials occurs via laser cutting. In some embodiments, selective deposition is used to provide a portion of the patterning. In some embodiments the structural material or structural materials are bounded from below by a sacrificial bridging material (e.g. a metal) and possibly from above by a sacrificial capping material (e.g. a metal).
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: January 30, 2018
    Assignee: Microfabrica Inc.
    Inventors: Arun S. Veeramani, Heath A. Jensen, Uri Frodis, Christopher G. Wiita, Michael S. Lockard, Irina Boguslavsky, Pavel Lembrikov, Dennis R. Smalley, Richard T. Chen
  • Patent number: 9870947
    Abstract: Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate wafer. A collective flexible sheet made of a heat-conductive material comprising a layer containing pyrolytic graphite is fixed to extend over a collective region extending over the electronic chips and over the collective substrate wafer between the electronic chips. The collective flexible sheet is then compressed. A dicing operation is then carried out in order to obtain electronic devices each including an electronic chip, a portion of the collective plate and a portion of the collective flexible sheet.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: January 16, 2018
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Didier Campos, Benoit Besancon, Perceval Coudrain, Jean-Philippe Colonna
  • Patent number: 9859266
    Abstract: Presented herein is a package comprising a carrier device of a device stack and at least one top device of the device stack mounted on a first side of the carrier device. A lid is mounted on the first side of the carrier device, with a first portion of the lid attached to the carrier device and a second portion of the lid extending past and overhanging a respective edge of the carrier device. The lid comprises a recess disposed in a first side, and the at least one top device is disposed within the recess. A thermal interface material disposed on the top device and contacts a surface of the recess.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Ding Wang, Kim Hong Chen, Jung Wei Cheng, Chien Ling Hwang, Hsin-Yu Pan, Han-Ping Pu
  • Patent number: 9859255
    Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a package substrate, an electronic component, a mold compound encapsulating the electronic component, and a redistribution layer disposed such that the mold compound is between the package substrate and the redistribution layer. The redistribution layer and the package substrate can be electrically coupled. In addition, the redistribution layer and the electronic component can be electrically coupled to electrically couple the electronic component and the package substrate. Associated systems and methods are also disclosed.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventors: Jh Yoon, Yong She, Mao Guo, Richard Patten
  • Patent number: 9842803
    Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: December 12, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongmin Baek, Sangho Rha, Sanghoon Ahn, Wookyung You, Naein Lee
  • Patent number: 9837383
    Abstract: Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: December 5, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Jaspreet S. Gandhi, Wayne H. Huang, James M. Derderian
  • Patent number: 9822284
    Abstract: An adhesive film of the present invention includes a base material layer and a self-peeling adhesive layer laminated therein. The base material layer has a thermal contraction percentage in a direction of flow (thermal contraction percentage in an MD direction) and a thermal contraction percentage in an orthogonal direction with respect to the direction of flow (thermal contraction percentage in a TD direction) that satisfy the following conditions: (1) after heating at 150° C. for 30 minutes, 0.4?|thermal contraction percentage in MD direction/thermal contraction percentage in TD direction|?2.5 and average of thermal contraction percentage in MD direction and thermal contraction percentage in TD direction?2%, and (2) after heating at 200° C. for 10 minutes, 0.4?|thermal contraction percentage in MD direction/thermal contraction percentage in TD direction|?2.5 and average of thermal contraction percentage in MD direction and thermal contraction percentage in TD direction?3%.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: November 21, 2017
    Assignee: MITSUI CHEMICALS TOHCELLO, INC.
    Inventors: Shinichi Usugi, Kouji Igarashi, Akimitsu Morimoto
  • Patent number: 9825031
    Abstract: A method includes forming first and second contact openings in a first dielectric layer. At least the first contact opening is at least partially lined with a liner layer. A first conductive feature is formed in the first contact opening and a second conductive feature is formed in the second contact opening. A portion of the liner layer adjacent a top surface of the first dielectric layer is removed to define a recess. A barrier layer is formed above the first dielectric layer and in the recess. The barrier layer has a first dielectric constant greater than a second dielectric constant of the first dielectric layer. A second dielectric layer is formed above the barrier layer. A third conductive feature is formed embedded in the second dielectric layer and contacting the second conductive feature.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: November 21, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Guillaume Bouche, Andy C. Wei, Jason E. Stephens, David M. Permana, Jagannathan Vasudevan
  • Patent number: 9786629
    Abstract: Dual-side reinforcement (DSR) materials and methods for semiconductor fabrication. The DSR materials exhibit the properties of conventional underfill materials with enhanced stability at room temperature.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: October 10, 2017
    Inventors: Ramakrishna Hosur Venkatagiriyappa, Sutapa Mukherjee, Harish Hanchina Siddappa, Morgana De Avila Ribas, Siuli Sarkar, Bawa Singh, Rahul Raut
  • Patent number: 9773823
    Abstract: A display device and a method of manufacturing the display device are disclosed. In one aspect, the method includes forming a sacrificial layer over a carrier substrate, forming a passivation barrier layer to cover upper and lateral sides of the sacrificial layer and forming a thin film transistor layer over the passivation barrier layer. The method also includes placing a mask over the thin film transistor layer so as to expose an edge portion of the passivation barrier layer, wherein the edge portion does not overlap the mask in the depth dimension of the display device. The method further includes removing the edge portion of the passivation barrier layer so as to form a barrier layer and separating the carrier substrate from the barrier layer via the sacrificial layer.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: September 26, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Su-Hyoung Kang, Gwang Min Cha, Chang Oh Jeong
  • Patent number: 9773684
    Abstract: A method of manufacturing a fan out wafer level package comprises: preparing conductive projections on an upper surface of a chip; mounting the chip on a carrier with the upper surface of the chip facing upwards; plastic packaging the chip to form a plastic packaging body with tops of the conductive projections being disposed outside the plastic package body; and implementing a redistribution line processing on the plastic package body. With this method, chips can be made small and thin and the manufacturing processes can be simplified.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: September 26, 2017
    Assignee: National Center for Advanced Packaging Co., Ltd.
    Inventors: Hongjie Wang, Yibo Liu, Feng Chen, Dongkai Shangguan, Peng Sun
  • Patent number: 9748133
    Abstract: A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is grown over the metal pattern layer and the first dielectric layer. A metal trench is formed with a metal width in the first dielectric layer. A via hole is formed with a via width in the second dielectric layer.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9690440
    Abstract: A touch screen panel is provided. The touch screen panel includes an Indium Tin Oxide (ITO) sensor glass layer, a window glass layer mounted above the ITO sensor glass layer by means of an Optical Clear Adhesive (OCA), a conductive layer disposed between a surface of the window glass layer and a surface of the ITO sensor glass layer that includes an electrode pattern, and a touch screen control unit mounted on one of the window glass layer surface and the ITO sensor glass layer surface on which the conductive layer is mounted.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: June 27, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Heon-Seok Lee
  • Patent number: 9688453
    Abstract: A hermetically sealed package effectively dissipates heat generated inside the package. The hermetically sealed package includes a hermetically sealed enclosure formed from a base portion and a lid. Within the enclosure two or more heat generating elements, such as integrated circuit chips, are supported by the base portion and rise to different heights from the base portion. At least one resilient heat exchange component, such as a leaf spring, extends from the lid of the hermetically sealed enclosure to the different heights. The heat exchange component is configured to conduct heat from the plurality of heat generating elements to the lid of the enclosure.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: June 27, 2017
    Assignee: Cisco Technology, Inc.
    Inventors: Jovica Savic, Mudasir Ahmad, Thomas Brenner
  • Patent number: 9672830
    Abstract: A voice signal encoding and decoding method, device, and codec system are provided. The coding method includes: encoding an input voice signal to obtain a broadband code stream, where the broadband code stream includes a core layer bit stream and an extension enhancement layer bit stream (101); compressing the core layer bit stream to obtain a compressed code stream (102); and packing the compressed code stream and the extension enhancement layer bit stream to obtain a packed code stream (103). The core layer bit stream is compressed, and the compressed code stream and the extension enhancement layer bit stream are packed, thereby reducing transmission bandwidth occupied by the input voice signal. Since the broadband voice encoding is performed on the input voice signal, a broadband voice code stream is transmitted by using narrowband transmission bandwidth, thereby improving the cost performance of voice signal transmission.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: June 6, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Fengyan Qi, Lei Miao
  • Patent number: 9644057
    Abstract: An alkoxysilane containing reactive organic functional groups is prepared as one of raw materials. The reactive organic functional groups are caused to react to bond with each other in advance so as to form an oligomer. The oligomer is swollen in an alkoxysilane of an identical or different kind, so that a sol solution is prepared and the sol solution is cured through a sol-gel reaction.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: May 9, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kei Toyota, Kazuma Oikawa
  • Patent number: 9648750
    Abstract: A flexible circuit board includes an electrically insulating top sheet and an electrically insulating bottom sheet. A plurality of conductive traces is positioned between the electrically insulating top and bottom sheets. A first conductive trace has a first contact pad, and a second conductive trace has a second contact pad. The first and second contact pads are exposed through at least one opening in the electrically insulating top sheet, and each of the first and second contact pads are configured to be connected to an LED. A third contact pad is exposed through openings in the electrically insulating top and bottom sheets, with a top surface of the third contact pad configured to be connected to the LED and a bottom surface of the third contact pad configured to be connected to a heat diffusion device.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: May 9, 2017
    Assignee: RSM Electron Power, Inc.
    Inventor: Ching Au
  • Patent number: 9640420
    Abstract: A method of processing a wafer includes coating the front side of the wafer with a water-soluble liquid resin to form a thin film; fixing the wafer to a protective plate for protecting the front side of the wafer, with a bond material interposed between the protective plate and the thin film; holding by a chuck table the protective plate with the wafer fixed thereto and grinding the back side of the wafer to make the wafer have a predetermined thickness; releasing step of releasing the bond material together with the protective plate to which the wafer has been fixed; and supplying water to the bond material remaining on the front side of the wafer to remove the thin film together with the bond material.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: May 2, 2017
    Assignee: DISCO CORPORATION
    Inventor: Masaru Nakamura
  • Patent number: 9627350
    Abstract: A method for manufacturing a semiconductor device according to the present invention includes: (a) disposing, on a substrate (insulating substrate), a bonding material having a sheet shape and having sinterability; (b) disposing a semiconductor element on the bonding material after the (a); and (c) sintering the bonding material while applying pressure to the bonding material between the substrate and the semiconductor element. The bonding material includes particles of Ag or Cu, and the particles are coated with an organic film.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: April 18, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasunari Hino, Daisuke Kawabata
  • Patent number: 9627358
    Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: April 18, 2017
    Assignee: Intel Corporation
    Inventor: Junfeng Zhao
  • Patent number: 9627281
    Abstract: A method of manufacturing is provided that includes applying a thermal interface tape to a side of a semiconductor wafer that includes at least one semiconductor chip. The thermal interface material tape is positioned on the at least one semiconductor chip. The at least one semiconductor chip is singulated from the semiconductor wafer with at least a portion of the thermal interface tape still attached to the semiconductor chip.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: April 18, 2017
    Assignees: Advanced Micro Device, Inc., ATI Technologies ULC
    Inventors: Seth Prejean, Dales Kent, Ronnie Brandon, Gamal Refai-Ahmed, Michael Z. Su, Michael Bienek, Joseph Siegel, Bryan Black
  • Patent number: 9589934
    Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: March 7, 2017
    Assignee: Intel Corporation
    Inventor: Junfeng Zhao
  • Patent number: 9576177
    Abstract: A fingerprint sensing device (and associated method of manufacturing) comprises a sensing chip arranged on a substrate with readout circuitry. The sensing chip comprising a plurality of sensing elements having a surface defining a sensing plane, each sensing element being configured to provide a signal indicative of an electromagnetic coupling between a sensing element and a finger placed on the sensing device; bond wires arranged between bond pads located on the sensing chip on the substrate, respectively, to electrically connect the sensing chip to the readout circuitry. A portion of the bond wire protrudes above the chip and an adhesive is arranged on the sensing chip to covering to cover the chip so that the portion of the bond wire protruding above the chip is embedded in the adhesive. A protective plate is attached to the sensing chip by the adhesive and forms an exterior surface of the device.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: February 21, 2017
    Assignee: FINGERPRINT CARDS AB
    Inventor: Karl Lundahl
  • Patent number: 9543272
    Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: January 10, 2017
    Assignee: Intel Corporation
    Inventor: Junfeng Zhao
  • Patent number: 9530762
    Abstract: According to an exemplary embodiment, a semiconductor package is provided. The A semiconductor package includes at least one chip, and at least one component adjacent to the at least one chip, wherein the at least one chip and the at least one component are molded in a same molding body.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Tsai-Tsung Tsai, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 9520333
    Abstract: A semiconductor device includes a semiconductor device includes an interposer having a first side and a second side opposite to the first side, wherein the interposer comprises a redistribution layer (RDL), and the RDL comprises a first passivation layer on the first side and a second passivation layer on the second side; at least one active chip mounted on the first passivation layer on the first side through a plurality of first bumps penetrating through the first passivation layer; a molding compound disposed on the first side, the molding compound covering the at least one active chip and a top surface of the first passivation layer; and a plurality of solder bumps mounted on the first passivation layer on the second side.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: December 13, 2016
    Assignee: INOTERA MEMORIES, INC.
    Inventors: Shing-Yih Shih, Neng-Tai Shih, Hsu Chiang