Including Adhesive Bonding Step Patents (Class 438/118)
  • Patent number: 11031374
    Abstract: Some embodiments include a method in which a first semiconductor wafer and a second semiconductor wafer are bonded with each other. The first semiconductor wafer includes a memory cell array, and the second semiconductor wafer includes a circuit to access the memory cell array. After the bonding, contacts are formed to be associated with the first semiconductor wafer. The contacts are for electrical connections between the first and second semiconductor wafers. The contacts are linked with reference positions, with each of the contacts being linked with an associated one of the reference positions. Each of the contacts is shifted from its associated one of the reference positions to absorb a bonding alignment error between the first and second semiconductor wafers.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Mitsunari Sukekawa
  • Patent number: 11006832
    Abstract: A wireless sensor device capable of constant operation without replacement of batteries. The wireless sensor device is equipped with a rechargeable battery and the battery is recharged wirelessly. Radio waves received at an antenna circuit are converted into electrical energy and stored in the battery. A sensor circuit operates with the electrical energy stored in the battery, and acquires information. Then, a signal containing the information acquired is converted into radio waves at the antenna circuit, whereby the information can be read out wirelessly.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: May 18, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Jun Koyama
  • Patent number: 10971457
    Abstract: A semiconductor device is disclosed. In one example, the semiconductor device comprises a first semiconductor die comprising a first surface, a second surface opposite to the first surface, and a contact pad disposed on the first surface, a further contact pad spaced apart from the semiconductor die, a clip comprising a first layer of a first metallic material and a second layer of a second metallic material different from the first metallic material, wherein the first layer of the clip is connected with the contact pad, and the second layer of the clip is connected with the further contact pad.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: April 6, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Bemmerl, Martin Gruber, Thorsten Scharf
  • Patent number: 10947330
    Abstract: A method for encapsulating a catalyst in a dispersed polymer particle comprising dissolving a Group 8 to Group 11 transition metal containing catalyst and a self-dispersing polymer in a solvent; adding water and optionally a base under particle forming conditions to form a dispersed polymer encapsulated catalyst comprising particles having a population number average diameter between 10 and 300 nanometers is provided.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: March 16, 2021
    Assignees: ROHM AND HAAS COMPANY, THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS
    Inventors: Damien Guironnet, Muhammad Rabnawaz, Ralph Even, Andrew Hughes, Joshua Katz
  • Patent number: 10943846
    Abstract: A chip package structure includes a circuit structure, a redistribution structure, a heat conductive component, a chip, and a heat sink. The circuit structure includes a first circuit layer. The redistribution structure is disposed on the circuit structure and includes a second circuit layer, wherein the redistribution structure has an opening. The heat conductive component is disposed on the circuit structure and covered by the redistribution structure. The heat conductive component has a horizontal portion and a vertical portion. The horizontal portion extends toward the opening until it exceeds the opening. The vertical portion extends upward beyond the top surface of the redistribution structure from a part of the horizontal portion. The chip is disposed in the opening, and the bottom of the chip contacts the heat conductive component. The heat sink is disposed over the redistribution structure and the chip.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: March 9, 2021
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Tzu-Hsuan Wang, Chien-Chen Lin, Kuan-Wen Fong
  • Patent number: 10919758
    Abstract: A physical quantity sensor includes a substrate, an acceleration sensor mounted on the substrate, an integrated circuit mounted on the substrate and stacked with the acceleration sensor, and serial communication wirings provided to the substrate. In a plan view of the acceleration sensor element, a bonding wire connecting the acceleration sensor element to the integrated circuit is disposed on an opposite side to the serial communication wirings with respect to a virtual central line of the acceleration sensor element.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: February 16, 2021
    Inventor: Yoshinao Yanagisawa
  • Patent number: 10925163
    Abstract: A printed circuit board includes an insulating layer including a cavity including a groove structure formed on one surface of the insulating layer, a circuit pattern including a first pad formed on a bottom surface of the cavity and a second pad formed inside the insulating layer, a first metal layer embedded in a side surface of the cavity, the first metal layer being in contact with the bottom surface of the cavity and being formed along the boundary of the cavity, and a second metal layer formed on the second pad and having a stepped structure formed with the second pad.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: February 16, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Je Sang Park, Sang Ho Jeong
  • Patent number: 10916450
    Abstract: A method includes forming a release film over a carrier, forming a metal post on the release film, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, decomposing a first portion of the release film to separate a second portion of the release film from the carrier, and forming an opening in the release film to expose the metal post.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: February 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Pu Wang, Szu-Wei Lu, Ying-Ching Shih, Jing-Cheng Lin
  • Patent number: 10861814
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a bump structure, a polymer layer and a metal layer. The bump structure includes a metal pad and a bump electrically connected to the metal pad. The polymer layer extends laterally from a sidewall of the bump. The metal layer is over the bump structure and in physical contact with a side surface of the metal pad.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzung-Hui Lee, Chen-Hua Yu, Chi-Ming Tsai, Hung-Jui Kuo, Ming-Che Ho
  • Patent number: 10859598
    Abstract: A method for electrically connecting a test and measurement instrument to a via of a printed circuit board, PCB, the method comprising: dispensing a UV-curable conductive adhesive into a back-drilled hole formed in the PCB, the back-drilled hole extending to the via, such that the dispensed adhesive contacts the via; curing the dispensed adhesive by applying a UV light source to the dispensed adhesive; and connecting a test and measurement instrument to the cured adhesive using a conductive member.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: December 8, 2020
    Assignee: Tektronix, Inc.
    Inventors: Julie A. Campbell, Karl A. Rinder, Daniel G. Knierim
  • Patent number: 10859915
    Abstract: A method is provided including forming a first layer over a substrate and forming an adhesion layer over the first layer. The adhesion layer has a composition including an epoxy group. A photoresist layer is formed directly on the adhesion layer. A portion of the photoresist layer is exposed to a radiation source. The composition of the adhesion layer and the exposed portion of the photoresist layer cross-link using the epoxy group. Thee photoresist layer is then developed (e.g., by a negative tone developer) to form a photoresist pattern feature, which may overlie the formed cross-linked region.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Yu Liu, Tzu-Yang Lin, Ya-Ching Chang, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10832935
    Abstract: An exemplary wafer structure comprises a source wafer having a patterned sacrificial layer defining anchor portions separating sacrificial portions. A patterned device layer is disposed on or over the patterned sacrificial layer, forming a device anchor on each of the anchor portions. One or more devices are disposed in the patterned device layer, each device disposed entirely over a corresponding one of the one or more sacrificial portions and spatially separated from the one or more device anchors. A tether structure connects each device to a device anchor. The tether structure comprises a tether device portion disposed on or over the device, a tether anchor portion disposed on or over the device anchor, and a tether connecting the tether device portion to the tether anchor portion. The tether is disposed at least partly in the patterned device layer between the device and the device anchor.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: November 10, 2020
    Assignee: X Display Company Technology Limited
    Inventors: Christopher Andrew Bower, Matthew Meitl, Salvatore Bonafede, Brook Raymond, Carl Ray Prevatte, Jr.
  • Patent number: 10830544
    Abstract: A self-healing metal structure is provided for transferring heat between an electronics component and a substrate. The self-healing metal structure includes a base metal structural component. A phase change material is provided adjacent at least a portion of the base metal structural component. A protective component at least partially encapsulates the phase change material. Upon the presence of a spatial defect in the base metal structural component, the phase change material reacts with the base structural component to form an intermetallic compound to at least partially occupy the spatial defect. The phase change material at least partially encapsulated with the protective component may be disposed within the base metal structural component as a plurality of separate capsules incorporated therein, or the phase change material at least partially surrounds the base metal structural component.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: November 10, 2020
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Shailesh N. Joshi, Naoya Take
  • Patent number: 10825484
    Abstract: A method of forming an integrated assembly includes providing a construction having laterally-spaced digit-line-contact-regions and having intervening regions between the laterally-spaced digit-line-contact-regions; forming an expanse of non-conductive-semiconductor-material which extends across the digit-line-contact-regions and the intervening regions; a lower surface of the non-conductive-semiconductor-material being vertically-spaced from upper surfaces of the digit-line-contact-regions; forming openings extending through the non-conductive-semiconductor-material to the digit-line-contact-regions; forming conductive-semiconductor-material-interconnects within the openings and coupled with the digit-line-contact-regions, upper surfaces of the conductive-semiconductor-material-interconnects being beneath the lower surface of the non-conductive-semiconductor-material; and forming metal-containing-digit-lines over the non-conductive-semiconductor-material.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Chandra Pandey, Si-Woo Lee
  • Patent number: 10772213
    Abstract: An adhesive substrate is disclosed, which includes a base substrate and a heat-resistant elastomer layer formed on the base substrate, wherein the base substrate is flexible and has a thickness of 0.2 mm or more and 2 mm or less, wherein the adhesive substrate is used as part of a method for physically separating an object that has been held immovable in such a manner that the object has been adhered to by the heat-resistant elastomer layer and the object is anchored from the upper side, and wherein by starting to physically separate the end portion of the adhesive substrate downward the object is able to be separated.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: September 8, 2020
    Assignee: Shin-Etsu Polymer Co., Ltd.
    Inventors: Yuji Irisawa, Toshiaki Hatsumi
  • Patent number: 10763185
    Abstract: Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Matt E. Schwab, J. Michael Brooks, David J. Corisis
  • Patent number: 10748855
    Abstract: A method of fabricating a semiconductor package using a laminating device is provided. The method includes placing a substrate on a substrate stand; providing a pressurizing unit which is expandable and includes a convex surface facing an upper surface of the substrate stand, on the substrate stand; injecting air into the pressurizing unit using a plate which is connected to the pressurizing unit; and supplying a film by a film supply unit which supplies the film between the substrate stand and the pressurizing unit, wherein the pressurizing unit attaches the film onto the substrate, while expanding.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tea-Geon Kim, Jung Lae Jung
  • Patent number: 10739209
    Abstract: Carbon nanotube-based multi-sensors for packaging applications and methods to form the carbon nanotube-based multi-sensors are capable of simultaneously measuring at least two measurands including temperature, strain, and humidity via changes in its electrical properties.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric Duchesne, Dominique Drouin, Hélène Frémont, Simon Landry, Aurore F. M. E. Quelennec, Umar Shafique, Patrick R. J. Wilson
  • Patent number: 10700008
    Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a RDL structure, an encapsulant and a conductive terminal. The die is on a redistribution layer (RDL) structure. The RDL structure comprises a polymer layer and a RDL in the polymer layer. The encapsulant is on the RDL structure and laterally aside the die. The encapsulant comprises a body part and an extending part underlying the body part. The conductive terminal is electrically connected to the RDL structure and the die. The body part of the encapsulant encapsulates sidewalls of the die. The extending part of the encapsulant extends into the polymer layer.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Chang, Hao-Yi Tsai, Tsung-Hsien Chiang, Tin-Hao Kuo
  • Patent number: 10679897
    Abstract: Disclosed herein is a device wafer processing method including a protective film forming step of applying a water-soluble protective film material to the front side of a device wafer having devices separated by division lines and next exposing the division lines to form a protective film for protecting each device, an application time recording step of recording the time at which the water-soluble protective film material is applied to the device wafer, a determining step of determining whether or not a predetermined duration has elapsed from the time recorded in the application time recording step, an etching step of dry-etching the device wafer along the division lines after performing the determining step, and a protective film removing step of supplying a cleaning water to the protective film to thereby remove the protective film after performing the etching step. Only when it is determined in the determining step that the predetermined duration has not elapsed, the etching step is performed.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: June 9, 2020
    Assignee: DISCO CORPORATION
    Inventors: Koichi Shigematsu, Satoshi Kumazawa
  • Patent number: 10622237
    Abstract: A conveying mechanism for conveying a wafer unit having a wafer disposed inside of and supported on an annular frame by a holding tape includes a housing tray housing the wafer unit therein and a transport unit supporting and transporting the housing tray between wafer treating apparatus. The housing tray includes a ceiling plate and a bottom plate that are interconnected by a pair of side walls facing each other across an opening defined in a side through which the wafer unit can be taken into and out of the housing tray. An air flow generator is disposed on the ceiling plate for generating air downflows in the housing tray that are directed from the ceiling plate into the opening. The transport unit conveys wafer units, one by one, between the wafer treating apparatus.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: April 14, 2020
    Assignee: DISCO CORPORATION
    Inventors: Kazunari Tanaka, Satoshi Ohkawara
  • Patent number: 10600760
    Abstract: Capacitive coupling of integrated circuit die components and other conductive areas is provided. Each component to be coupled has a surface that includes at least one conductive area, such as a metal pad or plate. An ultrathin layer of dielectric is formed on at least one surface to be coupled. When the two components, e.g., one from each die, are permanently contacted together, the ultrathin layer of dielectric remains between the two surfaces, forming a capacitor or capacitive interface between the conductive areas of each respective component. The ultrathin layer of dielectric may be composed of multiple layers of various dielectrics, but in one implementation, the overall thickness is less than approximately 50 nanometers. The capacitance per unit area of the capacitive interface formed depends on the particular dielectric constants ? of the dielectric materials employed in the ultrathin layer and their respective thicknesses.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: March 24, 2020
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Arkalgud R. Sitaram
  • Patent number: 10595424
    Abstract: This hermetic sealing lid member (10) is made of a clad material (20) including a silver brazing layer (21) that contains Ag and Cu and a first Fe layer (22) bonded onto the silver brazing layer and made of Fe or an Fe alloy. The hermetic sealing lid member is formed in a box shape including a recess portion (13) by bending the clad material.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: March 17, 2020
    Assignee: HITACHI METALS, LTD.
    Inventors: Masayuki Yokota, Masaharu Yamamoto
  • Patent number: 10580756
    Abstract: Wirebond bondpads on semiconductor packages that result in reduced cross-talk and/or interference between vertical wires are disclosed. The vertical wirebonds may be disposed in the semiconductor package with stacked dies, where the wires are substantially normal to the bondpads to which the vertical wirebonds are attached on the dies. The wirebond bondpads may include signal pads that carry input/output (I/O) to/from the die package, as well as ground bondpads. The bondpads may have widths that are greater than the space between adjacent bondpads. Bondpads may be fabricated to be larger than the size requirements for reliable wirebond formation on the bondpads. For a fixed pitch bondpad configuration, the size of the signal bondpads adjacent to the ground bondpads may be greater than half of the pitch. By increasing the size of the signal bondpads adjacent to a ground line relative to the space therebetween, improved cross-talk performance may be achieved.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventor: Hungying L. Lo
  • Patent number: 10566949
    Abstract: A transducer includes first and second piezoelectric layers made of corresponding different first and second piezoelectric materials and three or more electrodes, implemented in two or more conductive electrode layers. The first piezoelectric layer is sandwiched between a first pair of electrodes and the second piezoelectric layer is sandwiched between a second pair of electrodes. The first and second pairs of electrodes contain no more than one electrode that is common to both pairs.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: February 18, 2020
    Assignee: CHIRP MICROSYSTEMS, INC.
    Inventors: Stefon Shelton, Andre Guedes, Richard Przybyla, Meng-Hsiung Kiang, David Horsley
  • Patent number: 10551194
    Abstract: A sensor unit with high reliability and stable detection accuracy against vibrations of an installation target object is to be provided. A sensor unit includes: a sensor module configured including a substrate with inertial sensors mounted thereon, and an inner case in which the substrate is installed; and an outer case accommodating the sensor module. A recessed part is formed in the inner case. The inertial sensors are arranged in an area overlapping with the recessed part as viewed in a plan view seen from the direction of thickness of the substrate, and a filling member is provided to fill a space formed by the substrate and the recessed part. The sensor module is joined to a bottom wall of the outer case via a joining member.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: February 4, 2020
    Assignee: Seiko Epson Corporation
    Inventors: Yusuke Kinoshita, Masayasu Sakuma
  • Patent number: 10535378
    Abstract: Some embodiments include an integrated assembly which has digit-line-contact-regions laterally spaced from one another by intervening regions. Non-conductive-semiconductor-material is over the intervening regions. Openings extend through the non-conductive-semiconductor-material to the digit-line-contact-regions. Conductive-semiconductor-material-interconnects are within the openings and are coupled with the digit-line-contact-regions. Upper surfaces of the conductive-semiconductor-material-interconnects are beneath a lower surface of the non-conductive-semiconductor-material. Metal-containing-digit-lines are over the non-conductive-semiconductor-material. Conductive regions extend downwardly from the metal-containing-digit-lines to couple with the conductive-semiconductor-material-interconnects. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: January 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Chandra Pandey, Si-Woo Lee
  • Patent number: 10522433
    Abstract: A package which comprises a chip carrier made of a first material, a body made of a second material differing from the first material and being arranged on the chip carrier so as to form a cavity, a semiconductor chip arranged at least partially in the cavity, and a laminate encapsulating at least one of at least part of the chip carrier, at least part of the body and at least part of the semiconductor chip.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: December 31, 2019
    Assignee: Infineon Technologies AG
    Inventors: Juergen Hoegerl, Horst Theuss, Gottfried Beer
  • Patent number: 10522500
    Abstract: The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: December 31, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Min Lo, Chee-Key Chung, Chang-Fu Lin, Kuo-Hua Yu, Hsiang-Hua Huang
  • Patent number: 10510626
    Abstract: In one embodiment, a wafer includes a number of die areas each including a semiconductor device and dedicated to become a separate die. The die areas are disposed on a first face of the wafer and wherein adjacent die areas are distanced from one another. A first trench and a second trench are formed on the first face between adjacent die areas. The first trench and the second trench are spaced apart from one another by a ridge. A third trench is disposed above the ridge on a second face of the wafer.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: December 17, 2019
    Assignee: Infineon Technologies AG
    Inventors: Michaela Braun, Markus Menath
  • Patent number: 10510629
    Abstract: A package and a method of forming the same are provided. The package includes: a die stack bonded to a carrier, the die stack including a first integrated circuit die, the first integrated circuit die being a farthest integrated circuit die of the die stack from the carrier, a front side of the first integrated circuit die facing the carrier; a die structure bonded to the die stack, the die structure including a second integrated circuit die, a backside of the first integrated circuit die being in physical contact with a backside of the second integrated circuit die, the backside of the first integrated circuit die being opposite the front side of the first integrated circuit die; a heat dissipation structure bonded to the die structure adjacent the die stack; and an encapsulant extending along sidewalls of the die stack and sidewalls of the heat dissipation structure.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Chen-Hua Yu
  • Patent number: 10505071
    Abstract: A method of manufacturing a light emitting device includes placing a light emitting element in a first recess; covering with a first cover member the second to fourth element lateral faces of the light emitting element exposed in the first recess; extracting from the first recess the light emitting element equipped with the first cover member; placing the light emitting element in the second recess by bringing the first element lateral face of the light emitting element extracted from the first recess into contact with the second recess first inner lateral face of the second recess and spacing the substrate face of the light emitting element apart from the second recess bottom face of the second recess; covering the substrate face with a second cover member in the second recess; and extracting from the second recess the light emitting element equipped with the second cover member formed thereon.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: December 10, 2019
    Assignee: NICHIA CORPORATION
    Inventor: Shigeki Sajiki
  • Patent number: 10460991
    Abstract: Disclosed herein is a resin package substrate processing method for processing a resin package substrate including a mold resin in which a filler is mixed. The resin package substrate processing method includes a fixing step of fixing the resin package substrate through an adhesive tape to an annular frame, a dividing step of applying a laser beam having an absorption wavelength to the mold resin of the resin package substrate, to the mold resin to thereby form a plurality of division grooves dividing the resin package substrate into a plurality of package device chips, an interchip distance increasing step of expanding the adhesive tape to thereby increase the distance between any adjacent ones of the plural package device chips of the resin package substrate, and a cleaning step of supplying a cleaning liquid to the resin package substrate to thereby remove the filler caught between the adjacent package device chips.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: October 29, 2019
    Assignee: DISCO CORPORATION
    Inventor: Yuri Ban
  • Patent number: 10361068
    Abstract: A method of forming a feature in a void, the method including filling the void having at least one sloped wall with a polymeric material; forming a layer of photoresist over the polymeric material; forming a gap in the layer of photoresist; and etching the polymeric material exposed by the gap in the layer of photoresist to form a feature.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: July 23, 2019
    Assignee: Seagate Technology LLC
    Inventors: Sridhar Dubbaka, Sriram Viswanathan, Christina Hutchinson
  • Patent number: 10347508
    Abstract: A method includes applying a die attach material to a die pad of an integrated circuit. The die attach material is employed as a bonding material to the die pad. The method includes mounting an integrated circuit die to the die pad of the integrated circuit via the die attach material. The method includes printing an adhesion deposition material on the die attach material appearing at the interface of the integrated circuit die and the die pad of the integrated circuit to mitigate delamination between the integrated circuit die and the die pad.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: July 9, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yong Lin, Rongwei Zhang, Benjamin Stassen Cook, Abram Castro
  • Patent number: 10334725
    Abstract: A system for assembling electronic circuits on an electrically non-conductive surface or substrate. The system incorporates electronic components integrated into electronic component modules. The electronic component modules include identification markings on the top surfaces and electronic contact pads on the bottom surfaces. Electrical interconnects between discrete electronic component modules is achieved through the use of electrically conductive traces placed on the substrate surface. The bottom surfaces of the electronic component modules are coated with an adhesive so the electronic component modules can be mounted onto the substrate. The electronic component modules are affixed to the substrate such that the electronic component modules contact pads make electrical contact with the appropriate electrically conductive traces.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: June 25, 2019
    Inventor: Richard A. Marasas, Jr.
  • Patent number: 10297485
    Abstract: A semiconductor device is provided comprising a support, an adhesive resin layer, an insulating layer, a redistribution layer, a chip layer, and a mold resin layer. The adhesive resin layer consists of a resin layer (A) comprising a photo-decomposable resin containing a fused ring in its main chain and a resin layer (B) comprising a non-silicone base thermoplastic resin and having a storage elastic modulus E? of 1-500 MPa at 25° C. and a tensile break strength of 5-50 MPa. The semiconductor device is easy to fabricate and has thermal process resistance, the support is easily separated, and a semiconductor package is efficiently produced.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: May 21, 2019
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Hiroyuki Yasuda, Michihiro Sugo, Hideto Kato, Kazunori Kondo
  • Patent number: 10217686
    Abstract: The present disclosure relates to an air-cavity package, which includes a bottom substrate, a top substrate, a perimeter wall, a bottom electronic component, a top electronic component, and an external electronic component. The perimeter wall extends from a periphery of a lower side of the top substrate to a periphery of an upper side of the bottom substrate to form a cavity. The bottom electronic component is mounted on the upper side of the bottom substrate and exposed to the cavity. The top electronic component is mounted on the lower side of the top substrate and exposed to the cavity. And the external electronic component is mounted on an upper side of the top substrate, which is opposite the lower side of the top substrate and not exposed to the cavity.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: February 26, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Walid M. Meliane, Kevin J. Anderson, Tarak A. Railkar
  • Patent number: 10209478
    Abstract: A filter unit that is used by being detachably mounted on a lens barrel constituting an imaging device is configured so as to include a discoidal filter body, an annular filter frame that receives the filter body, an adhesion film that is formed between the filter frame and the filter body and that is formed of an elastic adhesion, and a decorative annular frame received at a portion that is inside the filter frame and that is, when mounted on the lens barrel, on the imaging object side with respect to the filter body. The filter body and the filter frame are in noncontact with each other by forming the adhesion film between the filter frame and the filter body, and by disposing the decorative annular frame, the adhesion film is hidden under the appearance of the filter unit when the filter unit is mounted on the lens barrel.
    Type: Grant
    Filed: September 7, 2015
    Date of Patent: February 19, 2019
    Assignee: Kenko Tokina Co., Ltd.
    Inventor: Eiji Okado
  • Patent number: 10186458
    Abstract: A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: January 22, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Karl Mayer, Evelyn Napetschnig, Michael Pinczolits, Michael Sternad, Michael Roesner
  • Patent number: 10186503
    Abstract: The module is implemented on a circuit board, the module including a wiring board; an electronic component implemented on a first surface of the wiring board; an external connection electrode formed on a second surface of the wiring board; a solder bump connected to the external connection electrode; a bare chip implemented facedown on the second surface of the wiring board; and a resin covering a surface and a side surface of the bare chip and a side surface of the solder bump on the second surface of the wiring board, wherein a reverse surface of the bare chip and a connection surface of the solder bump are exposed from the resin such that the reverse surface of the bare chip and the connection surface of the solder bump are on a same plane, and wherein the module is implemented on the circuit board so that the reverse surface of the bare chip and the connection surface of the solder bump face the circuit board.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: January 22, 2019
    Assignee: MITSUMI ELECTRIC CO., LTD.
    Inventors: Makoto Kitazume, Toshiki Komiyama
  • Patent number: 10170299
    Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.
    Type: Grant
    Filed: June 18, 2016
    Date of Patent: January 1, 2019
    Assignee: Applied Materials, Inc.
    Inventors: He Ren, Mehul B. Naik, Yong Cao, Yana Cheng, Weifeng Ye
  • Patent number: 10131826
    Abstract: An adhesive film for a semiconductor chip with a through electrode, which is used for stacking multiple semiconductor chips each with a through electrode on a semiconductor wafer, which can favorably connect the through electrodes while suppressing formation of voids, and which can reduce the length of burrs protruding around the semiconductor chips. An adhesive film for a semiconductor chip with a through electrode, to be used for stacking multiple semiconductor chips each with a through electrode on a semiconductor wafer, the adhesive film having a minimum melt viscosity of 50 to 2500 Pa·s and a thixotropic index at 140° C. of 8 or lower.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: November 20, 2018
    Assignee: SEKISUI CHEMICAL CO., LTD.
    Inventors: Mai Nagata, Kohei Takeda, Toshio Enami
  • Patent number: 10103298
    Abstract: A light emitting diode (LED) module which includes: a substrate; a resist including a plurality of layers above the substrate; and an LED element mounted above the substrate. The plurality of layers includes a second layer that is an uppermost layer and a first layer that is an underlying layer. The second layer that is the uppermost layer includes fluorine as a component.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: October 16, 2018
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Naoki Tagami, Masumi Abe, Hisaki Fujitani, Kosuke Takehara, Toshiaki Kurachi
  • Patent number: 10090177
    Abstract: Systems and methods for releasing semiconductor dies during pick and place operations are disclosed. In one embodiment, a system for handling semiconductor dies comprises a support member positioned to carry at least one semiconductor die releasably attached to a support substrate. The system further includes a picking device having a pick head coupleable to a vacuum source and positioned to releasably attach to the semiconductor die at a pick station. The system still further includes a cooling member coupleable to a cold fluid source and configured to direct a cold fluid supplied by the cold fluid source toward the support substrate at the pick station. The cold fluid cools a die attach region of the substrate where the semiconductor die is attached to the substrate to facilitate removal of the semiconductor die.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: October 2, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jeremy E. Minnich, Benjamin L. McClain, Travis M. Jensen
  • Patent number: 10079175
    Abstract: Insulating a via in a semiconductor substrate, including: depositing, in the via, a dielectric layer; depositing, in the via, a barrier layer; allowing the barrier layer to oxidize; and depositing, in the via, a conducting layer.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Jennifer A. Oakley, Kevin S. Petrarca, Nicole R. Reardon, Andrew H. Simon
  • Patent number: 10068853
    Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an active surface, a plurality of sidewalls connected to the active surface, and a plurality of pads distributed on the active surface. The insulating encapsulation encapsulates the active surface and the sidewalls of the integrated circuit. The insulating encapsulation includes a plurality of first contact openings and a plurality of through holes, and the pads are exposed by the first contact openings. The redistribution circuit structure includes a redistribution conductive layer, wherein the redistribution conductive layer is disposed on the insulating encapsulation and is distributed in the first contact openings and the through holes. The redistribution conductive layer is electrically connected to the pads through the first contact openings. A method of fabricating the integrated fan-out package is also provided.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: September 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hsiang Hu, Hung-Jui Kuo, Yi-Wen Wu
  • Patent number: 10049985
    Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a dielectric layer and providing electrical connection to source/drain epitaxial regions surrounding a set of fins, the contact line including: a first portion of the contact line electrically isolated from a second portion of the contact line by a contact line spacer, wherein the first portion and the second portion each include a liner layer and a metal, the liner layer separating the metal from the dielectric layer and the source/drain epitaxial regions, and wherein the metal is directly in contact with the contact line spacer.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: August 14, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Veeraraghavan S. Basker, Keith H. Tabakman, Patrick D. Carpenter, Guillaume Bouche, Michael V. Aquilino
  • Patent number: 10014537
    Abstract: The present disclosure is directed to a method and system for dynamically controlling seal decompression. The method includes monitoring a set of parameters associated with an operation of a seal, wherein the set of parameters includes a maximum pressure subjected to the seal and an exposure time at the maximum pressure, calculating a target pressure ramp down rate based on at least one of the maximum pressure and the exposure time, and decreasing a pressure about the seal at a decompression rate that is based on the target pressure ramp down rate.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: July 3, 2018
    Assignee: Nuvera Fuel Cells, LLC
    Inventor: Scott Blanchet
  • Patent number: 10008405
    Abstract: An embodiment of the present invention relates to an expansion method comprising: a step (I) of preparing a laminate having a semiconductor wafer in which modified sections have been formed along intended cutting lines, a die bonding film and a dicing tape, a step (IIA) of expanding the dicing tape with the laminate in a cooled state, a step (IIB) of loosening the expanded dicing tape, and a step (IIC) of expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening the spaces between the chips.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: June 26, 2018
    Assignee: HITACHI CHEMICAL COMPANY, LTD
    Inventors: Yukihiro Iwanaga, Kouji Suzumura, Tatsuya Sakuta