Including Adhesive Bonding Step Patents (Class 438/118)
  • Patent number: 11404344
    Abstract: A heat spreading plate is suitable to be a top cover of a chip package structure. The heat spreading plate includes a main body and an isolating frame. The main body includes a plurality of metal sheets which are arranged spaced apart from one another totally and capable of thermally connecting different working chips mounted within the chip package structure, respectively. A gap is formed between any two neighboring ones of the metal sheets to completely separate them. The isolating frame surrounds the outer edges of the metal sheets and fills into the gaps for fixedly holding the metal sheets together. One surface of the isolating frame is formed with a plurality of hollow recesses, and each of the metal sheets is exposed outwards from one of the hollow recesses.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: August 2, 2022
    Assignee: Jentech Precision Industrial Co., LTD.
    Inventor: Chun-Ta Yeh
  • Patent number: 11393720
    Abstract: A method for separating semiconductor dies of a semiconductor die assembly comprises depositing a first coating on a first surface of the assembly. The assembly comprises a die wafer having a plurality of semiconductor dies and first and second surfaces. A first portion of the die wafer and the first coating is removed between adjacent semiconductor dies to form trenches having an intermediate depth in the die wafer between first and second surfaces such that die corners are formed on either side of the trenches. A protective coating is deposited on the first surface of the die assembly to cover the die corners, trenches and at least a portion of the first coating. The first coating is selectively removed such that portions of the protective coating covering die corners and trenches remain on the die wafer. Adjacent semiconductor dies are separated and the protective coating remains covering the die corners.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Po Chih Yang
  • Patent number: 11367995
    Abstract: An electronic device according to a present disclosure includes a semiconductor substrate, a chip, and a connection part. The chip has a different thermal expansion rate from that of the semiconductor substrate. The connection part includes a porous metal layer for connecting connection pads that are arranged on opposing principle surfaces of the semiconductor substrate and the chip.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: June 21, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Takashi Imahigashi, Kaoru Tanaka, Masashi Miyazaki
  • Patent number: 11367667
    Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: June 21, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Hong Wan Ng, Choon Kuan Lee, David J. Corisis, Chin Hui Chong
  • Patent number: 11335614
    Abstract: In an electric component embedded structure, a first electrode terminal provided on a first main surface includes an intra-area terminal, and the intra-area terminal is electrically connected to an overlap portion of an overlap wiring in a formation area of an electric component. Accordingly, a decrease in mounting area of the electric component embedded structure is achieved. The intra-area terminal can be electrically connected to a second electrode terminal provided on a second main surface via a first via-conductor, the overlap wiring, and a second via-conductor. The intra-area terminal is connected to a wiring (an overlap wiring) of a first insulating layer without additionally providing a rewiring layer causing an increase in thickness, and the increase in thickness is curbed, whereby a decrease in size of the electric component embedded structure is achieved.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: May 17, 2022
    Assignee: TDK CORPORATION
    Inventors: Takaaki Morita, Kenichi Yoshida, Mitsuhiro Tomikawa
  • Patent number: 11328978
    Abstract: A device package and a method of forming a device package are described. The device package has dies disposed on a substrate, and one or more layers with a high thermal conductivity, referred to as the highly-conductive (HC) intermediate layers, disposed on the dies on the substrate. The device package further includes a lid with legs on an outer periphery of the lid, a top surface, and a bottom surface. The legs of the lid are attached to the substrate with a sealant. The bottom surface of the lid is disposed over the one or more HC intermediate layers and the one or more dies on the substrate. The device package may also include thermal interface materials (TIMs) disposed on the HC intermediate layers. The TIMs may be disposed between the bottom surface of the lid and one or more top surfaces of the HC intermediate layers.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Johanna M. Swan, Sergio Chan Arguedas, John J. Beatty
  • Patent number: 11315821
    Abstract: A processing method for a wafer includes the steps of forming a frame unit having a ring-shaped frame, providing a resin sheet, fixing the resin sheet, which covers the wafer at its front side, at its outer peripheral edge, on the ring-shaped frame, forming through-holes in the resin sheet, holding the frame unit on a side of the resin sheet under suction on a holding surface to fix the ring-shaped frame, applying a laser beam to the wafer to form modified layers inside the wafer, and separating the resin sheet. In the holding step, the adhesive tape is suctioned under a negative pressure acting from the holding surface via through-holes while the front side of the wafer is prevented by the resin sheet from being suctioned on the holding surface.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: April 26, 2022
    Assignee: DISCO CORPORATION
    Inventor: Jinyan Zhao
  • Patent number: 11291116
    Abstract: An integrated circuit structure and method of forming is provided. A die is placed on a substrate and encased in molding compound. A redistribution layer is formed overlying the die and the substrate is removed. One or more surface mounted devices and/or packages are connected to the redistribution layer on an opposite side of the redistribution layer from the die. The redistribution layer is connected to a printed circuit board.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jui-Pin Hung, Kuo-Chung Yee
  • Patent number: 11289459
    Abstract: The present invention relates to an apparatus and a method for manufacturing a light-emitting diode (LED) module and, more particularly, to an apparatus and a method for manufacturing a light-emitting diode module, which are capable of manufacturing a light emitting diode module on which a plurality of light-emitting diodes are mounted with an improved bonding speed and high accuracy by manufacturing the light-emitting diode module by simultaneously transferring the plurality of light emitting diodes onto a substrate by using a multi-eject pin or a multi-collet.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: March 29, 2022
    Assignee: LUMENS CO., LTD.
    Inventors: Seung Hyun Oh, Sung Sik Jo, Jung Hyun Park
  • Patent number: 11254563
    Abstract: Embodiments include a microelectronic device package structure having a die on a substrate, where a first side of the die is electrically coupled to the substrate, and a second side of the die is covered with a first material having a first thermal conductivity. A second material is adjacent to a sidewall of the die and adjacent to a sidewall of the first material. The second material has second thermal conductivity, smaller than the first thermal conductivity. The second material may have mechanical and/or underfill properties superior to those of the first material. Together, the two materials may provide a package structure having enhanced thermal and mechanical performance.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: February 22, 2022
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nitin A. Deshpande
  • Patent number: 11227983
    Abstract: A method of manufacturing a light emitting device includes: providing a substantially flat plate-shaped base member which in plan view includes at least one first portion having an upper surface, and a second portion surrounding the at least one first portion and having inner lateral surfaces; mounting at least one light emitting element on the at least one first portion; shifting a relative positional relationship between the at least one first portion and the second portion in an upper-lower direction to form at least one recess defined by an upper surface of the at least one first portion that serves as a bottom surface of the at least one recess and at least portions of the inner lateral surfaces of the second portion that serve as lateral surfaces of the at least one recess; and bonding the at least one first portion and the second portion with each other.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: January 18, 2022
    Assignee: NICHIA CORPORATION
    Inventor: Tsuzuki Takahashi
  • Patent number: 11217471
    Abstract: A method for executing a direct transfer of semiconductor device die from a first substrate to transfer locations on a second substrate. The method includes determining a position of impact wires disposed on a transfer head, semiconductor device die, and transfer locations; determining whether there are at least two positions that an impact wire, a semiconductor device die, and a transfer locations are aligned within a threshold tolerance; and transferring, by the impact wires, the semiconductor device die such that the semiconductor device die detaches from the first substrate and attaches to transfer locations on the second substrate. The transferring being completed based at least in part on determining that the impact wire, the semiconductor device die, and the circuit trace are aligned within the threshold tolerance.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: January 4, 2022
    Assignee: Rohinni, LLC
    Inventors: Cody Peterson, Andrew Huska
  • Patent number: 11192339
    Abstract: One embodiment of the disclosure discloses a touch screen display including a first polarizing plate, a second polarizing plate disposed under the first polarizing plate, a touch panel disposed between the first polarizing plate and the second polarizing plate, a display panel disposed under the second polarizing plate, and a photosensitive adhesive member disposed at least between the first polarizing plate and the touch panel or between the second polarizing plate and the display panel. Further, one embodiment of the disclosure discloses an electronic device including the touch screen display. In addition, various embodiments are possible which are understood through the specification.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 7, 2021
    Inventor: Min Uk Kim
  • Patent number: 11164745
    Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include exposing a substrate to a blocking molecule to selectively deposit a blocking layer on the first surface. The blocking layer is exposed to a polymer initiator to form a networked blocking layer. A layer is selectively formed on the second surface. The blocking layer inhibits deposition on the first surface. The networked layer may then optionally be removed.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: November 2, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Mark Saly, Bhaskar Jyoti Bhuyan
  • Patent number: 11158558
    Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
  • Patent number: 11152256
    Abstract: A carrier film according to an embodiment of the present invention comprises: a base film; and a first adhesive layer formed on a surface of the base film such that an element to be transferred is attached to the first adhesive layer, wherein the magnitude of force of adhesion between the element and the first adhesive layer is in proportion to the depth of press-fitting at which the element is press-fitted into the first adhesive layer.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: October 19, 2021
    Assignees: KOREA INSTITUTE OF MACHINERY & MATERIALS, CENTER FOR ADVANCED META-MATERIALS
    Inventors: Yun Hwangbo, Byung-Ik Choi, Jae-Hyun Kim, Hak Joo Lee, Bongkyun Jang, Yeon Woo Jeong, Seong Min Hong
  • Patent number: 11152914
    Abstract: An elastic wave device includes a piezoelectric layer including a first main surface and a second main surface facing the first main surface, an acoustically reflective layer stacked on the first main surface of the piezoelectric layer, an excitation electrode disposed on the piezoelectric layer, and a support layer. The acoustically reflective layer overlaps at least the excitation electrode in a plan view of the piezoelectric layer from the side of the second main surface. The support layer surrounds the acoustically reflective layer in a plan view of the piezoelectric layer from the side of the second main surface.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: October 19, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yutaka Kishimoto
  • Patent number: 11128268
    Abstract: Power amplifier (PA) packages containing peripherally-encapsulated dies are provided, as are methods for fabricating such PA packages. In embodiments, a method for fabricating a PA package includes obtaining a die-substrate assembly containing a radio frequency (RF) power die, a package substrate, and a die bond layer. The die bond layer is composed of at least one metallic constituent and electrically couples a backside of the RF power die to the package substrate. A peripheral encapsulant body is formed around the RF power die and covers at least a portion of the die bond layer, while leaving at least a majority of a frontside of the RF power die uncovered. Before or after forming the peripheral encapsulant body, terminals of the PA package are interconnected with the RF power die; and a cover piece is bonded to the die-substrate assembly to enclose a gas-containing cavity within the PA package.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: September 21, 2021
    Assignee: NXP USA, Inc.
    Inventors: Sharan Kishore, Jaynal A. Molla, Lakshminarayan Viswanathan, Tianwei Sun, David James Dougherty
  • Patent number: 11088106
    Abstract: A stack of electrical components has a first electrical component having a first surface, a second surface that is opposite to the first surface and a side surface that is located between the first surface and the second surface; a second electrical component having a third surface on which the first electrical component is mounted, the third surface facing the second surface and forming a corner portion between the third surface and the side surface; an adhesive layer that bonds the first electrical component to the second electrical component, wherein the adhesive layer has a first portion that is located between the second surface and the third surface and a curved second portion that fills the corner portion; and a conductive layer that extends on a side of the side surface, curves along the second portion and extends to the third surface.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: August 10, 2021
    Assignee: TDK Corporation
    Inventors: Yohei Hirota, Hiroshi Yamazaki, Hitoshi Iwama, Yusuke Takahashi
  • Patent number: 11062968
    Abstract: A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes an interposer, a first semiconductor die and a second semiconductor die over the interposer. The method for forming a package structure also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component. The method for forming a package structure further includes forming an underfill layer between the dam structure and the package component, and removing the dam structure after the underfill layer is formed.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Chen, Chih-Chien Pan, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu
  • Patent number: 11062923
    Abstract: An apparatus includes a transfer mechanism to transfer an electrically-actuatable element directly from a wafer tape to a transfer location on a circuit trace on a product substrate. The transfer mechanism includes one or more transfer wires. Two or more stabilizers disposed on either side of the one or more transfer wires. A needle actuator is connected to the one or more transfer wires and the two or more stabilizers to move the one or more transfer wires and the two or more stabilizers to a die transfer position.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 13, 2021
    Assignee: Rohinni, LLC
    Inventors: Justin Wendt, Cody Peterson, Andrew Huska
  • Patent number: 11056466
    Abstract: Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A gap forms between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. Additionally, interstitial gaps form between each of the PoP semiconductor packages disposed on an organic substrate. A curable fluid material, such as a molding compound, may be flowed both in the interstitial spaces between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Omkar Karhade, Christopher L. Rumer, Nitin Deshpande, Robert M. Nickerson
  • Patent number: 11043418
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: June 22, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Jason E. Stephens, Daniel Chanemougame, Ruilong Xie, Lars W. Liebmann, Gregory A. Northrop
  • Patent number: 11031374
    Abstract: Some embodiments include a method in which a first semiconductor wafer and a second semiconductor wafer are bonded with each other. The first semiconductor wafer includes a memory cell array, and the second semiconductor wafer includes a circuit to access the memory cell array. After the bonding, contacts are formed to be associated with the first semiconductor wafer. The contacts are for electrical connections between the first and second semiconductor wafers. The contacts are linked with reference positions, with each of the contacts being linked with an associated one of the reference positions. Each of the contacts is shifted from its associated one of the reference positions to absorb a bonding alignment error between the first and second semiconductor wafers.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Mitsunari Sukekawa
  • Patent number: 11006832
    Abstract: A wireless sensor device capable of constant operation without replacement of batteries. The wireless sensor device is equipped with a rechargeable battery and the battery is recharged wirelessly. Radio waves received at an antenna circuit are converted into electrical energy and stored in the battery. A sensor circuit operates with the electrical energy stored in the battery, and acquires information. Then, a signal containing the information acquired is converted into radio waves at the antenna circuit, whereby the information can be read out wirelessly.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: May 18, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Jun Koyama
  • Patent number: 10971457
    Abstract: A semiconductor device is disclosed. In one example, the semiconductor device comprises a first semiconductor die comprising a first surface, a second surface opposite to the first surface, and a contact pad disposed on the first surface, a further contact pad spaced apart from the semiconductor die, a clip comprising a first layer of a first metallic material and a second layer of a second metallic material different from the first metallic material, wherein the first layer of the clip is connected with the contact pad, and the second layer of the clip is connected with the further contact pad.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: April 6, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Bemmerl, Martin Gruber, Thorsten Scharf
  • Patent number: 10947330
    Abstract: A method for encapsulating a catalyst in a dispersed polymer particle comprising dissolving a Group 8 to Group 11 transition metal containing catalyst and a self-dispersing polymer in a solvent; adding water and optionally a base under particle forming conditions to form a dispersed polymer encapsulated catalyst comprising particles having a population number average diameter between 10 and 300 nanometers is provided.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: March 16, 2021
    Assignees: ROHM AND HAAS COMPANY, THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS
    Inventors: Damien Guironnet, Muhammad Rabnawaz, Ralph Even, Andrew Hughes, Joshua Katz
  • Patent number: 10943846
    Abstract: A chip package structure includes a circuit structure, a redistribution structure, a heat conductive component, a chip, and a heat sink. The circuit structure includes a first circuit layer. The redistribution structure is disposed on the circuit structure and includes a second circuit layer, wherein the redistribution structure has an opening. The heat conductive component is disposed on the circuit structure and covered by the redistribution structure. The heat conductive component has a horizontal portion and a vertical portion. The horizontal portion extends toward the opening until it exceeds the opening. The vertical portion extends upward beyond the top surface of the redistribution structure from a part of the horizontal portion. The chip is disposed in the opening, and the bottom of the chip contacts the heat conductive component. The heat sink is disposed over the redistribution structure and the chip.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: March 9, 2021
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Tzu-Hsuan Wang, Chien-Chen Lin, Kuan-Wen Fong
  • Patent number: 10925163
    Abstract: A printed circuit board includes an insulating layer including a cavity including a groove structure formed on one surface of the insulating layer, a circuit pattern including a first pad formed on a bottom surface of the cavity and a second pad formed inside the insulating layer, a first metal layer embedded in a side surface of the cavity, the first metal layer being in contact with the bottom surface of the cavity and being formed along the boundary of the cavity, and a second metal layer formed on the second pad and having a stepped structure formed with the second pad.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: February 16, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Je Sang Park, Sang Ho Jeong
  • Patent number: 10919758
    Abstract: A physical quantity sensor includes a substrate, an acceleration sensor mounted on the substrate, an integrated circuit mounted on the substrate and stacked with the acceleration sensor, and serial communication wirings provided to the substrate. In a plan view of the acceleration sensor element, a bonding wire connecting the acceleration sensor element to the integrated circuit is disposed on an opposite side to the serial communication wirings with respect to a virtual central line of the acceleration sensor element.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: February 16, 2021
    Inventor: Yoshinao Yanagisawa
  • Patent number: 10916450
    Abstract: A method includes forming a release film over a carrier, forming a metal post on the release film, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, decomposing a first portion of the release film to separate a second portion of the release film from the carrier, and forming an opening in the release film to expose the metal post.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: February 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Pu Wang, Szu-Wei Lu, Ying-Ching Shih, Jing-Cheng Lin
  • Patent number: 10859915
    Abstract: A method is provided including forming a first layer over a substrate and forming an adhesion layer over the first layer. The adhesion layer has a composition including an epoxy group. A photoresist layer is formed directly on the adhesion layer. A portion of the photoresist layer is exposed to a radiation source. The composition of the adhesion layer and the exposed portion of the photoresist layer cross-link using the epoxy group. Thee photoresist layer is then developed (e.g., by a negative tone developer) to form a photoresist pattern feature, which may overlie the formed cross-linked region.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Yu Liu, Tzu-Yang Lin, Ya-Ching Chang, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10859598
    Abstract: A method for electrically connecting a test and measurement instrument to a via of a printed circuit board, PCB, the method comprising: dispensing a UV-curable conductive adhesive into a back-drilled hole formed in the PCB, the back-drilled hole extending to the via, such that the dispensed adhesive contacts the via; curing the dispensed adhesive by applying a UV light source to the dispensed adhesive; and connecting a test and measurement instrument to the cured adhesive using a conductive member.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: December 8, 2020
    Assignee: Tektronix, Inc.
    Inventors: Julie A. Campbell, Karl A. Rinder, Daniel G. Knierim
  • Patent number: 10861814
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a bump structure, a polymer layer and a metal layer. The bump structure includes a metal pad and a bump electrically connected to the metal pad. The polymer layer extends laterally from a sidewall of the bump. The metal layer is over the bump structure and in physical contact with a side surface of the metal pad.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzung-Hui Lee, Chen-Hua Yu, Chi-Ming Tsai, Hung-Jui Kuo, Ming-Che Ho
  • Patent number: 10832935
    Abstract: An exemplary wafer structure comprises a source wafer having a patterned sacrificial layer defining anchor portions separating sacrificial portions. A patterned device layer is disposed on or over the patterned sacrificial layer, forming a device anchor on each of the anchor portions. One or more devices are disposed in the patterned device layer, each device disposed entirely over a corresponding one of the one or more sacrificial portions and spatially separated from the one or more device anchors. A tether structure connects each device to a device anchor. The tether structure comprises a tether device portion disposed on or over the device, a tether anchor portion disposed on or over the device anchor, and a tether connecting the tether device portion to the tether anchor portion. The tether is disposed at least partly in the patterned device layer between the device and the device anchor.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: November 10, 2020
    Assignee: X Display Company Technology Limited
    Inventors: Christopher Andrew Bower, Matthew Meitl, Salvatore Bonafede, Brook Raymond, Carl Ray Prevatte, Jr.
  • Patent number: 10830544
    Abstract: A self-healing metal structure is provided for transferring heat between an electronics component and a substrate. The self-healing metal structure includes a base metal structural component. A phase change material is provided adjacent at least a portion of the base metal structural component. A protective component at least partially encapsulates the phase change material. Upon the presence of a spatial defect in the base metal structural component, the phase change material reacts with the base structural component to form an intermetallic compound to at least partially occupy the spatial defect. The phase change material at least partially encapsulated with the protective component may be disposed within the base metal structural component as a plurality of separate capsules incorporated therein, or the phase change material at least partially surrounds the base metal structural component.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: November 10, 2020
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Shailesh N. Joshi, Naoya Take
  • Patent number: 10825484
    Abstract: A method of forming an integrated assembly includes providing a construction having laterally-spaced digit-line-contact-regions and having intervening regions between the laterally-spaced digit-line-contact-regions; forming an expanse of non-conductive-semiconductor-material which extends across the digit-line-contact-regions and the intervening regions; a lower surface of the non-conductive-semiconductor-material being vertically-spaced from upper surfaces of the digit-line-contact-regions; forming openings extending through the non-conductive-semiconductor-material to the digit-line-contact-regions; forming conductive-semiconductor-material-interconnects within the openings and coupled with the digit-line-contact-regions, upper surfaces of the conductive-semiconductor-material-interconnects being beneath the lower surface of the non-conductive-semiconductor-material; and forming metal-containing-digit-lines over the non-conductive-semiconductor-material.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Chandra Pandey, Si-Woo Lee
  • Patent number: 10772213
    Abstract: An adhesive substrate is disclosed, which includes a base substrate and a heat-resistant elastomer layer formed on the base substrate, wherein the base substrate is flexible and has a thickness of 0.2 mm or more and 2 mm or less, wherein the adhesive substrate is used as part of a method for physically separating an object that has been held immovable in such a manner that the object has been adhered to by the heat-resistant elastomer layer and the object is anchored from the upper side, and wherein by starting to physically separate the end portion of the adhesive substrate downward the object is able to be separated.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: September 8, 2020
    Assignee: Shin-Etsu Polymer Co., Ltd.
    Inventors: Yuji Irisawa, Toshiaki Hatsumi
  • Patent number: 10763185
    Abstract: Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Matt E. Schwab, J. Michael Brooks, David J. Corisis
  • Patent number: 10748855
    Abstract: A method of fabricating a semiconductor package using a laminating device is provided. The method includes placing a substrate on a substrate stand; providing a pressurizing unit which is expandable and includes a convex surface facing an upper surface of the substrate stand, on the substrate stand; injecting air into the pressurizing unit using a plate which is connected to the pressurizing unit; and supplying a film by a film supply unit which supplies the film between the substrate stand and the pressurizing unit, wherein the pressurizing unit attaches the film onto the substrate, while expanding.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tea-Geon Kim, Jung Lae Jung
  • Patent number: 10739209
    Abstract: Carbon nanotube-based multi-sensors for packaging applications and methods to form the carbon nanotube-based multi-sensors are capable of simultaneously measuring at least two measurands including temperature, strain, and humidity via changes in its electrical properties.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric Duchesne, Dominique Drouin, Hélène Frémont, Simon Landry, Aurore F. M. E. Quelennec, Umar Shafique, Patrick R. J. Wilson
  • Patent number: 10700008
    Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a RDL structure, an encapsulant and a conductive terminal. The die is on a redistribution layer (RDL) structure. The RDL structure comprises a polymer layer and a RDL in the polymer layer. The encapsulant is on the RDL structure and laterally aside the die. The encapsulant comprises a body part and an extending part underlying the body part. The conductive terminal is electrically connected to the RDL structure and the die. The body part of the encapsulant encapsulates sidewalls of the die. The extending part of the encapsulant extends into the polymer layer.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Chang, Hao-Yi Tsai, Tsung-Hsien Chiang, Tin-Hao Kuo
  • Patent number: 10679897
    Abstract: Disclosed herein is a device wafer processing method including a protective film forming step of applying a water-soluble protective film material to the front side of a device wafer having devices separated by division lines and next exposing the division lines to form a protective film for protecting each device, an application time recording step of recording the time at which the water-soluble protective film material is applied to the device wafer, a determining step of determining whether or not a predetermined duration has elapsed from the time recorded in the application time recording step, an etching step of dry-etching the device wafer along the division lines after performing the determining step, and a protective film removing step of supplying a cleaning water to the protective film to thereby remove the protective film after performing the etching step. Only when it is determined in the determining step that the predetermined duration has not elapsed, the etching step is performed.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: June 9, 2020
    Assignee: DISCO CORPORATION
    Inventors: Koichi Shigematsu, Satoshi Kumazawa
  • Patent number: 10622237
    Abstract: A conveying mechanism for conveying a wafer unit having a wafer disposed inside of and supported on an annular frame by a holding tape includes a housing tray housing the wafer unit therein and a transport unit supporting and transporting the housing tray between wafer treating apparatus. The housing tray includes a ceiling plate and a bottom plate that are interconnected by a pair of side walls facing each other across an opening defined in a side through which the wafer unit can be taken into and out of the housing tray. An air flow generator is disposed on the ceiling plate for generating air downflows in the housing tray that are directed from the ceiling plate into the opening. The transport unit conveys wafer units, one by one, between the wafer treating apparatus.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: April 14, 2020
    Assignee: DISCO CORPORATION
    Inventors: Kazunari Tanaka, Satoshi Ohkawara
  • Patent number: 10600760
    Abstract: Capacitive coupling of integrated circuit die components and other conductive areas is provided. Each component to be coupled has a surface that includes at least one conductive area, such as a metal pad or plate. An ultrathin layer of dielectric is formed on at least one surface to be coupled. When the two components, e.g., one from each die, are permanently contacted together, the ultrathin layer of dielectric remains between the two surfaces, forming a capacitor or capacitive interface between the conductive areas of each respective component. The ultrathin layer of dielectric may be composed of multiple layers of various dielectrics, but in one implementation, the overall thickness is less than approximately 50 nanometers. The capacitance per unit area of the capacitive interface formed depends on the particular dielectric constants ? of the dielectric materials employed in the ultrathin layer and their respective thicknesses.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: March 24, 2020
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Arkalgud R. Sitaram
  • Patent number: 10595424
    Abstract: This hermetic sealing lid member (10) is made of a clad material (20) including a silver brazing layer (21) that contains Ag and Cu and a first Fe layer (22) bonded onto the silver brazing layer and made of Fe or an Fe alloy. The hermetic sealing lid member is formed in a box shape including a recess portion (13) by bending the clad material.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: March 17, 2020
    Assignee: HITACHI METALS, LTD.
    Inventors: Masayuki Yokota, Masaharu Yamamoto
  • Patent number: 10580756
    Abstract: Wirebond bondpads on semiconductor packages that result in reduced cross-talk and/or interference between vertical wires are disclosed. The vertical wirebonds may be disposed in the semiconductor package with stacked dies, where the wires are substantially normal to the bondpads to which the vertical wirebonds are attached on the dies. The wirebond bondpads may include signal pads that carry input/output (I/O) to/from the die package, as well as ground bondpads. The bondpads may have widths that are greater than the space between adjacent bondpads. Bondpads may be fabricated to be larger than the size requirements for reliable wirebond formation on the bondpads. For a fixed pitch bondpad configuration, the size of the signal bondpads adjacent to the ground bondpads may be greater than half of the pitch. By increasing the size of the signal bondpads adjacent to a ground line relative to the space therebetween, improved cross-talk performance may be achieved.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventor: Hungying L. Lo
  • Patent number: 10566949
    Abstract: A transducer includes first and second piezoelectric layers made of corresponding different first and second piezoelectric materials and three or more electrodes, implemented in two or more conductive electrode layers. The first piezoelectric layer is sandwiched between a first pair of electrodes and the second piezoelectric layer is sandwiched between a second pair of electrodes. The first and second pairs of electrodes contain no more than one electrode that is common to both pairs.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: February 18, 2020
    Assignee: CHIRP MICROSYSTEMS, INC.
    Inventors: Stefon Shelton, Andre Guedes, Richard Przybyla, Meng-Hsiung Kiang, David Horsley
  • Patent number: 10551194
    Abstract: A sensor unit with high reliability and stable detection accuracy against vibrations of an installation target object is to be provided. A sensor unit includes: a sensor module configured including a substrate with inertial sensors mounted thereon, and an inner case in which the substrate is installed; and an outer case accommodating the sensor module. A recessed part is formed in the inner case. The inertial sensors are arranged in an area overlapping with the recessed part as viewed in a plan view seen from the direction of thickness of the substrate, and a filling member is provided to fill a space formed by the substrate and the recessed part. The sensor module is joined to a bottom wall of the outer case via a joining member.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: February 4, 2020
    Assignee: Seiko Epson Corporation
    Inventors: Yusuke Kinoshita, Masayasu Sakuma
  • Patent number: 10535378
    Abstract: Some embodiments include an integrated assembly which has digit-line-contact-regions laterally spaced from one another by intervening regions. Non-conductive-semiconductor-material is over the intervening regions. Openings extend through the non-conductive-semiconductor-material to the digit-line-contact-regions. Conductive-semiconductor-material-interconnects are within the openings and are coupled with the digit-line-contact-regions. Upper surfaces of the conductive-semiconductor-material-interconnects are beneath a lower surface of the non-conductive-semiconductor-material. Metal-containing-digit-lines are over the non-conductive-semiconductor-material. Conductive regions extend downwardly from the metal-containing-digit-lines to couple with the conductive-semiconductor-material-interconnects. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: January 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Chandra Pandey, Si-Woo Lee