Abstract: A method for position-selective and material-selective etching of silicon, and examination structures formed using the method, are presented. A semiconductor topography is exposed to an electron beam in the presence of xenon difluoride (XeF2) gas. The beam is scanned over a portion of the semiconductor topography, and silicon portions of the topography contacted by the electron beam and the XeF2 gas are etched. Non-silicon portions, such as dielectrics, metals, and/or metal silicides, are not believed to be etched. Shorter exposure times may be used to remove polycrystalline silicon portions of a topography, while leaving monocrystalline silicon portions intact. Removal of silicon and non-silicon portions of the topography by other means may be used to expose silicon portions of the topography. The electron beam controlled etching recited herein may be used alone or combined with such removal by other means to form examination structures for use in evaluation of semiconductor manufacturing techniques.

Abstract: A test arrangement is designed to test whether one in a chain of vias or contacts has abnormally high resistance. The arrangement contains a plurality of via or contact chains and a plurality of decoders. The chains are switchably connected to a resistance measurement device. Each decoder has a unique address such that it will generate a control signal when a predetermined address is address thereon. The control signal is used to close a switch, which connect one of the chains to the resistance measurement device. By sequentially applying different addresses to the decoders, the resistance of the chains can be individually measured.

Abstract: A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer.

Abstract: A semiconductor random access memory device has stacked capacitor electrodes and test conductive pieces laid on the same pattern as the stacked capacitor electrodes, and the test conductive pieces are alternately isolated from and connected to a ground line, wherein the test conductive pieces are scanned with an electron beam to see whether or not any one of the conductive pieces generates secondary electrons different in intensity from those radiated from the other conductive pieces for detecting a short-circuit, whereby an analyst investigates the stacked capacitor electrodes for a possible short-circuit.

Abstract: A dummy active region is formed in which abrading processes are averaged. A semiconductor device is characterized in that an active region for forming an actual device, a device separation region being formed by a trench, and a dummy active region formed substantially in a rectangular shape are included, and the length of the short side of the dummy active region is less than 1 &mgr;m.

Abstract: A device of forming a film from an organic compound material at low cost is provided, using an organic compound material having high light emission efficiency. An organic compound film is formed on a substrate under an inert gas atmosphere by spraying of a colloid solution in which organic compound aggregates are dispersed (this solution is also referred to as a “sol”). Note that the organic compound may be one in which particles are composed of aggregates of several organic compounds within a liquid, and may be one in which a portion of the organic compound is dissolved within a liquid.

Abstract: A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the dice with the temporary test package bases, and an automated robot arm system is employed to retrieve and assemble the dice with the various package components. The invention has particular utility in the burn-in and other pre-packaging testing of dice to establish known good dice (KGD).

Abstract: A contact structure for establishing electrical connection with contact targets. The contact structure is formed of a contact substrate and a plurality of contactors. The contactor has a tip portion which is protruded in a vertical direction to form a contact point, a base portion which is inserted in a through hole provided on the contact substrate in such a way that an end of the contactor functions as a contact pad for electrical connection at a surface of the contact substrate, and a spring portion provided between the tip portion and the base portion which produces a contact force when the contactor is pressed against the contact target.

Abstract: A sorting section can be supplied with parts from plurality of supply sources. A semiconductor device sorting system is provided with a sorting section for sorting good transistors by means of an electric performance test thereof and supply sections adapted to separate the transistor parts that are collectively supplied in a complex into transistors and supply the separated transistors to the sorting section. An appropriate one of the supply sections can be selected corresponding to the supply form of the transistor parts to be separated. A selected supply section can be switched to another depending on the supply form of the transistor parts.

Abstract: A semiconductor structure and a method for reducing charge damage during plasma etch processing are disclosed. Structures (22, 26, 28) for accumulating charge during plasma etch processing are provided on a semiconductor wafer (10), the structures (22, 26, 28) being electrically connected to device structures (30, 32).

Abstract: This invention relates to the fabrication of thin-film transistors (TFTs) on a substrate (4) such as a glass or insulating polymer substrate for use in an active-matrix liquid-crystal display or other large area electronic device. A method of forming a TFT is described which includes the deposition of a masking layer (8) over a semiconductor film (2) and the removal of portions of the masking layer (8) to form a plurality of holes therethrough of a predetermined size and distribution. The perforated portion (26,28) of the masking layer (8) serves to mask partially the semiconductor film (2) during a dopant implantation step to form a field relief region (20,22) simultaneously with definition of the source and drain regions (16,18).

Abstract: The present invention provides an ink-jet ink composition which includes (a) at least one water-soluble dye; (b) at least one low vapor-pressure solvent; (c) a nonionic non-amphoteric surfactant; (d) a fluoric surfactant; and (e) balanced water. The ink-jet ink composition of the present invention is suitable for thermal ink-jet printers.

Abstract: A semiconductor chip has, at a corner area of the chip, an evaluation test circuit for evaluating the operational speed of the internal circuit of the semiconductor chip, and a reference element having a known coordinates and emitting light and/or generating heat upon energization thereof. Coordinates of a failed element found in a normal test are fixed with respect to the known coordinates of the reference element for analyzing the failed element.

Abstract: It is an object of the present invention to provide a structure capable of determining a failed part of a semiconductor device in sufficient detail. An n+ impurity region (3) and a p+ impurity region (4) are connected with each other and further connected with a peripheral circuit (50). A gate electrode (1) and a gate electrode (10) are connected with each other and further connected with the peripheral circuit (50). A ground potential (8) is applied to an n+ impurity region (2) and a p− well region (6). A power source potential (9) is applied to a p+ impurity region (5) and an n− well region (7). An n+ impurity region (23) and a p+ impurity region (24) are connected with each other and further connected with the gate electrode (10) through a metal wire (31). The ground potential (8) is applied to a p− well region (26) and the power source potential (9) is applied to an n− well region (27).

Abstract: One or more electrical characteristics of an integrated circuit device are measured at one or more relatively lower frequencies. One or more parameters of the integrated circuit device are measured at one or more frequencies higher than the one or more relatively lower frequencies. One or more parameters of the integrated circuit device are calculated based on the measured one or more electrical characteristics. The integrated circuit device is characterized based on the calculated one or more parameters and the measured one or more parameters.

Abstract: To provide a method for evaluating chargeup damage caused in the practical fabrication process. Evaluation is carried out based on the electric current flowing between the source and the drain of a MOS transistor of a semiconductor element (1—1) having a wiring layer provided with an antenna effect by installing the semiconductor element (1—1) in the periphery of a practical device installed in a semiconductor substrate and measuring the electric current without attaching a probe to the gate of the semiconductor element (1—1).

Abstract: A method of inspecting a semiconductive wafer-in-process to determine the accuracy of alignment of a lower process layer to an upper process layer. In this method, a conductive target attribute is formed on a first alignment portion of the wafer-in-process. A contact attribute is formed on the upper process layer through which an electric path can be established with the target attribute in an acceptable alignment situation but cannot established in an unacceptable alignment situation. By attempting to establish an electric path from the target attribute through the contact attribute, the accuracy of alignment can be determined based on whether or not an electrical path is established. The target attribute may be a series of conductive strips and the contact attribute may be a series of contact holes that will overlay the corresponding target attributes in differing degrees in an acceptable alignment situation.

Abstract: A semiconductor integrated circuit device provided with an IC chip so as to prevent its circuits from malfunction when the IC chip is cracked. To detect chip cracks, a resistor R01 is disposed at the outer periphery of the area which wants to detect the chip crack. If the chip is cracked and the resistance value of the resistor R01 is changed, the resistance change is detected, thereby controlling internal signals such as the power on reset signal and stopping the whole operation of the circuit device so as to prevent the circuits from malfunction. Thus, the system security can also be improved.

Abstract: A measurement method and system are presented for measuring parameters of a patterned structure. Scatterometry and SEM measurements are applied to the structure, measured data indicative of, respectively, the structure parameters and lateral pattern dimensions of the structure are generated. The entire measured data are analyzed so as to enable using measurement results of either one of the scatterometry and SEM measurements for optimizing the other measurement results.

Abstract: The present invention provides a structure of a contact chain comprising a substrate of a first conductive type, a dielectric layer on the substrate, a plurality of contact structures and two probe pads. The contact structures are connected in series and have two ends. Each contact structure comprises a contact hole in the dielectric layer and conductive material in the contact hole, for electrically contacting with a first doped layer of a second conductive type. The first doped region is formed on the substrate. Two probe pads are coupled to the two ends, respectively. The contact chain further comprises a means for selectively coupling the first doped layer to the substrate. When the first doped layer is not coupled to the substrate, the total resistance of the contact chain can be measured through the two probe pads.

Abstract: A testing methodology for increasing the performance and reliability of integrated circuits (“chips”) outputted from a manufacturing process, utilizes a method by which the operating frequency of the integrated circuit is measured when the Self-Timed Pulse Control parameter is adjusted to provide a more strict test upon the chip. Under this more stringent test, the integrated circuits that do not pass the test then are designated as failures or marketed with listed lower operating frequencies.

Abstract: A method and apparatus is provided to identify defective laminate objects or package substrates having mounting sites for integrated circuit dies during the package substrate fabrication process. A hole is drilled or punched within the boundary of an individual package substrate contained within a larger laminate substrate and covered with a material layer coating composed of an opaque material such as a resist. The coating may then be selectively applied or removed at a later point during the fabrication process dependent upon whether the package substrate has been classified as defective or non-defective. After specific package substrates have been marked as defective, a light source and light collector are supplied to the fabrication process on opposite sides of the wafer. By shining the light source on the laminate substrate, defective package substrates can be identified by the passage of light through the hole which is no longer covered with resist.

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.

Abstract: First characteristic values (SS,FF) which fluctuate most of the characteristic of a device composing a semiconductor device are obtained according to a fluctuation of manufacturing process for the semiconductor device. Next, the width (optimized K value) of a fluctuation width of manufacturing process which matches second characteristic values (C1,C16) of the worst cases of the characteristic of this device with the first characteristic values (SS,FF) is determined. Finally, a third characteristic value of the worst case of the circuit characteristic of the semiconductor device is determined based on this fluctuation width (optimized K value).

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.

Abstract: The method of the present invention is a method of forming a pattern by using a photomask having both a minute aperture where the main component of a transmitted light is an evanescent light and an aperture where the main component of a transmitted light is a propagating light, comprising the steps of forming a photoresist with a film thickness equal to or smaller than a width of the minute aperture on a substrate to be processed, and exposing the photoresist by an incident light for exposure.

Abstract: The present invention is directed to a method of attaching a leadframe to a singulated good die using a wet film adhesive applied in a predetermined pattern on the active surface of the good die, the lead finger of a leadframe, or both. By applying the adhesive only to identified good dice, time and material are saved over a process that applies adhesive to the entire wafer. By attaching the leadframe to the good die with a wet film, it is possible to remove the leadframe from the good die for rework if the good die subsequently tests unacceptable.

Abstract: The method for improving circuit location assignment is capable of operating in the boolean, electrical and spatial (location) domains. Optimization of location assignment parameters can be performed simultaneously by determining a subset of nets or paths and generating sets of motions to improve these nets or paths. Once sets of motions have been generated, they are tested to determine the most beneficial movement for improving the given circuit parameter (e.g., wireability, timing, etc.).

Abstract: A method of testing an integrated circuit having a layout structure which includes a plurality of branch structures, the method comprising the steps of: (A) generating a control current in response to an input reference; (B) establishing a respective branch current through each of the plurality of branch structures when a process bias supports fabrication of a respective predetermined dimension associated with the branch structures; and (C) generating, in response to the branch currents, an output indicative of the process bias obtained during fabrication of the layout structure.

Abstract: Apparatus and methods of packaging and testing die. In one embodiment, a stacked die package includes a packaging substrate having a first surface with a recess disposed therein and a plurality of conductive leads coupled thereto, a first die attached to the packaging substrate within the recess and having a plurality of first bond pads electrically coupled to at least some of the conductive leads, and a second die attached to the first die and having a plurality of second bond pads that are electrically coupled to at least some of the conductive leads. When the stacked die package is engaged with, for example, a circuit board, the first surface of the packaging substrate is proximate the circuit board so that the packaging substrate at least partially encloses and protects the first and second die. The properties and dimensions of the packaging substrate are tailored to optimize the operational environment of the die, including improving thermal dissipation and enhancing performance of the die.

Abstract: A drop-in test structure fabricated upon a virtual integrated circuit elevational profile and a method for using the drop-in test structure for characterizing an integrated circuit production methodology and integrated circuit fabrication equipment are described. According to an embodiment, the test structure may be fabricated upon an elevational profile corresponding elevationally to a complete or substantially complete production integrated circuit topography. According to an alternative embodiment, the test structure may be fabricated upon an elevational profile corresponding elevationally to a partially complete production topography. The test structure and method may be used to characterize the underlying elevational profile and to identify both systematic and random defects either as part of routine monitoring or in response to the observance of defective chips using other monitoring.

Abstract: A method and apparatus for collecting defect includes forming a defect collecting structure on a wafer such that any residue defects tend to settle on the defect collecting structure instead of the circuit patterns. The defect collecting structure can be located within the die or on the scribelines between the dies. When the defect collecting structure is located in a die, it should have dimensions significantly larger than the dimensions of the surrounding circuits patterns. The defect collecting structure can include a plurality of defect collecting structures. The defect collecting structures can be contiguous or non-contiguous. The defect collecting structure(s) can occupy one hundredth of one percent of the die or more. The defect collecting structures can be created on a wafer by coating, exposing, developing, and optionally, detecting defects. The wafer is exposed with a mask that includes a pattern for the defect collecting structure(s).

Abstract: A pattern and method of a metal line package level test for a semiconductor device, which is capable of efficiently testing characteristic of a metal line. The metal line package level test pattern includes a metal line for test, a current applying pad which is connected to both ends of the metal line, for applying a current to the metal line, a voltage sensing pattern formed at both ends of the metal line, for sensing a voltage of the metal line, and a heater for varying the temperature of the current applying pad.

Abstract: A compound semiconductor device is formed having a plurality of FETs exhibiting the same electrode ratio of a difference between a surface area of the active region and the combined overlapping surface area of the source and drain ohmic electrodes to the combined overlapping surface area of the source and drain ohmic electrodes. As such, precise control of a threshold voltage of the FETs is achieved. The compound semiconductor device is also formed so as to include a plurality of resistors having the same ratio of a difference between a surface area of the resistivity region and the combined overlapping surface area of the pair electrodes to the combined overlapping surface area of the pair electrodes. In this manner, a resistivity of the resistor is precisely controlled.

Abstract: A control method of semiconductor manufacturing equipment allows early detection of deterioration in the equipment. After cleaning the upper surface of an SOI layer (3), a silicon oxide film (4) is formed thereon by thermal oxidation. At this time, deterioration of a cleaning bath or an oxidation furnace causes the mixing of impurities (5) into a monitor wafer (50). Since the SOI wafer (3) has little gettering capabilities and the monitor wafer (50) has no impurity trap region, most of those impurities (5) are stored in the silicon oxide film (4), etc. The stored impurities (5) cause anomalies in the thickness or quality of the silicon oxide film (4), so that the evaluated characteristics of the silicon oxide film (4) vary from the normal. Accordingly, deterioration in the semiconductor manufacturing equipment can be judged when the characteristics of the silicon oxide film (4) vary from the normal.

Abstract: A contact structure for achieving an electrical connection with a contact target is formed by producing contactors on a semiconductor substrate by a microfabrication technology. The contact structure is formed of a contact substrate and a plurality of contactors mounted on the contact substrate. Each of the contactors has a sphere contact to contact with the contact target when the contact structure is pressed against the contact target. A spring force is generated when the contactor is pressed against the contact target. Various types of contact structures and the production method thereof are also described.

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.

Abstract: A structure suitable for aligning two patterned conductive layers that are separated by a dielectric layer is described. Included in the lower pattern is a square and, as part of the upper pattern, four T-shaped capacitor electrodes are provided. The latter are positioned so that, when the alignment is exact, they all overlap the square by the same amount. Thus, under conditions of exact alignment, the capacitance value measured between any one of the top electrodes and the square will be the same for all electrodes. When, however, misalignment occurs, the degree of overlap will change, increasing on one side of the square while decreasing at the opposite side. In this way a comparison of measured capacitance values between electrodes located on opposing sides of the square will indicate whether, and what extent, misalignment has occurred.

Abstract: Ferroelectric switching properties are severely degraded in a hydrogen ambient atmosphere. By controlling the polarity of the capacitors in a ferroelectric memory during the manufacturing process, the amount of degradation can be significantly reduced. After metalization of a ferroelectric memory wafer, all of the ferroelectric capacitors are poled in the same direction. The polarization vector is in a direction that helps to counteract hydrogen damage. A hydrogen gas anneal is subsequently performed to control underlying CMOS structures while maintaining ferroelectric electrical properties. The wafer is then passivated and tested.

Abstract: A wafer level IC structure and a method of manufacturing this wafer level IC structure are proposed, which can help increase the yield of the IC manufacture. The wafer level IC structure is constructed on a semiconductor wafer which is defined into a plurality of discrete IC blocks on the wafer, each IC block being used to form a plurality of IC components such as memory cells. A multi-layer interconnect structure is formed to electrically interconnect these IC components in each of the IC blocks. A first testing and repair process is then perform to disconnect any inoperative IC components from active use. This completes the fabrication stage of the manufacture process. In the subsequent packaging stage, a redistribution line structure is formed to interconnect the discrete IC blocks into an integral functional unit. A second testing and repair process is then perform to disconnect any inoperative IC blocks from active use.

Abstract: Improved techniques for quantifying proximity effects during fabrication of integrated circuits are disclosed. The improved techniques use active features formed on a semiconductor wafer to quantify proximity effects. According to the improved techniques, a device performance quantity for an active feature is measured, and then a feature length for the active feature is determined in accordance with the measured device performance quantity. The fabrication processing can then be evaluated and/or compensated based on the determined feature length. In one example, the active feature can be a metal-oxide semiconductor (MOS) transistor and the device performance quantity can be current.

Abstract: The invention relates to a method of manufacturing, on a silicon wafer, a plurality of integrated circuits and at least one test circuit, comprising steps of insulation of the silicon wafer by means of a reticle disposed in an exposure chamber provided with a diaphragm which allows to hide the non useful parts of the reticle. According to the invention, the method comprises an insulation (exposure) step performed by means of a reticle (130) comprising an insulation mask region (132) for integrated circuits together with at least one insulation mask region (133, 134, 135) for a test circuit. The insulation step includes one or more insulation steps during which the insulation mask region for test circuit is hidden by the diaphragm, and at least one insulation step during which the insulation mask region for test circuit is uncovered by the diaphragm, while all or part of the insulation mask for integrated circuit is hidden by the diaphragm.

Abstract: A gate array integrated circuit wafer is formed having M-N generic metal interconnection layers and having performance and/or electrical testing circuits which are operative using only the M-N generic metal interconnection layers. The performance and electrical testing circuits are located in the active chip area and/or in the scribe line area between dies on the wafer. Performance and/or electrical tests are performed after generic fabrication is completed, but before the final customization of the wafers. Wafers are sorted and assigned to performance and/or yield bins based upon the results of the performance and/or electrical tests. The contents of different bins are provided to different customers for addition of the final N application specific metal interconnection layers based upon the customer's performance and/or yield requirements.

Abstract: Process monitoring circuitry according to the invention incorporates additional routing structures that approximate signal delays due to long metal routing paths. The additional process monitor circuitry builds upon existing approaches without increasing the die size of an integrated circuit through the utilization of excess silicon space available between the bonding pads and the scribe lines of an integrated circuit wafer. More specifically, supplemental metal routing lines and vias are included in the delay paths of process monitor circuitry and located on the integrated circuit such that impact to other metal signal lines/vias used in the actual design is minimized. The supplemental metal routing lines are disposed in unused routable silicon space, such that no silicon area penalty is suffered as a result of having long metal routing lines.

Abstract: A test device for testing an integrated circuit fabricated according to a process is disclosed. The device includes a layout structure, and a excitation circuit. The layout structure includes a plurality of branch structures which are arranged in parallel. Each branch structure includes a feature having a predetermined dimension. The dimension of the feature between associated with adjacent branch structures increases/decreases so as to cover an entire, predetermined spectrum or range of predetermined minimum dimensions. The feature is present (i.e., formed) in a respective branch structure when the process bias/resolution supports fabrication of that dimension. Otherwise, that feature is absent. The excitation circuit is adapted to provide a current through each branch structure to the extent the feature in the branch structure is present. All the branch currents are collected at a common node. If the feature is absent, the current will not be carried, and will thus not contribute to the total current.

Abstract: A method of manufacturing integrated circuits based on providing a test column of memory cells in the devices. Cells in the test column are selected by a portion of the addresses which identifies a row in the main array on the device. A test is executed to determine a characteristic of the device, and the results of that test are mapped to the portion of the address which identifies a row in the array. This produces a characteristic code address for the device which indicates the results of the test. Access to the test column on the device is enabled, and a bit is written in response to the characteristic code address in a memory cell on the test column. During manufacture the test column is read in order to classify the device according to the characteristic.

Abstract: In a semiconductor device fabrication process, a first semiconductor device is constructed with a gate electrode and an active (e.g., source/drain) region. The thickness of the active region is determined. A second semiconductor device is constructed with the same gate electrode and active region dopant concentrations as the first device and is generally the same as the first device except for the thickness of the gate electrode. Using the determined thickness of the active region of the first device, the thickness of the gate electrode of the second device is controlled so that it differs from the thickness of the active region of the second device by a desired amount.

Abstract: The present invention is directed to a method of attaching a leadframe to a singulated good die using a wet film adhesive applied in a predetermined pattern on the active surface of the good die, the lead finger of a leadframe, or both. By applying the adhesive only to identified good dice, time and material are saved over a process that applies adhesive to the entire wafer. By attaching the leadframe to the good die with a wet film, it is possible to remove the leadframe from the good die for rework if the good die subsequently tests unacceptable.

Abstract: A method and system for manufacturing integrated circuit devices having multiple memory units embedded therein. Initially, a single reusable configurable test circuit is fabricated within an integrated circuit device. A number and type of each memory unit embedded within the integrated circuit device are then identified. Finally, the single reusable configurable test circuit is configured, in response to the identifying of a number and type of each memory unit, such that only one test circuit is required for use with multiple integrated circuit devices having multiple diverse memory units embedded therein. The single reusable configurable test circuit can be placed within or outside a fixed core of the integrated circuit device. In addition, the single reusable configurable test circuit can include array built-in self test (ABIST) controller which includes a hierarchical memory configuration that includes a state machine, address counter, compare register and data pattern generator.

Abstract: The present invention advantageously provides a test structure and method for determining how lithographic patterning of transistor gate conductors laterally spaced from conductors affects the operation of transistors which employ the gate conductors. The test structure includes a sequence of gate conductors interposed above and between a respective sequence of source and drain regions. The test structure further includes a sequence of conductors which have been patterned from the same material as the gate conductors. The conductors are spaced an increasing distance from respective gate conductors. The gate conductors extend beyond the respective source and drain regions by varying distances or by the same distance. Lithographic patterning of the gate conductors and the conductors may result in the edges of the gate conductors and the conductors being substantially round and absent of sharp corners.