Abstract: According to one embodiment, a semiconductor storage device includes an organic board provided with external connection terminals on one surface and formed as an individual piece into a plane shape substantially identical to that of an area where the external connection terminals are provided, a lead frame having a mounting area positioned relative to the organic board, and a semiconductor memory chip bonded to the mounting area.

Abstract: In some embodiments, a semiconductor package can include: (a) a base having a cavity; (b) an interposer coupled to the base and at least partially over the cavity such that the interposer and the base form a back chamber, the interposer has a first opening into the back chamber; (c) a micro-electro-mechanical system device located over the interposer at the first opening; and (d) a lid coupled to the base. Other embodiments also are disclosed.

Abstract: Systems and methods according to embodiments of the invention enable flip chip packaging using high density routing while minimizing the thickness and layer count of the flip chip package. By using a photoresist layer to create very fine traces on a metallic base layer, embodiments of the present invention combine advantages of leadframe substrates and laminate substrates by supporting high-density routing while minimizing layer count and manufacturing cost. Additionally, the use of raised metallic pads in a routing layer enables embodiments of the present invention to include highly compact traces that pass over IC die bond pad connection sites without directly coupling to these bond IC die bond pad connection sites. Further, embodiments of the present invention can support multiple thin routing layers without the need for organic (e.g., laminate) material separating these routing layers.

Abstract: A method of manufacturing a semiconductor device, includes the steps of mounting a lead frame in a recessed portion of a lower die, bringing the lower die and an upper die to overlap each other so that a portion for sliding the lead frame slides the lead frame toward injection surfaces, the sliding portion being formed on the recessed portion of the lower die or on the recessed portion of the upper die, clamping the lower die and the upper die together so that at least one projection formed on the upper die crushes down an end portion of the lead frame so as to form lateral projections on the left and right sides of the gate, the lateral projections blocking up the gap between the injection surfaces and the lead frame, and injecting a molding resin through the gate.

Abstract: An LED package and a fabrication method thereof are provided. The LED package includes an upper metal plate having an LED-receiving hole therein; a lower metal plate disposed under the upper metal plate; and an insulator which the upper metal plate and the lower metal plate from each other. A portion of the lower metal plate is exposed via the LED-receiving hole and an LED is mounted on the exposed portion of the lower metal plate and is electrically connected to both of the upper and lower metal plates. A protective cover encloses and protects exposed surfaces of the upper and lower metal plates.

Abstract: The present invention provides a Quad Flat Non-leaded (QFN) package, which comprises a chip, a lead frame, a plurality of composite bumps and an encapsulant. The chip has a plurality of pads, and the lead frame has a plurality of leads. Each of the plurality of composite bumps has a first conductive layer and a second conductive layer. The first conductive layer is electrically connected between one of the pads and the second conductive layer, and the second conductive layer is electrically connected between the first conductive layer and one of the leads. The encapsulant encapsulates the chip, the leads and the composite bumps. Thereby, a QFN package with composite bumps and a semi-cured encapsulant is forming between the spaces of leads of lead frame before chip bonded to the lead frame are provided.

Abstract: A microelectronic assembly includes an interconnection element, a conductive plane, a microelectronic device, a plurality of traces, and first and second bond elements. The interconnection element includes a dielectric element, a plurality of element contacts, and at least one reference contact thereon. The microelectronic device includes a front surface with device contacts exposed thereat. The conductive plane overlies a portion of the front surface of the microelectronic device. Traces overlying a surface of the conductive plane are insulated therefrom and electrically connected with the element contacts. The traces also have substantial portions spaced a first height above and extending at least generally parallel to the conductive plane, such that a desired impedance is achieved for the traces. First bond element electrically connects the at least one conductive plane with the at least one reference contact. Second bond elements electrically connect device contacts with the traces.

Abstract: An electronic device can include a packaging material having a first surface and a second surface opposite the first surface, and leads including die connection surfaces and external connection surfaces. The electronic device can further include a trench extending from an upper surface of the packaging substrate towards a lower surface of the packaging substrate, wherein a set of leads lie immediately adjacent to the trench, and the packaging material is exposed at the bottom of the trench. In an embodiment, an encapsulant is formed over the upper surface of the packaging substrate and within the trench. In a particular embodiment, the trenches may be formed before or after placing a die over the packaging substrate, or before or after forming electrical connections between the die and leads of the packaging substrate.

Abstract: Methods and apparatus for improved electromagnetic interference (EMI) shielding and thermal performance in integrated circuit (IC) packages are described. A die-up or die-down package includes a protective lid, a plurality of ground posts, an IC die, and a substrate. The substrate includes a plurality of ground planes. The IC die is mounted to the substrate. Plurality of ground posts is coupled to plurality of ground planes that surround IC die. Protective lid is coupled to plurality of ground posts. The plurality of ground posts and the protective lid from an enclosure structure that substantially encloses the IC die, and shields EMI from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.

Abstract: An integrated circuit package that comprises a lead frame 105, an integrated circuit located on the lead frame and a shunt resistor coupled to the integrated circuit. The shunt resistor has a lower temperature coefficient of resistance than the lead frame, and the lead frame has a lower resistivity than the shunt resistor. The shunt resistor has a low-resistance coupling to external leads of the lead frame, or, the shunt resistor has its own integrated external leads.

Abstract: A semiconductor component having wetable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. A portion of at least one leadframe lead is exposed and an electrically conductive material is formed on the exposed portion. The mold compound is separated to form singulated semiconductor components.

Abstract: A method for packaging one or more power semiconductor devices is provided. A lead frame comprising one or more base die paddles, multiple lead terminals, and a tie bar assembly is constructed. The lead terminals extend to a predetermined elevation from the base die paddles. The base die paddles are connected to the lead terminals by the tie bar assembly. The tie bar assembly mechanically couples the base die paddles to each other and to the lead terminals. The tie bar assembly is selectively configured to isolate the lead terminals from the base die paddles and to enable creation of multiple selective connections between one or more of the lead terminals and one or more power semiconductor devices mounted on the base die paddles, thereby enabling flexible packaging of one or more isolated and/or non-isolated power semiconductor devices and increasing their power handling capacity.

Abstract: A module and a method for manufacturing a module are disclosed. An embodiment of a module comprises a first semiconductor device, a frame arranged on the first semiconductor device, the frame comprising a cavity, and a second semiconductor device arranged on the frame wherein the second semiconductor device seals the cavity.

Abstract: A metal sheet is patterned into a leadframe that includes metal wiring structures one side and metal pads arranged for ball grid array (BGA) style connection on the other side. A semiconductor chip is bonded to the leadframe, for example, by solder balls that are reflowed onto the side of the leadframe that includes the metal wiring structures. The metal wiring structures provide interconnection among solder balls as needed. Peripheral portions of the leadframe are removed. The bonded structure is embedded in a dielectric molding compound that embeds, and provides mechanical support for, lead structures and the solder balls. The composite structure including the bonded structure and the dielectric molding compound can be bonded to a substrate employing an array of BGA balls that is bonded to the metal pads of the lead structures embedded in the dielectric molding compound.

Abstract: A power semiconductor module includes a power semiconductor die, a metal substrate, a patterned metallization layer, a plurality of padless electrical connections, a plurality of vias and an inductor. The power semiconductor die has a top surface, an opposing bottom surface and a plurality of sides extending between the top and bottom surfaces. The metal substrate is attached to the bottom surface of the die. The patterned metallization layer is disposed above the top surface of the die. The plurality of padless electrical connections are at the top surface of the die and connect the patterned metallization layer to the die. The plurality of vias are disposed adjacent one or more of the sides of the die and electrically connected to the patterned metallization layer at a first end of the plurality of vias and to the metal substrate at a second end of the plurality of vias.

Abstract: A conduction path includes a first conduction path forming plate (11) made of a first metal and having a through hole (13), and a second conduction path forming plate (15) made of a second metal and having a press-fit portion (17) press-fitted into the through hole. A wall surface of the through hole and a side surface of the press-fit portion forms an inclined bonding surface (18) inclined relative to a normal line of an overlap surface of the first conduction path forming plate and the second conduction path forming plate, and a bonding portion (25) formed by metal flow is formed in a region located in a periphery of the inclined bonding surface.

Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a wafer containing an interconnect structure. The interconnect structure includes a plurality of vias and interconnect lines. The semiconductor device includes a first conductive pad disposed over the interconnect structure. The first conductive pad is electrically coupled to the interconnect structure. The semiconductor device includes a plurality of second conductive pads disposed over the interconnect structure. The semiconductor device includes a passivation layer disposed over and at least partially sealing the first and second conductive pads. The semiconductor device includes a conductive terminal that is electrically coupled to the first conductive pad but is not electrically coupled to the second conductive pads.

Abstract: A light-emitting semiconductor device includes a lead frame having lead electrodes, a reflector arranged with the lead frame, and a light-emitting semiconductor chip accommodated in the reflector and having electrodes connected to the lead electrodes by a flip-chip bonding method, wherein: a gap between the lead frame and the light-emitting semiconductor chip is filled with a cured underfill material, and a cured silicon oxide film of 0.05 to 10 ?m thickness is formed covering surfaces of the light-emitting semiconductor chip and reflector.

Abstract: A high positional accuracy of a semiconductor chip is attained to stabilize the quality of a semiconductor device. In a die bonding process during assembly of an SIP, a microcomputer chip not required to have a high positional accuracy is picked up with a surface non-contact type collet and is die-bonded onto a first chip mounting portion, thereafter, an ASIC chip required to have a high positional accuracy is picked up with a surface contact type collet and die-bonded onto a second chip mounting portion. By thus using two types of collets properly, not only a high positional accuracy of the ASIC chip which has been die-bonded with the surface contact type collet is attained, but also the quality of the SIP is stabilized.

Abstract: A lead frame having improved connectivity with a molded portion and a method of manufacturing the lead frame are provided. The lead frame includes a die pad on which a semiconductor chip is to be disposed; at least one lead portion arranged to be connected to the semiconductor chip; and at least one plating layer formed on at least one of the at least one lead portion and the die pad, wherein a top surface of the at least one plating layer has an uneven portion having a first average surface roughness.

Abstract: In one embodiment, a leadless package includes down-set conductive leads having base portions. The base portions include stand-offs that attach to electrodes on an electronic chip using, for example, a solder die attach material. An optional encapsulating layer covers portions of the down-set conductive leads and portions of the electronic chip while leaving pad portions of the down-set conductive leads and a surface of the electronic chip exposed. The pad portions and the surface of the electronic chip are oriented to attach to a next level of assembly.

Abstract: In one embodiment, an integrated circuit package includes a lead frame with a die paddle and several leads. Portions of the lead frame not having an external electrical connection may be thinned such that they may be encapsulated by an electrically insulating packaging material on the back of the lead frame. Portions of the lead frame having external electrical connections may have a thickness such that they are exposed through the packaging material. The lead frame may be covered by an electrically insulating cover to protect components on the lead frame from erroneous electrical contact or electro-static discharge (ESD) damage.

Abstract: An LED package includes a die pad having a bottom surface, an upper surface and a centrally located recessed cavity. The recessed cavity has a chip attach surface between the bottom surface and upper surface and sidewalls that extend from the recessed chip attach surface to the upper surface. The package additionally has leads arranged on opposing sides of the die pad. The leads have a bottom surface that is coextensive with the bottom surface of the die pad and an upper surface coextensive with the upper surface of the die pad. An LED chip is attached to the chip attach surface. The package further includes a package body having an encapsulant which fills space between the die pad and leads forming a bottom encapsulant surface that is coextensive with the bottom surfaces of the die pad and leads.

Abstract: According to one embodiment, a semiconductor memory device including an organic substrate with an external connection terminal and a semiconductor memory chip. The semiconductor memory device further includes a lead frame having a bonded portion and an installation portion. It further includes a resin mold for sealing the semiconductor memory chip. The lead frame is provided with a plurality of extensions at least from one of the installation portion and the bonded portion, in a way of extending at least to two or more sides of the resin mold.

Abstract: This invention relates to a module including a semiconductor chip, at least two contact elements and an insulating material between the two contact elements. Furthermore, the invention relates to a method for production of such a module.

Abstract: In one embodiment, a method is provided for packaging a semiconductor die. A leadframe having a die-pad and one or more lead-pads is placed (502) on an assembly surface. The die-pad has a base portion (202) resting on the assembly surface, an upper portion (204) on the base portion extending laterally from the base portion, and a support arm (208) extending from and supporting the upper portion of die-pad. A semiconductor die (206) is wirebonded (504) to a top surface of the upper portion of the die-pad. The semiconductor die is wirebonded (506) to the one or more lead-pads (210). The semiconductor die and leadframe are encased (508) in a package material (802). The package material fills a space between the upper portion of the die-pad and the assembly surface. A portion of the support arm located in a cutting lane is removed (512).

Abstract: Disclosed is a discrete semiconductor device package (100) comprising a leadframe portion (10) comprising a recess (14) having a depth substantially equal to the thickness of the discrete semiconductor device (20), wherein a raised portion of the leadframe portion adjacent to said recess defines a first contact area (12); a discrete semiconductor device (20) in said recess, wherein the exposed surface (22) of the discrete semiconductor device defines a second contact area; a protective layer (30) covering the leadframe portion and the a discrete semiconductor device but not the first contact area and the second contact area; and respective plating layers (40) covering the first contact area and the second contact area. A method of manufacturing such a package and a carrier comprising such a package are also disclosed.

Abstract: A combination for electrically connecting an integrated circuit (14) to a lead frame package (18) comprises a first jumper chip (16) and a plurality of bonding wires (20) including at least a first bonding wire and a second bonding wire. The first bonding wire extends between and electrically connects the first jumper chip (16) and the lead frame package (18). Additionally, the second bonding wire extends between and electrically connects the first jumper chip (16) and the integrated circuit (14). The plurality of bonding wires (20) can further include a third bonding wire that extends between and electrically connects the integrated circuit (14) and the lead frame package (18). Further, the combination can also comprise a second jumper chip (216B), and the plurality of bonding wires (20) can further include a third bonding wire and a fourth bonding wire. The third bonding wire can extend between and electrically connect the second jumper chip (216B) and the lead frame package (18).

Abstract: According to one embodiment, there is provided a semiconductor device including a wiring board, a semiconductor chip mounted on a first surface of the wiring board, first external electrodes provided on the first surface of the wiring board, second external electrodes provided on a second surface of the wiring board, and a sealing resin layer sealing the semiconductor chip together with the first external electrodes. The sealing resin layer has a recessed portion exposing a part of each of the first external electrodes. The plural semiconductor devices are stacked to form a semiconductor module with a POP structure. In this case, the first external electrodes of the lower-side semiconductor device and the second external electrodes of the upper-side semiconductor device are electrically connected.

Abstract: There is provided a technology capable of suppressing the damage applied to a pad. When the divergence angle of an inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is very small in magnitude. In other words, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is sufficiently smaller in magnitude than the ultrasonic conversion load in a direction in parallel with the surface of the pad. Consequently, when the divergence angle of the inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad can be sufficiently reduced in magnitude, which can prevent pad peeling.

Abstract: A manufacturing method of a non-leaded package structure is provided. An upper surface and a lower surface of a metal base plate are patterned so as to form a plurality of first protruding parts and at least a second protruding part on the upper surface and to form a plurality of first recess patterns on the lower surface corresponding to the first protruding parts. A first solder layer is formed in each of the first recess patterns respectively. A chip is mounted on the second protruding part and electrically connected to the first protruding parts with a plurality of bonding wires. An encapsulant is formed on the upper surface. A back etching process is performed on the lower surface to partially remove the metal base plate until the encapsulant is exposed and a lead group including at least a die pad and a plurality of leads is defined.

Abstract: The package structure includes a metal sheet having a first central block, a plurality of first metal blocks, a second central block and a plurality of second metal blocks, a first finish layer and a second finish layer, at least a chip disposed on the metal sheet and a package body encapsulating the chip. The package structure may further include at least an area block for wire routing.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, a peripheral lead horizontal ridge, and a peripheral lead conductive plate, the peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a first top distribution layer on the peripheral lead top side, the first top distribution layer having a first top terminal; connecting an integrated circuit to the first top distribution layer, the integrated circuit having a central portion directly over a plurality of the first top terminal; and applying an insulation layer directly on a bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge.

Abstract: The present technology is directed generally to a semiconductor device. In one embodiment, the semiconductor device includes a first vertical transistor and a second vertical transistor, and the first vertical transistor is stacked on top of the second vertical transistor. The first vertical transistor is mounted on a lead frame with the source electrode of the first vertical transistor coupled to the lead frame. The second vertical transistor is stacked on the first vertical transistor with the source electrode of the second vertical transistor coupled to the drain electrode of the first vertical transistor.

Abstract: Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package with a stamped leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked atop a source of the III-nitride transistor, and a stamped leadframe comprising a first bent lead coupled to a gate of the III-nitride transistor and the anode of the diode, and a second bent lead coupled to a drain of the III-nitride transistor. The bent leads expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.

Abstract: The relay member is at least partly positioned between the semiconductor chip and lead in the plan view, and metal pieces insulated from one another are arranged on the surface. At least either of the first wire and the second wire has their respective other ends and joined to at least one of the metal pieces arranged on the surface of the relay member. Also, the first wire and the second wire have their respective other ends and joined to each other at that part of the relay member which is between the semiconductor chip and the lead. The foregoing structure is highly reliable and versatile for wire connection.

Abstract: A leadframe including a die pad, leads, an outer frame, connecting bars and grounding bars is provided. Each of the grounding bars is suspended between two connecting bars by being connected with branches of the two connecting bars, such that the grounding bars are spaced by the die pad. The leadframe and the chip package of the present invention can permit a great design variation.

Abstract: A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.

Abstract: Disclosed are systems and methods for improving the thermal performance of integrated circuit packages. Aspects of the present invention include improved thermal package structures and methods for producing the same through the application of one or more thermal spreaders in the package. In embodiments, a thermal spreader is incorporated in a semiconductor chip package between a semiconductor die and its die pad. By including a thermal spreader in an IC package, the package can handle higher levels of power while maintaining approximately the same temperature of the package or can reduce the temperature of the package when operating at the same power level, as compared to a package without a thermal spreader.

Abstract: A pallet (501) supporting a half-etched leadframe with cantilever-type leads (403) without metallic supports during the step of attaching components (510) to the leads in order to assemble an electronic system. After assembly, the pallet is removed before the molding step that encapsulates (601a) the components on the leadframe and mechanically supports (601b) the cantilever leads. The pallet is machined from metal or inert plastic material, tolerates elevated temperatures during soldering, and is reusable for the next assembly batch.

Abstract: An integrated circuit package on package system includes: providing a lead having a wire-bonded die with a bond wire connected thereto; mounting a fan-in interposer over the wire-bonded die and the bond wire; connecting the fan-in interposer to the lead with the bond wires; and encapsulating the wire-bonded die, bond wires, and the fan-in interposer with an encapsulation leaving a portion of the fan-in interposer exposed.

Abstract: A method includes: forming a photoresist pattern to form each of a semiconductor element mounting section on which a semiconductor element is mounted, semiconductor element electrode connection terminals for connection with electrodes of the semiconductor element, and a first outer frame section on a first surface of a metal plate; forming a photoresist pattern to form each of external connection terminals, a second outer frame section, and grooves in at least a part of the second outer frame section on a second surface of the metal plate; etching a metal plate exposing section, in which the metal plate of the second surface is exposed, to form holes that do not pass through the metal plate exposing section and grooves that run from an inside to an outside of the second outer frame section; coating a pre-mold resin on the holes and the grooves, and heating the pre-mold resin under pressure using a flat-bed press to form a resin layer; and etching the first surface to form the semiconductor element mounting se

Abstract: A packaged semiconductor device includes a semiconductor die including a substrate having a topside including active circuitry and a bottomside with at least one backside metal layer directly attached. A package including a molding material having a die pad and a plurality of leads is encapsulated within the molding material, wherein the leads include an exposed portion that includes a bonding portion. The topside of the semiconductor die is attached to the die pad, and the package includes a gap that exposes the backside metal layer along a bottom surface of the package. Bond wires couple pads on the topside of the semiconductor die to the leads. The bonding portions, the molding material along the bottom surface of the package, and the backside metal layer are all substantially planar to one another.

Abstract: Embodiments of the invention relate to methods for semiconductor chip package assembly. An embodiment of the invention includes providing a metallic leadframe with a chip mounting surface and a plurality of leadfingers. The leadfingers have a proximal end for receiving one or more wirebonds and a distal end for providing an electrical path from the proximal end. One or more of the leadfingers also has an offset portion and underlying heat spreader, increasing the stiffness of the leadfinger, and increasing leadfinger deflection-resistance and spring-back. The offset is in the direction opposite the plane of a heat spreader thermally coupled to the mounting surface. A semiconductor chip is affixed to the mounting surface and a plurality of bond pads of the chip are wirebonded to the offset portions of the proximal ends of individual leadfingers. The chip, the bondwires, portions of the heat spreader and leadfingers are encapsulated.

Abstract: A power supply module and a packaging and integrating method thereof are provided. The power supply module includes a lead frame, a passive element, an integrated circuit (IC), and a power switch Metallic Oxide Semiconductor Field Effect Transistor (MOSFET). The passive element is soldered onto the lead frame by using the surface mount technology. The IC is a flip chip and is mounted and soldered onto the lead frame.

Abstract: The present invention discloses an integrated circuit (IC) chip package and a manufacturing method thereof. The IC chip package includes: a lead frame, including a lead frame array having plural conductive cells, wherein some of the conductive cells are respectively electrically connected with corresponding first extended wires; at least one redistribution layer, wherein each redistribution layer includes plural second extended wires, which are respectively electrically connected to the first extended wires or the second extended wires of another redistribution layer; and a solder array, including plural solder balls, which are electrically connected to the lead frame array.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are disclosed. An embodiment comprises forming a bump on a die, the bump having a solder top, melting the solder top by pressing the solder top directly on a contact pad of a support substrate, and forming a contact between the die and the support substrate.

Abstract: A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element.

Abstract: The present technology discloses a multi-die package. The package comprises a lead frame structure and three dies including a first flip chip die, a second flip chip die and a third flip chip die stacked vertically. The first flip chip die is mounted on the bottom surface of the lead frame structure through the flip chip bumps; the second flip chip is mounted on the top surface of the first flip chip die through flip chip bumps; and the third flip chip die is mounted on the top surface of the lead frame structure through flip chip bumps.

Abstract: The method for producing a resin package according to the present invention includes a step of forming a copper oxide layer by oxidizing the surface of a lead frame in which at least the surface is made of copper, and a step of forming a resin package main unit by allowing a resin to adhere to the copper oxide layer on the lead frame surface by resin molding for package, and then removing a predetermined area of the copper oxide layer with an acidic solution.