Metallic Housing Or Support Patents (Class 438/121)
  • Patent number: 10332853
    Abstract: A bonding structure (100) of the present invention includes a substrate (110), a metal film (120), a semiconductor element (130). The substrate (110), the metal film (120), and the semiconductor element (130) are laminated in order just mentioned. The metal film (120) contains a metal diffused through stress migration, and the substrate (110) and the semiconductor element (130) are bonded together with the metal film (120) therebetween.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: June 25, 2019
    Assignee: OSAKA UNIVERSITY
    Inventors: Katsuaki Suganuma, Shijo Nagao, Chulmin Oh
  • Patent number: 10312213
    Abstract: The invention relates to a power semiconductor device with a substrate with a cooling device and power semiconductor components connected thereon, having load current terminal elements and a cooling device. Pressure devices have a pressure element is arranged movably in a direction normal (N) to the substrate, and an elastic deformation element between the pressure element and a load current terminal element. The pressure element presses the assigned load current terminal element against an electrically conductive contact area of the substrate via the elastic deformation element and provides electrically conductive pressure contacting of the assigned load current terminal element with the substrate. The electrical connection of the power semiconductor device is improved.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: June 4, 2019
    Assignee: SEMIKRON ELEKTRONIK GMBH & CO. KG
    Inventors: Markus Beck, Alexander Schneider, Hartmut Kulas, Patrick Graschl, Christian Zeller
  • Patent number: 9786644
    Abstract: Provided is a method of fabricating a semiconductor package. The method include providing a lower package with an inner solder ball, providing a conductive material on the inner solder ball to form an outer solder ball enclosing the inner solder ball, providing an upper package with an upper solder ball, on the lower package, performing a first process at a first temperature to join the upper solder ball to the outer solder ball, and performing a second process at a second temperature to unite the upper, inner, and outer solder balls into a connection terminal.
    Type: Grant
    Filed: May 30, 2016
    Date of Patent: October 10, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hongbin Shi, Hojeong Moon, Kang Joon Lee
  • Patent number: 9588140
    Abstract: An inspection probe 16Ai is formed by subjecting a thin sheet material made of a copper alloy to press working. The inspection probe 16Ai includes: a device side plunger 16A having a contact point which selectively comes into contact with an electrode portion DVb of a semiconductor device DV; a board side plunger 16B having a contact point which selectively comes into contact with a contact pad of a printed wiring board 18; a spring portion 16D which biases the device side plunger 16A and the board side plunger 16B in a direction away from each other; and a cylindrical support stem 16C being disposed inside the spring portion 16D, making the spring portion 16D slidable thereon, and being configured to retain straight advancing property of the spring portion 16D.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: March 7, 2017
    Assignee: YAMAICHI ELECTRONICS CO., LTD.
    Inventors: Katsumi Suzuki, Yuji Nakamura, Takeyuki Suzuki, Yukio Ota
  • Patent number: 9431275
    Abstract: A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: August 30, 2016
    Assignee: PFG IP LLC
    Inventors: Randy Bindrup, W. Eric Boyd, John Leon, James Yamaguchi, Angel Pepe
  • Patent number: 9368438
    Abstract: Various embodiments of mechanisms for forming through package vias (TPVs) with multiple conductive layers and/or recesses in a die package and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. One of the multiple conductive layers acts as a protective layer of the main conductive layer of the TPVs. The protective layer is less likely to oxidize and also has a slower formation rate of intermetallic compound (IMC) when exposed to solder. The recesses in TPVs of a die package are filled by solder from the other die package and the IMC layer formed is below the surface of TPVs, which strengthen the bonding structures.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Po-Hao Tsai
  • Patent number: 9362138
    Abstract: An IC package is provided. The IC package comprises a leadframe comprising a metal strip (222) partially etched on a first side. The leadframe may be configured for an IC chip to be mounted thereon and for a plurality of bonding areas (218) to be electrically coupled to the leadframe and the IC chip. The IC chip, the bonding areas, and a portion of the metal leadframe are covered with an encapsulation compound, with a plurality of contact pads (206) protruding from the bottom surface of the leadframe. The bottom surface of the leadframe may be etched one or more times during the manufacturing process to reduce the depth of the undercutting. A method for manufacturing an IC package is also provided.
    Type: Grant
    Filed: November 26, 2009
    Date of Patent: June 7, 2016
    Assignee: Kaixin, Inc.
    Inventor: Tunglok Li
  • Patent number: 9355989
    Abstract: A method of eliminating a defective bonding wire is provided, including moving a bonding member from a first region of a carrier to a second region of the carrier if the bonding wire of the bonding member is defective, and cooperatively operating a movement member and the bonding member so as to cause the defective bonding wire to be removed from the bonding member and bonded to the second region of the carrier, thereby auto-debugging the bonding member and improving the production efficiency.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: May 31, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Wei-Sheng Lin, Lien-Chen Chiang, Lung-Tang Hung, Meng-Hung Yeh, Yude Chu
  • Patent number: 9343367
    Abstract: An integrated device die and package is disclosed. The integrated device die includes a unitary body. The unitary body can have an upper portion comprising one or more active components. The upper portion can have first and second opposing lateral sides defining at least a portion of a periphery of the upper portion such that an upper surface of the upper portion is disposed between upper edges of the first and second opposing lateral sides. The unitary body can also have a lower portion monolithically formed with the upper portion. The lower portion can comprise a pedestal extending downwardly from the upper portion. The pedestal can be laterally inset from lower edges of the first and second opposing lateral sides. The pedestal can include a distal end portion configured to couple to a carrier.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: May 17, 2016
    Assignee: ANALOG DEVICES, INC.
    Inventors: Thomas M. Goida, Xiaojie Xue
  • Patent number: 9310065
    Abstract: In one embodiment, a lamp comprises an optically transmissive enclosure. An LED array is disposed in the optically transmissive enclosure operable to emit light when energized through an electrical connection. A gas is contained in the enclosure to provide thermal coupling to the LED array. A board supports lamp electronics for the lamp and is located in the enclosure. The LED array is mounted to the board and LEDs are mounted on a submount formed to have a three dimensional shape. The board is electrically coupled to the LED array and the submount may be thermally coupled to the gas for dissipating heat from the plurality of LEDs.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: April 12, 2016
    Assignee: Cree, Inc.
    Inventors: Christopher P. Hussell, John Adam Edmond, Gerald H. Negley, Curt Progl, Mark Edmond, Praneet Athalye, Charles M. Swoboda, Antony Paul van de Ven, Paul Kenneth Pickard, Bart P. Reier, James Michael Lay, Peter E. Lopez, Ed Adams
  • Patent number: 9196560
    Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate having a first area and a second area. A first metal layer structure is formed which includes at least a first metal portion in the first area and a second metal portion in the second area. A plating mask is formed on the first metal layer structure to cover the second metal portion, and a second metal layer structure is plated on and in ohmic contact with the first metal portion of the first metal layer structure.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: November 24, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Roman Roth, Frank Umbach
  • Patent number: 9136164
    Abstract: Semiconductor devices and fabrication methods are provided. First metal layers are provided in a substrate including a first region and a second region. An interlayer dielectric (ILD) layer formed over the substrate includes a top surface in the second region coplanar with a bottom of a trench in the ILD layer in the first region. Through-holes are formed in the ILD layer. A polymer layer fills the through-holes and the trench in ILD layer and covers top surface of ILD layer in both regions. The polymer layer is exposed and developed to form vias, each including an upper via in the polymer layer and a lower via in ILD layer. A second metal layer is formed to fill each via on a corresponding first metal layer in both regions. The polymer layer between adjacent second metal layers is removed to form air gaps in the second region.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: September 15, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Xinpeng Wang, Weihai Bu
  • Patent number: 9123617
    Abstract: A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Hsun Wan, Yi-Shin Chu, Szu-Ying Chen, Pao-Tung Chen, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 9041226
    Abstract: In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 26, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Rainer Steiner, Edward Fuergut, Khalil Hosseini, Georg Meyer-Berg, Joachim Mahler
  • Patent number: 9040412
    Abstract: The present invention discloses a three-dimensional vertically interconnected structure and a fabricating method therefor. The structure comprises at least two layers of chips which are stacked in sequence or stacked together face to face. An adhesive material is used for adhesion between adjacent layers of the chips while each layer of the chips contains a substrate layer and a dielectric layer from bottom to top. A front surface of the chip has a first concave, which is filled with metal to form a first electrical conductive ring that connects to microelectronic devices inside the chip via a redistribution layer. A first through layers of chips hole with a first micro electrical conductive pole inside, penetrates the stacked chips. The structure in the present invention enhances the electric interconnection and the bonding between adjacent layers of chips while the instant fabricating method simplifies the process and increases the yield.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: May 26, 2015
    Assignee: PEKING UNIVERSITY
    Inventors: Shenglin Ma, Yunhui Zhu, Xin Sun, Yufeng Jin, Min Miao
  • Publication number: 20150137340
    Abstract: A secure integrated circuit package is provided. The secure integrated circuit package includes a first substrate having an upper surface and a lower surface. A first plurality of solder balls are arranged in a pattern on the lower surface of the first substrate. A die is coupled to the upper surface of the first substrate. A second plurality of solder balls is coupled to the upper surface of the substrate and arranged in a ring surrounding the die. A mesh substrate including a mesh protection grid is coupled to the second plurality of solder balls.
    Type: Application
    Filed: November 13, 2014
    Publication date: May 21, 2015
    Inventors: Mark BUER, Matthew KAUFMANN
  • Patent number: 9035445
    Abstract: A method includes providing a substrate having a seal ring region and a circuit region, forming a seal ring structure over the seal ring region, forming a first frontside passivation layer above the seal ring structure, etching a frontside aperture in the first frontside passivation layer adjacent to an exterior portion of the seal ring structure, forming a frontside metal pad in the frontside aperture to couple the frontside metal pad to the exterior portion of the seal ring structure, forming a first backside passivation layer below the seal ring structure, etching a backside aperture in the first backside passivation layer adjacent to the exterior portion of the seal ring structure, and forming a backside metal pad in the backside aperture to couple the backside metal pad to the exterior portion of the seal ring structure. Semiconductor devices fabricated by such a method are also provided.
    Type: Grant
    Filed: September 23, 2012
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semicondutor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Hsin-Hui Lee, Wen-De Wang, Shu-Ting Tsai
  • Patent number: 9029194
    Abstract: A method of making an integrated circuit module starts with a top leadframe strip comprising a plurality of integrally connected top leadframes. A plurality of flipchip dies are mounted on the top leadframe strip with solder bumps of each flipchip bonded to predetermined pad portions on each of the top leadframes. The top leadframe strip is attached to a bottom leadframe strip. The bottom leadframe strip has a plurality of integrally connected bottom leadframes each having a central die attach pad (DAP) portion and a peripheral frame portion. A back face of each flipchip die contacts the DAP portion of each bottom leadframe. Lead portions of each top leadframe are attached to the peripheral frame portion of each bottom leadframe. The top leadframe strip is attached to the bottom leadframe strip with a back face of each flipchip die contacting the DAP portion of each bottom leadframe and with lead portions of each top leadframe attached to the peripheral frame portion of each bottom leadframe.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: May 12, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Lee Han Meng@Eugene Lee, Anis Fauzi bin Abdul Aziz, Susan Goh Geok Ling, Ng Swee Tiang
  • Patent number: 9029200
    Abstract: A method for manufacturing semiconductor devices is disclosed. In one embodiment a semiconductor substrate having a first surface, a second surface opposite to the first surface and a plurality of semiconductor components is provided. The semiconductor substrate has a device thickness. At least one metallization layer is formed on the second surface of the semiconductor substrate. The metallization layer has a thickness which is greater than the device thickness.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Rudolf Zelsacher, Paul Ganitzer
  • Publication number: 20150115427
    Abstract: A package structure and a packaging method thereof are provided, in which an inductor is integrated into a substrate so as to save a packaging space and thus improve the integration level and packaging effect of the system.
    Type: Application
    Filed: May 18, 2012
    Publication date: April 30, 2015
    Inventors: Guanhua Li, Jing Jiang, Qinwei Peng
  • Patent number: 9018039
    Abstract: A circuit module includes a circuit substrate, at least one mount component, sealing bodies, and a shield. The circuit substrate includes a mount surface. The mount component is mounted on the mount surface. The sealing body is formed on the mount surface, covers the mount component and has a first sealing body section having a first thickness and a second sealing body section having a second thickness larger than the first thickness. The shield covers the sealing body and has a first shield section formed on the first sealing body section and having a third thickness and a second shield section formed on the second sealing body section and having a fourth thickness smaller than the third thickness. The sum of the fourth thickness and the second thickness equals to the sum of the first thickness and the third thickness.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: April 28, 2015
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Eiji Mugiya, Takehiko Kai, Masaya Shimamura, Tetsuo Saji, Hiroshi Nakamura
  • Patent number: 9012268
    Abstract: Embodiments of the present disclosure are directed to leadframe strips and methods of forming packages that include first separating adjacent leads of a leadframe strip and subsequently singulating components into individual packages. In one embodiment, the adjacent leads are separated by etching through the leads, thereby providing electrical isolation of the adjacent packages. In that regard, if desired, the individual adjacent packages may be electrically tested in leadframe strip form. Subsequently, the individual packages are formed by sawing through the encapsulation material.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: Jonathan Jaurigue, Rogelio Real, Francis Ann Llana, Ricky Calustre, Rodolfo Gacusan
  • Patent number: 9012269
    Abstract: Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics PTE Ltd.
    Inventors: Yonggang Jin, Xavier Baraton, Faxing Che
  • Publication number: 20150102383
    Abstract: A press pack module includes a collector module terminal, an emitter module terminal, a gate module terminal, and an auxiliary module terminal. Each IGBT cassette within the module includes a set of shims, two contact pins, and an IGBT die. The first contact pin provides part of a first electrical connection between the gate module terminal and the IGBT gate pad. The second contact pin provides part of a second electrical connection between the auxiliary module terminal and a shim that in turn contacts the IGBT emitter pad. The electrical connection between the auxiliary emitter terminal and each emitter pad of the many IGBTs is a balanced impedance network. The balanced network is not part of the high current path through the module. By supplying a gate drive signal between the gate and auxiliary emitter terminals, simultaneous IGBT turn off in high speed and high current switching conditions is facilitated.
    Type: Application
    Filed: October 15, 2013
    Publication date: April 16, 2015
    Applicant: IXYS Corporation
    Inventors: Ashley Golland, Franklin J. Wakeman, Howard D. Neal
  • Publication number: 20150102481
    Abstract: Within a cassette of a press pack module, a conductive shim is bonded to the backside of a device die by a layer of sintered metal. The die, sintered metal, and shim together form a sintered assembly. The cassette is compressed between a metal top plate member and a metal bottom plate member such that the backside of the assembly is pressed against the top plate member, and such that the frontside of the assembly is pressed against another shim. A central portion of the frontside surface of the die is contacted on the bottom by the other shim, but there is no shim contacting a peripheral portion of the frontside surface. Despite there being no shim in contact with the peripheral portion of the frontside surface, the peripheral portion is in good thermal contact with the top plate member through the sintered metal and the bonded conductive shim.
    Type: Application
    Filed: October 15, 2013
    Publication date: April 16, 2015
    Applicant: IXYS CORPORATION
    Inventors: Stefan Steinhoff, Philip Townsend
  • Publication number: 20150102473
    Abstract: A chip package and a packaging method are provided, which relates to the field of communications technologies, and is invented to implement high-frequency electromagnetic interference shielding and effectively improve chip performance. The package includes a package substrate and a metal cap covering the package substrate, where a silicon chip placement area is arranged on an upper surface of the package substrate, multiple first conductive parts are arranged in a peripheral area of the silicon chip placement area, and an edge of the metal cap is in contact with the package substrate and electrically connected to the multiple first conductive parts, where at least a portion of first conductive parts in the multiple first conductive parts are electrically connected to a grounding part by using the metal cap, and the grounding part is arranged on the package substrate, and configured to ground the package substrate.
    Type: Application
    Filed: December 15, 2014
    Publication date: April 16, 2015
    Inventors: Xuequan Yu, Yadong Bai, Ping Yu
  • Patent number: 9006005
    Abstract: A method of fabricating a light emitting diode device comprises depositing conductive material to cover a portion of surface of a conductive and reflective layer to form a first contact pad, and surfaces between adjacent first trenches to form a second contact pad; and depositing a first passivation layer over uncovered portion of surface of the conductive and reflective layer to form a first planar passivation contact surface between the first contact pad and the second trench and depositing bonding material to cover a portion of surface of the first contact pad, a portion of the second contact pad and a portion of the first planar passivation contact to form a first light emitting diode bonding pad on the first contact pad, a second light emitting diode bonding pad on the second contact pad, and a third light emitting diode bonding pad on the first planar passivation contact.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: April 14, 2015
    Assignee: Starlite Led Inc
    Inventors: Chang Han, Pao Chen
  • Patent number: 9006037
    Abstract: Provided are methods of forming a bump and a semiconductor device with the same. The method may include providing a substrate with pads, forming a bump maker layer to cover the pads and include a resin and solder particles, thermally treating the bump maker layer to aggregate the solder particles onto the pads, removing the resin to expose the aggregated solder particles, forming a resin layer to cover the aggregated solder particles, and reflowing the aggregated solder particles to form bumps on the pads.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: April 14, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Kwang-Seong Choi, Yong Sung Eom, Hyun-cheol Bae, Haksun Lee
  • Patent number: 9006868
    Abstract: The invention relates to a component and a method for producing said component. The component comprises a substrate (S), a chip (CH), a frame (MF), which is connected to the substrate (S) and on which the chip (CH) bears. A metallic closure layer (ML) encompasses the frame (MF), the substrate (S) and the chip (CH) such that a volume enclosed by the substrate (S), the chip (CH) and the frame (MF) is hermetically sealed.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: April 14, 2015
    Assignee: EPCOS AG
    Inventors: Christian Bauer, Hans Krüger, Jürgen Portmann, Alois Stelzl
  • Patent number: 8999758
    Abstract: Semiconductor die are assembled on a substrate by providing the semiconductor die, substrate, and an elastically deformable foil fixture preformed with one or more sunken regions having sidewalls and a bottom, and placing the semiconductor die in the one or more sunken regions so that the foil fixture is populated with a first side of the semiconductor die facing the bottom of the one or more sunken regions and a second opposing side of the semiconductor die facing away from the bottom of the one or more sunken regions. The substrate is placed adjacent the second side of the semiconductor die with a joining material interposed between the substrate and the semiconductor die. The substrate and the populated foil fixture are pressed together at an elevated temperature and pressure via first and second pressing tool members so that the substrate is attached to the second side of the semiconductor die via the joining material.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies AG
    Inventor: Reinhold Bayerer
  • Patent number: 8999759
    Abstract: A method for fabricating a packaging structure having an embedded semiconductor element includes: providing a substrate having opposite first and second surfaces and at least an opening penetrating the first and second surfaces; forming a first metallic frame around the periphery of the opening on the first surface; forming at least an opening inside the first metallic frame by laser ablation; disposing a semiconductor chip in the opening; forming a first dielectric layer on the first and second surfaces and the chip; forming a first wiring layer on the first dielectric layer of the first surface; and forming a first built-up structure on the first dielectric layer and the first wiring layer of the first surface. A shape of the opening is precisely controlled through the first metallic frame around the periphery of the predefined opening region, thereby allowing the chip to be precisely embedded in the substrate.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: April 7, 2015
    Assignee: Unimicron Technology Corporation
    Inventor: Kan-Jung Chia
  • Patent number: 8994058
    Abstract: Disclosed is a light emitting device including a conductive substrate, a first electrode layer disposed on the conductive substrate, a light emitting structure disposed on the first electrode layer, the light emitting structure including a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer, and a second electrode layer electrically connected to the second semiconductor layer, wherein the first electrode layer includes a transparent electrode layer disposed between the conductive substrate and the first semiconductor layer, and an ohmic layer comprising a plurality of metal contact portions vertically passing through the transparent electrode layer, wherein each metal contact portion includes AuBe.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: March 31, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventors: BumDoo Park, TaeJin Kim, MinSuk Kim, YeongUn Seong, SangJun Lee, TaeYong Lee, KiYong Hong, SonKyo Hwang
  • Patent number: 8994153
    Abstract: A semiconductor device (semiconductor module) includes a circuit board (module board) and a semiconductor element mounted on the circuit board. A shielding layer that blocks electromagnetic waves is disposed on the upper surface of the semiconductor element, and an antenna element is disposed over the shielding layer. The semiconductor element and the antenna element are electrically connected to each other by a connecting portion. This structure enables the semiconductor device to be reduced in size and to have both an electromagnetic-wave blocking function and an antenna function.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: March 31, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hirohisa Matsuki, Masao Sakuma
  • Patent number: 8994193
    Abstract: A semiconductor package includes: a metal plate including a first surface, a second surface and a side surface; a semiconductor chip on the first surface of the metal plate, the semiconductor chip comprising a first surface, a second surface and a side surface; a first insulating layer that covers the second surface of the metal plate; a second insulating layer that covers the first surface of the metal plate, and the first surface and the side surface of the semiconductor chip; and a wiring structure on the second insulating layer and including: a wiring layer electrically connected to the semiconductor chip; and an interlayer insulating layer on the wiring layer. A thickness of the metal plate is thinner than that of the semiconductor chip, and the side surface of the metal plate is covered by the first insulating layer or the second insulating layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 31, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Akihiko Tateiwa, Masato Tanaka, Akio Rokugawa
  • Patent number: 8987060
    Abstract: A method for making the same is disclosed. First, a first substrate and a second substrate are provided. The first substrate includes a release film attached to a carrier. The second substrate includes a copper film covered with a solder mask. Second, the solder masked is patterned. Next, the release film and the patterned solder mask are pressed together so that the first substrate is attached to the second substrate. Then, the copper film is patterned to form a first pattern and a second pattern. The first pattern is in direct contact with the release film and the second pattern is in direct contact with the patterned solder mask. Later, a passivation is formed to cover the first pattern and the second pattern to form a circuit board structure. Afterwards, a package is formed on the carrier to form a packaging structure.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: March 24, 2015
    Assignee: Advance Materials Corporation
    Inventor: Lee-Sheng Yen
  • Patent number: 8987871
    Abstract: A cap for a microelectromechanical system device includes a first layer of, e.g., Bismaleimide Triazine (BT) resin material in which a through-aperture is formed, laminated to a second layer of BT resin material that closes the aperture in the first layer, forming a cavity. The first and second layers are laminated with a thermosetting adhesive that is sufficiently thick to encapsulate particles that may remain from a routing operation for forming the apertures. The interior of the cavity, including exposed portions of the adhesive, and the exposed face of the first layer are coated with an electrically conductive paint. The cap is adhered to a substrate over the MEMS device using an electrically conductive adhesive, which couples the conductive paint layer to a ground plane of the substrate. The layer of conductive paint serves as a shield to prevent or reduce electromagnetic interference acting on the MEMS device.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: March 24, 2015
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Jerome Teysseyre, Glenn de los Reyes, Wee Chin Judy Lim
  • Patent number: 8987061
    Abstract: Methods for antenna switch modules are disclosed. In certain implementations, a method of making an antenna switch module is provided. The method includes providing a package substrate implemented to receive one or more electrical components, attaching a silicon on insulator (SOI) die to the package substrate, and providing an integrated filter. The SOI die includes a capacitor and a switch coupled to a plurality of radio frequency (RF) signal paths. The integrated filter filters an RF signal received on a first RF signal path of the plurality of RF signal paths, and includes the capacitor of the SOI die and an inductor.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: March 24, 2015
    Assignee: Skyworks Soultions, Inc.
    Inventors: Jong-Hoon Lee, Chuming Shih
  • Publication number: 20150076699
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor element, an interconnection layer, and a bonding layer. The interconnection layer includes Cu. The bonding layer includes a first alloy that is an alloy of Cu and a first metal other than Cu between the semiconductor element and the interconnection layer. A melting point of the first alloy is higher than a melting point of the first metal.
    Type: Application
    Filed: March 11, 2014
    Publication date: March 19, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yo Sasaki, Yuuji Hisazato, Kazuya Kodani, Atsushi Yamamoto, Hitoshi Matsumura
  • Patent number: 8981551
    Abstract: A semiconductor device may include at least one pad adjacent a top surface of the device, and a metal crack stop structure below the at least one pad. The metal crack structure may have an inner envelope and an outer envelope, and may be configured to be vertically aligned with the at least one pad so that an edge of the at least one pad is between the inner and outer envelopes.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: March 17, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Delpech, Eric Sabouret, Sebastien Gallois-Garreignot
  • Publication number: 20150069132
    Abstract: A method for producing a smart card module arrangement includes: arranging a smart card module on a first carrier layer, wherein the first carrier layer is free of a prefabricated smart card module receptacle cutout for receiving the smart card module. The smart card module includes: a substrate; a chip on the substrate; a first mechanical reinforcement structure between the chip and the substrate. The first mechanical reinforcement structure covers at least one part of a surface of the chip. The method further includes applying a second carrier layer to the smart card module, wherein the second carrier layer is free of a prefabricated smart card module receptacle cutout for receiving the smart card module; and at least one of laminating or pressing the first carrier layer with the second carrier layer, such that the smart card module is enclosed by the first carrier layer and the second carrier layer.
    Type: Application
    Filed: September 11, 2014
    Publication date: March 12, 2015
    Inventors: Frank PUESCHNER, Thomas Spoettl, Jens POHL, Peter STAMPKA
  • Publication number: 20150061149
    Abstract: Packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a redistribution layer (RDL) and a plurality of through package vias (TPV's) coupled to the RDL. Each of the plurality of TPV's comprises a first region proximate the RDL and a second region opposite the first region. The first region comprises a first width, and the second region comprises a second width. The second width is greater than the first width.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih Ting Lin, Szu Wei Lu, Jui-Pin Hung, Jing-Cheng Lin
  • Publication number: 20150060898
    Abstract: A method for bonding an LED assembly 71 or other electronic package 31 to a substrate PCB containing a heat-sink 52, which utilizes layers of reactive multilayer foil 51 disposed between contacts 32, 34 of the electronic package 31 and the associated contact pads 55 on the supporting substrate PCB. By initiating an exothermic reaction in the reactive multilayer foil 51, together with an application of pressure, sufficient heat is generated between the contacts 32, 34 and the associated contact pads 55 to melt adjacent bonding material 54 to obtain good electrically and thermally conductive bonds between the contacts 32, 34 and contact pads 55 without thermally damaging the electronic package 31, heat-sensitive components 35 associated with the electronic package 31, or other the supporting substrate PCB.
    Type: Application
    Filed: November 10, 2014
    Publication date: March 5, 2015
    Inventors: David Van Heerden, Timothy Ryan Rude, Ramzi Vincent
  • Publication number: 20150061924
    Abstract: A semiconductor module has: an integrated circuit, which includes at least one oscillator for generating a radar signal; a rewiring layer for the external connection of the integrated circuit; and at least two antenna structures integrated into the semiconductor module for transmitting and/or receiving radar signals, at least one of the at least two antenna structures being connected to the integrated circuit, and at least one first one of the antenna structures being embedded in a housing material of the semiconductor module outside a height region of the rewiring layer.
    Type: Application
    Filed: January 18, 2013
    Publication date: March 5, 2015
    Applicant: ROBERT BOSCH GMBH
    Inventors: Thomas Binzer, Delf Mittelstrass
  • Patent number: 8963299
    Abstract: A semiconductor package is provided, including: a substrate having at least a conductive pad; a semiconductor element disposed on the substrate; a conductive adhesive formed on top and side surfaces of the semiconductor element and extending to the conductive pad; and an electronic element disposed on the conductive adhesive. The conductive adhesive and the conductive pad form a shielding structure so as to prevent electromagnetic interference from occurring between the semiconductor element and the electronic element.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: February 24, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Cheng Lin, Tsung-Hsien Hsu, Heng-Cheng Chu, Chao-Ya Yang, Chih-Ming Cheng
  • Publication number: 20150048506
    Abstract: A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a 3D memory array, a periphery circuit, and a conductive connection structure. The 3D memory array and the periphery circuit are stacked on the substrate. The periphery circuit includes a patterned metal layer and a contact structure electrically connected to the patterned metal layer. The conductive connection structure is electrically connected to the patterned metal layer. The 3D memory array is electrically connected to the periphery circuit via the conductive connection structure.
    Type: Application
    Filed: August 13, 2013
    Publication date: February 19, 2015
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yi-Hsuan Hsiao, Yen-Hao Shih, Shih-Hung Chen, Hang-Ting Lue
  • Publication number: 20150048492
    Abstract: A semiconductor package includes a baseplate having a die attach region and a peripheral region, a transistor die having a first terminal attached to the die attach region, and a second terminal and a third terminal facing away from the baseplate, and a frame including an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first metallization at the first side of the insulative member and a second metallization at the second side of the insulative member. The insulative member extends outward beyond a lateral sidewall of the baseplate. The first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate. The first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate.
    Type: Application
    Filed: November 3, 2014
    Publication date: February 19, 2015
    Inventors: Alexander Komposch, Soon Ing Chew, Brian Condie
  • Patent number: 8957518
    Abstract: The invention provides a molded interposer package and a method for fabricating the same. The molded interposer package includes a plurality of metal studs. A molding material encapsulates the metal studs leaving the bottom surfaces of the metal studs exposed. A first chip is disposed on the molding material, connecting to the top surfaces of the metal studs. A plurality of solder balls connects and contacts to the bottom surfaces of the metal studs.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 17, 2015
    Assignee: Mediatek Inc.
    Inventors: Thomas Matthew Gregorich, Andrew C. Chang, Tzu-Hung Lin
  • Patent number: 8956918
    Abstract: A method for manufacturing a chip arrangement in accordance with various embodiments may include: placing a chip on a carrier within an opening of a metal structure disposed over the carrier; fixing the chip to the metal structure; removing the carrier to thereby expose at least one contact of the chip; and forming an electrically conductive connection between the at least one contact of the chip and the metal structure.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: February 17, 2015
    Assignee: Infineon Technologies AG
    Inventor: Petteri Palm
  • Patent number: 8957531
    Abstract: A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: February 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: William E. Bernier, Timothy H. Daubenspeck, Virendra R. Jadhav, Valerie A. Oberson, David L. Questad
  • Patent number: 8956914
    Abstract: An integrated circuit package system comprising: forming a substrate having a solder mask with a support structure formed from the solder mask; mounting a first integrated circuit device over the support structure; connecting the substrate and the first integrated circuit device; and encapsulating the first integrated circuit device and the support structure.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: February 17, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Ja Eun Yun, Jong Wook Ju