Abstract: A substrate is provided with a plurality of regions, at least one of which is operationally redundant. An integrated circuit to be placed onto the substrate has a plurality of functional units that are designed to be interchangeable. The integrated circuit is tested for defects and, if a functional unit is found to be defective, then the integrated circuit is oriented (e.g., rotated or translated) with respect to the substrate such that the defective functional unit overlies the operationally redundant region of the substrate. A functional association is then formed between the remaining regions of the substrate and the non-defective functional units of the integrated circuit. Such functional association may be achieved by connecting each pair of unit and region. In this way, an integrated circuit with defective functional unit need not be discarded.

Abstract: Chalcopyrite semiconductors, such as thin films of copper-indium-diselenide (CuInSe2), copper-gallium-diselenide (CuGaSe2), and Cu(Inx,Ga1-x)Se2, all of which are sometimes generically referred to as CIGS, have become the subject of considerable interest and study for semiconductor devices in recent years. They are of particular interest for photovoltaic device or solar cell absorber applications. The quality of Cu(In,Ga)Se2 thin films, as an example of chalcopyrite films, is controlled by making spectrophotometric measurements of light reflected from the film surface. This permits the result of non-contacting measurements of films in a continuous production environment to be fed back to adjust the production conditions in order to improve or maintain the quality of subsequently produced film.

Abstract: In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.

Abstract: In an integrated device, an etch is performed in an intermediate layer to form a via. The via is inspected using a scanning electron microscopy. The scanning electron microscopy detects a level of brightness associated with the via and a background shade. Whether the etch reached an etch-stop layer is determined by comparing the level of brightness associated with the via to the background shade.

Abstract: A submount substrate is used for the dual purposes of enabling simultaneous burn-in processing for a relatively large number of arrays of optical transmitters and enabling conventional dicing techniques to be used to form mounting-ready assemblies. In the preferred embodiment, the submount substrate is a silicon wafer that is specifically designed to provide connectivity between VCSEL arrays and burn-in equipment during the testing stage, but is also designed to be segmented and used in the final packaging stage. Because the submount is a silicon wafer, conventional integrated circuit fabrication techniques may be used to form conductive patterns that define array-receiving areas and that allow external circuitry to communicate with the various VCSEL arrays.

Abstract: A wafer level packaging process for making flip-chips and integrated circuits formed are proposed. The process comprises in turn, providing a wafer, forming a protective material, bumping the wafer, removing the protective material, probing the wafer, laser repairing, and dicing the wafer. The laser repairing step is after bumping step. The protective material such as photoresist or metal layer is filled into the depression portions above the fuses for temporary protection of the fuses during bumping.

Abstract: A semiconductor element is first fixed on a frame. The semiconductor element and a plurality of leads are connected together. The semiconductor element is sealed with molding resin, to thereby fabricate a package having a length per side of 14 mm or more. After tie bars interconnecting a plurality of leads have been cut, a package is subjected to heat treatment at a predetermined temperature.

Abstract: A system and method for repairing defects in semiconductor wafers utilizing a repair tool including a device for applying energy to obliterate defects at locations on the wafer, the method being a graphical approach implementing a graphical user interface (GUI) comprising a pixel screen display and comprising the steps of: via the interface, identifying a wafer defect to repair and enclosing the defect within a polygonal repair outline drawn using a default line thickness; graphically adjusting the line thickness to modify the enclosed polygonal repair outline area; automatically detecting one or more areas within an interior region of the modified polygonal repair outline area; and, scanning the modified polygonal repair outline, and for each pixel location inside the one or more detected areas, applying energy to the wafer coordinated to the pixel location for repairing the defect, whereby the identification of said pixel location is accomplished using standard graphical tools with minimal operator interven

Abstract: Semiconductor analysis is enhanced using a system and method for improving the heat-dissipation characteristics of a semiconductor die. According to an example embodiment of the present invention, a flip-chip integrated circuit die having circuitry in a circuit side opposite a back side is formed having a back side including a thermal conductivity enhancing material. The thermal conductivity enhancing material improves the heat dissipating characteristics of the die during operation and testing and helps to reduce or prevent overheating. An epitaxial layer of silicon is formed in the back side, and circuitry is constructed in the epitaxial layer. Pre-existing circuitry on the circuit side and the newly formed circuitry in the back side are electrically coupled.

Abstract: A mark configuration for the alignment and/or determination of a relative position of at least two planes in relation to one another in a substrate and/or in layers on a substrate during lithographic exposure, in particular, in the case of a wafer during the production of DRAMs, includes a mark structure, and at least one layer of a definable thickness underneath the mark structure for adjusting the physical position of the mark structure relative to a reference plane in or on the substrate. Also provided is a wafer having such a configuration and a process for providing such a configuration. The invention allows a mark configuration to have mark structures exhibiting good contrast regardless of the design or the process conditions.

Abstract: A method and a structure for assembling a circuit board whereby high temperature attach devices can be electrically tested prior to the joining of permanent low temperature attach devices. A test interposer, with low temperature attach known good reference devices, is placed in electrical contact with the circuit board containing high temperature attach devices. The test interposer/circuit board assembly can be used to identify any defective high temperature attach devices which can be replaced prior to joining the permanent low temperature attach devices on the circuit board. This partial interim test, when only the high temperature attach devices are mounted on the circuit board, eliminates the need to remove known good low temperature attach devices from the circuit board during the high temperature attach device rework process.

Abstract: A system, and methods of its use, for characterizing semiconductor wafers with enhanced S parameter contour mapping employ small signal scatter parameter measurements of a representative sample of die to create a contour map of a wafer surface. Those die which fail to meet performance specifications are marked as bad die before the wafer is sent to a back-end process, where the unmarked good die are extracted and assembled into working products. By using enhanced S parameter mapping for characterizing the die, only those die marked as bad die need be discarded. Thus, instead of scrapping an entire wafer die lot based on the failure of a single die from that wafer, the wafer sort yield may be dramatically increased. The increase in wafer sort yield in turn, increases total production yield.

Abstract: A method for testing a semiconductor device comprises executing a function test on the semiconductor device, executing a DC characteristic test on the semiconductor device, executing a remedy determination process of the semiconductor device, and executing a remedy process on the semiconductor device. The remedy determination process is performed in parallel to the DC test.

Abstract: A semiconductor chip is attached on a package substrate so as to be electrically connected to it and sealed. A ring member is attached to the package substrate and surrounds the semiconductor chip. A lid member is attached to the ring member and covers the semiconductor chip. The lid member is formed so as to be able to be removed from the ring member without impairing the attachment of the ring member to the package substrate.

Abstract: Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element.

Abstract: A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the dice with the temporary test package bases, and an automated robot arm system is employed to retrieve and assemble the dice with the various package components. The invention has particular utility in the burn-in and other pre-packaging testing of dice to establish known good dice (KGD).

Abstract: A semiconductor memory chip has fuses and a redundancy memory cell which can replace a normal memory cell that is found defective by cutting off the fuses. If the normal memory cell is defective, the fuses are cut off thereby to connect the redundancy memory cell instead of the normal memory cell which is defective. The entire surface of the semiconductor memory chip is coated with a resist layer. The coated the resist layer is exposed at regions of the fuses to an energy beam, and then developed form a resist pattern. The semiconductor memory chip is etched at the regions using the resist pattern as a mask for thereby cutting off the fuses. The fuses may be spaced at intervals of 2 &mgr;m or smaller, and can be cut off without causing damage to a layer beneath the fuses.

Abstract: Aspects for detecting integrated circuit package orientation in carrier tape packing are described. In accordance with these aspects, a digital circuit is provided over a carrier rail of a tape and reel system. The digital circuit detects package orientation based on a chamfer side of packages within a tape on the carrier rail. The digital circuit further includes at least two optical sensors, where the optical sensors emit a light beam and sense reflection of the light beam for each package within the tape for use in determining package orientation in an automated manner.

Abstract: A passivation layer of AlN is deposited on a GaN channel HFET using molecular beam epitaxy (MBE). Using MBE, many other surfaces may also be coated with AlN, including silicon devices, nitride devices, GaN based LEDs and lasers as well as other semiconductor systems. The deposition is performed at approximately 150° C. and uses alternating beams of aluminum and remote plasma RF nitrogen to produce an approximately 500 Å thick AlN layer.

Abstract: Analysis of a flip-chip type IC die having SOI structure is enhanced via analysis and repair of the die that make possible analysis that would typically result in the die being in a state of disrepair. According to an example embodiment of the present invention, a focused ion beam (FIB) is directed at a back side of a flip-chip die having a circuitry in a circuit side opposite a back side, wherein the circuitry including silicon on insulator (SOI) structure. The FIB is used to remove a selected portion of substrate including a portion of the insulator of the SOI structure from the die. The removed substrate exposes an insulator region in the die, and a signal is coupled from circuitry in the die via the exposed insulator region and used to analyze the die. Material is deposited in the exposed region and the selected portion of the die that had been removed is reconstructed.

Abstract: A new method is provided for determining the optimum film thickness of a film that is to be deposited over a semiconductor surface. The invention observes the electrical current and the therefrom resulting torque that is supplied to a rotating part of a polishing apparatus, from this the CMP end-point can be determined for a reference film that has been deposited. This technique is known as the “CMP end-point detection” technique. The invention addresses observing CMP end-point curves for films of various thicknesses and compares these CMP end-point curves of one film thickness with each other and calculates a deviation for multiple layers (deposited on different wafers) of that film thickness. The process is repeated for different film thickness. The film thickness that has a deviation of the CMP end-point curve that closest resembles an optimum deviation is the film thickness that is selected as having the optimum thickness for the deposition of that film.

Abstract: A method for producing a probe unit for contacting an electronic circuit such as a wafer or a die having a predetermined pattern of contact pads deployed in a common plane. The method employes a base plate of made of a material capable of surface uplift when irradiated. On the surface of the base plate locations corresponding to said contact pads are determined. Further, the base plate is irradiated at the determined locations by means of a laser. This results in forming conical surface uplifts. The method further includes plating the conical surface uplifts with an electrically conductive material and providing means for electical connection between said plated conical surface uplifts and an external device.

Abstract: A method of manufacturing an integrated circuit having metal programmable logic cells. Metal programmable logic cells include transistors which, by varying routing of conductors in the metalization of the integrated circuit, may be connected in or disconnected from a logic path extending between the input and output of the cell. Transistors which are deselected by not being connected in the logic path are also decoupled from the supply rails. Generally speaking, deselected transistors can not be scan tested without substantial additional circuitry, as they do not form part of the logic path between the cell input and output to which the scan test circuitry is normally coupled. Decoupling transistors which are not in the logic path ensures that “stuck on” faults, in which transistors are stuck in a conductive state, do not allow current to flow between the supply rails through these faulty transistors, thus avoiding hot spots and reliability problems.

Abstract: A method and system are provided for analyzation of those defects with possibility to become electrical failures with higher priority during inspection processes of particles and/or pattern defects of a wafer for formation of electronic devices such as semiconductor integrated circuits.

Abstract: A reverse biasing apparatus is used to remove short-circuited portions in a solar battery module having multiple strings of solar cells each including a first electrode layer, a photovoltaic semiconductor layer and a second electrode layer formed on a glass substrate, by applying a reverse bias voltage between the electrodes of adjacent solar cells. The reverse biasing apparatus comprises probes to be in contact with the electrodes of adjacent three or more strings of solar cells, an actuator for actuating the probes up and down, and a relay switch for selecting, from the probes, a pair of probes for applying the reverse bias voltage between the electrodes of an arbitrary pair of adjacent solar cells. The use of the reverse biasing apparatus can ensure an efficient reverse biasing process on a solar battery module having integrated multiple strings of solar cells.

Abstract: A tester is designed to test a semiconductor memory device. First of all, the tester executes the function test of a memory cell array, which is among the function tests of the semiconductor device. Then, the tester performs redundancy analysis to replace an abnormal portion of the memory cell array with a spare row/column. The tester also executes the DC characteristic test of the semiconductor memory device and the function test of a peripheral circuit of the semiconductor memory device. The redundancy analysis is performed in parallel to both the DC characteristic test and the function test of the peripheral circuit.

Abstract: The method for improving circuit location assignment is capable of operating in the boolean, electrical and spatial (location) domains. Optimization of location assignment parameters can be performed simultaneously by determining a subset of nets or paths and generating sets of motions to improve these nets or paths. Once sets of motions have been generated, they are tested to determine the most beneficial movement for improving the given circuit parameter (e.g., wireability, timing, etc.).

Abstract: A method is provided for preparing a sample for cross-section analysis by a transmission electron microscope. Semiconductor samples containing recessed portions or unfilled structures are filled with a filling material so as to produce a planar top surface onto which a metal layer can be deposited for thinning the sample to a thickness of less than 100 nm by an FIB technique.

Abstract: A method and apparatus for collecting defect includes forming a defect collecting structure on a wafer such that any residue defects tend to settle on the defect collecting structure instead of the circuit patterns. The defect collecting structure can be located within the die or on the scribelines between the dies. When the defect collecting structure is located in a die, it should have dimensions significantly larger than the dimensions of the surrounding circuits patterns. The defect collecting structure can include a plurality of defect collecting structures. The defect collecting structures can be contiguous or non-contiguous. The defect collecting structure(s) can occupy one hundredth of one percent of the die or more. The defect collecting structures can be created on a wafer by coating, exposing, developing, and optionally, detecting defects. The wafer is exposed with a mask that includes a pattern for the defect collecting structure(s).

Abstract: A substrate removal approach involves sensing acoustic energy in an integrated circuit as a function of substrate in the integrated circuit being removed. According to an example embodiment of the present invention, a method for substrate removal includes removing a portion of substrate from the back side of a semiconductor chip circuitry near a circuit side and opposite the back side. The substrate is removed as a function of detected acoustic energy propagating through the device. The detected acoustic energy can be correlated to a parameter and used for controlling the substrate removal process, improving the ability to efficiently and accurately test semiconductor devices.

Abstract: A method and apparatus for removing layers from a circuit side of a semiconductor die includes the use of a holder, for example a semiconductor wafer having an opening therein for receiving the semiconductor die. Additionally the holder can include one or more layers thereover which are removed at a similar rate as those layers which comprise the semiconductor die. A die is placed into the opening and a circuit side of the die is aligned with a front side of the holder, for example using a generally planar surface, and is secured to the holder with an adhesive material. Using a holder reduces uneven layer removal which is known to occur in conventional processing, for example excessive removal at the edges of the die. A potting jig which aids in aligning and securing the die to the holder is also described.

Abstract: A system and method for preparing semiconductor samples for analytical techniques such as backside emission microscopy. Samples may be prepared from a wafer or packaged die. In package form, the package is affixed to a polishing jig such that the backside of the die is oriented to face a polishing wheel. The package material is removed until die attach paddle and the backside of the die are exposed. The material is further removed until a selected thinness of the die is obtained. If the package's leadframe or a portion thereof remains after the removal of package material, a suitable testing fixture is attached thereto. If the leadframe is sacrificed, wire spots on the polished side of the semiconductor die are wire-to-wire bonded to a second leadframe's conductive fingers. In wafer form, the die is separated and encapsulated with a suitable substantially rigid material to form a substantially rigid body that is affixed to the polishing jig.

Abstract: A process for manufacturing a semiconductor comprising the step of mounting a semiconductor component on a printed circuit board, with electrodes of the semiconductor component facing to electrodes of the printed circuit board, the step of inspecting a function as a semiconductor device with the semiconductor component being mounted on the printed circuit board, the step of bonding the electrodes of the printed circuit board and the electrodes of the mounted semiconductor component to obtain the semiconductor device when the inspection result is good, and the step of replacing at least one of the printed circuit board and the semiconductor component with another one of the same type and again inspecting the function as the semiconductor device when the inspection result is not good.

Abstract: A method for removing short circuits in thin film solar cell elements during manufacturing by applying a pseudo-alternating voltage between the substrate side and the back electrodes of the solar cell elements. The waveform of the pseudo-alternating voltage may be a sinusoidal wave, a half-wave sinusoidal wave, a sawtooth wave, a square wave or the like. The peak voltage in the reverse direction is up to the reverse breakdown voltage of the solar cell element, and the waveform may either contain a small forward component or no fond component The peak voltage in Se reverse direction may also momentarily exceed the reverse breakdown voltage. The period of the pseudo-alternating voltage matches the tine constant of the solar cell element determined by the capacity and reverse resistance of the solar cell element.

Abstract: An improved method of detecting and removing a shunt from a photoelectric semiconductor device comprises the steps of characterizing the device by generated data or performance graph; forward biasing the device; producing electromagnetic radiation from the device; receiving the radiation; associating a contrast in radiation to the defect; and mechanically removing the defect, whereby the defect is removed in the absence of a step of applying a chemical to the defect to assist in removing the defect.

Abstract: The formation and/or growth of dendrites emanating from Cu or Cu alloy lines into a bordering open dielectric field are prevented or substantially reduced by chemically removing a portion of the surface from the dielectric field and between the lines after CMP. Embodiments include removing up to 20 Å of silicon oxide by buffing with a solution containing ammonium fluoride, diammonium hydrogen citrate, triammonium citrate and dionized water.

Abstract: A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the dice with the temporary test package bases, and an automated robot arm system is employed to retrieve and assemble the dice with the various package components. The invention has particular utility in the burn-in and other pre-packaging testing of dice to establish known good dice (KGD).

Abstract: Scanning Electron Microscope (SEM) analysis is used to detect undesired conductive material on the gate sidewall spacers. The undesired conductive material is then etched from the sidewall spacers if the undesired material is detected by the SEM analysis. More specifically, integrated circuit field effect transistors may be manufactured by forming on an integrated circuit substrate, a plurality of field effect transistors, each comprising spaced apart source and drain regions, a gate therebetween including a sidewall, a sidewall spacer on the sidewall and contacts comprising conductive material on the source and drain regions. At least one of the field effect transistors may include undesired conductive material on the sidewall spacer thereof. The integrated circuit field effect transistors are tested by performing SEM analysis on the integrated circuit substrate to detect the undesired conductive material on the sidewall spacer.

Abstract: A method is provided for performing in-line process checks in an integrated circuit fabrication process. The process checks are performed on actual product wafers, rather than control wafers. According to the method, production lots of product wafers are subjected to in-line testing. Selected wafers representing each chamber of the fabrication apparatus are tested for defects. Using the actual product wafers allows the detection of the quantity, size, type, composition, and even the cause of the defects. When defects are found, the fabrication process and apparatus are adjusted to avoid producing additional lots with undesirable defects.

Abstract: Aspects for removing device packaging from an FBGA (fine pitch ball grid array) package are described. In an exemplary method aspect, the method includes recessing a predetermined area of the FBGA package, and exposing an integrated circuit die covered by the FBGA package. Device analysis is then performed on the exposed die. The step of recessing further includes milling the predetermined area, while the step of exposing includes chemically etching the FBGA package.

Abstract: A method for nondestructive layer defect detection includes projecting radiation such as a laser beam on a surface of the layer. The surface of the layer is heated by the projected radiation so as to melt at least a portion of the layer. An impurity contained in a defect is heated by the projected radiation so as to increase the pressure of the material within the defect sufficiently to cause the impurity to emerge from the defect through the surface of the layer. The layer is then scanned for a visible defect created by the emergence of the impurity from the defect. A wafer scanning system for nondestructive layer defect detection includes a radiation source such as a laser and a wafer support system that supports a semiconductor wafer with a layer formed thereon in alignment with the radiation source.

Abstract: A method for repairing defects in a surface layer of a substrate. The method comprises the redeposition, in a solvent environment, of a fill material into the defects of the surface layer. The fill material is provided by the surface layer itself or from a separate source comprising a different material from that of the surface layer.

Abstract: A method for fabricating custom integrated circuits includes the steps of 1) patterning the layer to be customized with a standard precision mask to define all possible connections, vias or cut-points, and 2) using a targeting energy beam to select the desired connections, vias or cut-points for customization.Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods.In other embodiments, a non-precision configuration mask may replace the targeting energy beam, where the configuration mask can be made by conventional mask-making techniques or by applying an opaque layer to a mask blank and using a targeting energy beam to selectively remove the desired portions of the opaque areas.

Abstract: A method is provided for obtaining a topography with a substantially planar upper surface. The profile of the upper surface of the semiconductor topography is first detected by a profile detection tool, such as a stylus profilometer. The profile detection tool creates a database to quantify the elevational variations across the upper surface of the semiconductor topography. The database is then provided to a control system of a deposition tool. The control system controls the deposition of a profile layer upon the upper surface of the semiconductor topography such that a thickness of the profile layer is a function of the elevation of the surface. In one embodiment, the control system controls a potential gradient across the semiconductor topography so as to cause more reactant species to be directed toward the more recessed regions of the topography. In another embodiment, the control system controls the opening and closing of valves disposed within a shower head above the semiconductor topography.

Abstract: The present invention provides a device and a method for substantially minimizing defects on the surface of the interface of the stop layer and the oxide layer during manufacturing of a semiconductor device. A method according to the present invention for minimizing defects in a semiconductor device, the method including the steps of depositing a stop layer, the stop layer having a surface; bombarding the surface of the stop layer with N2 using a power of at least approximately 320 W; and depositing the oxide layer over the stop layer.

Abstract: A method and system provide for yield loss analysis for use in determining the killer stage in the manufacture of a semiconductor wafer at a plurality of manufacturing stages. The method comprising the following steps. Inspect semiconductor devices on the wafer visually to identify the location of visual defects on dies being manufactured on the wafer and to maintain a count of visual defects on the dies by location. Inspect the semiconductor dies on the wafer to determine the location and number defective dies on the wafer at each of the manufacturing stages. Calculate the defective die count for each stage for the wafer. Calculate the defective bad die count for each stage for the wafer. Determine the percentage of the defective bad die count divided by the defective die count. Plot the trend of the percentage of yield loss and the percentage of defective bad dies for each of the manufacturing stages.

Abstract: A semiconductor with dedicated wire bond sites that are routed and via'd only to a top surface of a semiconductor package to flush mount pads where they are probed during debug, thus reducing the overall inductance and capacitance of the path from the wire bond site to the debug probing site over conventional debug testing by means of dedicated pins on the semiconductor package. This design permits higher performance debug data capture, while at the same time decreasing the number of pads and pins that are necessary for debug.

Abstract: Techniques for improving manufacturing process control based on inspection of manufactured items at intermediate process steps, based on clustering and binning of defect data. Additionally, the using the defect data produced by inspection machines to improve manufacturing process control specifically relating to semiconductor manufacturing process control. Examples described here relate specifically to semiconductor wafers, but may be generalized to any manufacturing process.

Abstract: A method and apparatus for accurately transforming coordinates within a first coordinate system (e.g., a two-dimensional coordinate system associated with a substrate (or portion thereof)) into coordinates in a second coordinate system (e.g., a three-dimensional coordinate system of substrate (or portion thereof) tilted within a wafer analysis tool.

Abstract: A semiconductor memory chip has fuses and a redundancy memory cell which can replace a normal memory cell that is found defective by cutting off the fuses. If the normal memory cell is defective, the fuses are cut off thereby to connect the redundancy memory cell instead of the normal memory cell which is defective. The entire surface of the semiconductor memory chip is coated with a resist layer. The coated the resist layer is exposed at regions of the fuses to an energy beam, and then developed form a resist pattern. The semiconductor memory chip is etched at the regions using the resist pattern as a mask for thereby cutting off the fuses. The fuses may be spaced at intervals of 2 .mu.m or smaller, and can be cut off without causing damage to a layer beneath the fuses.