Abstract: A method for locating possible defects on an opaque layer deposited on a production wafer of a semiconductor circuit, consisting in locally radiating an upper surface of the wafer by means of a laser, and detecting the occurrence of a current in a diode constituted by a PN junction placed under the opaque layer to be examined.

Abstract: A method of removing thin film layers of a semiconductor component suitable for exposing a defective thin film layer for failure analysis. A focused ion beam is used instead of conventional mechanical polishing in non-selectively etching the thin film layers above a defective thin film layer in a semiconductor component. The focused ion beam has a better control over the etching thickness, so that a higher sample point success rate is obtained from a test specimen. Processing time is saved using the focused ion beam, which requires only a few minutes compared with hours needed by the conventional mechanical polishing method. The focused ion beam performs localized etching only, so that the thin film layers of other sample points in the test specimen will be unaffected. Therefore, a number of sample points can be prepared on the same test specimen at the same time.

Abstract: A method for forming silica stain on a substrate to facilitate monitoring of the silica stain during integrated circuit manufacture. The method includes providing a silica stain test structure which has a silicon substrate, a hydrophilic silicon dioxide containing layer disposed above the silicon substrate, and a plurality of cavities formed in the silicon substrate through the silicon dioxide containing layer. The cavities have hydrophobic sidewalls. The method also includes exposing the silica stain test structure to deionized water, and drying the silica stain test structure to form the silica stain on the silicon dioxide containing layer.

Abstract: The method of this invention for heat treatment of a Si single crystal grown by the Czochralski method at a speed of pull of not less than 0.8 mm/min., characterized by heat-treating at a temperature in the range of from 1,150.degree. C. to 1,280.degree. C. a wafer cut out of the Si single crystal thereby producing a Si wafer excellent in oxide film dielectric breakdown voltage characteristic due to elimination of crystal defects. Consequently, this invention ensures production of LSI in a high yield.

Abstract: According to the present invention, an improved method for locating particle contamination during the integrated circuit manufacturing process is disclosed. The integrated circuit wafer is grounded and then exposed to an electron beam to create an enhanced electrical potential in any conducting or semi-conducting particles embedded in the layered wafer. The embedded particle will begin to accumulate an electrical charge and will reach a certain electrical potential based on the size and composition of the particle as well as the length of exposure to the electron beam. After a sufficient charge has been accumulated in the embedded particle, the wafer is subjected to burn-in testing. Since the particles embedded in the wafer have been previously exposed to the electron beam, the standard voltages applied during burn-in testing will force a certain number of embedded particles to suffer accelerated breakdown.

Abstract: A method and apparatus are disclosed for stressing the oxide layer (36) of an MOS integrated circuit during the fabrication process. One aspect of the invention is a method for fabricating an MOS integrated circuit. In accordance with this method, an oxide layer (36) is formed on a semiconductor substrate (34), and a gate layer (38) is formed on top of the oxide layer (36). During fabrication of the MOS integrated circuit, a potential is applied between the gate layer (38) and the semiconductor substrate (34) in order to stress the oxide layer (36). Other aspects of the invention include applying both a forward and reverse potential to stress the oxide layer (36). Also, the oxide stress can be applied at an elevated temperature. Elevated temperature aids in stressing the oxide layer (36).

Abstract: Each transistor or logic unit on an integrated circuit wafer is tested prior to interconnect metallization. By means of CAD software, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD computer system. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than with conventional testing at the completed circuit level.The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure.

Abstract: The ROM device comprises a number of memory cells each is constructed based on a MOS transistor, the memory cells in the ROM are arranged into a number of rows and a columns. A number of word lines each connects to the gates of each of the MOS transistors of all the memory cells in each of the rows. A number of bit lines each connects to one of the source/drain pair of each of the MOS transistors of all the memory cells in each of the columns. A multiplexer comprises a number of transmitting transistors, each of the transmitting transistors is connected to a corresponding one of the bit lines, forming a current flow path including the transmitting transistor, the connected bit line, and the memory cells correspondingly connected to the bit line. A sense amplifier is coupled to the multiplexer for sensing the current flowing therethrough the current flow path to output a corresponding sense output signal.