Making Conductivity Modulation Device (e.g., Unijunction Transistor, Double Base Diode, Conductivity-modulated Transistor, Etc.) Patents (Class 438/141)
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Patent number: 12095229Abstract: The invention relates to a light emitter unit having at least one VCSEL chip, which light emitter unit comprises: a light exit surface, via which light produced by the VCSEL chip and radiated perpendicularly to the chip plane is emitted into the surroundings; and contacts for supplying the electrical energy required for the production of the light by the VCSEL chip. The described technical solution is characterized in that at least one lateral surface of the VCSEL chip arranged perpendicularly to the chip plane is touched and covered, at least in parts, by a cover element.Type: GrantFiled: November 20, 2019Date of Patent: September 17, 2024Assignee: OSRAM Opto Semiconductors GmbHInventors: Zeljko Pajkic, Florian Nuetzel, Fabian Knorr, Michael Mueller
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Patent number: 11624770Abstract: This disclosure is related to arranging micro devices in the donor substrate by either patterning or population so that there is no interfering with non-receiving pads and the non-interfering area in the donor substrate is maximized. This enables the transfer of micro devices to a receiver substrate with fewer steps.Type: GrantFiled: August 15, 2019Date of Patent: April 11, 2023Assignee: VueReal Inc.Inventors: Gholamreza Chaji, Ehsanollah Fathi
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Patent number: 11227908Abstract: A flexible organic light-emitting diode (OLED) display substrate and manufacturing method using the same are provided. The flexible OLED display substrate includes a display region, a non-display region, and a bending region connected to the display region and the non-display region. The bending region is provided with multiple liquid conductive wires spaced from each other. Each liquid conductive wire includes a conductive flow channel disposed in the bending region and a pair of metal wire portions connected to two ends of the conductive flow channel. A packaging layer is arranged on each conductive flow channel to store a liquid conductive material. The liquid conductive material is sealed in each conductive flow channel. Therefore, the liquid conductive wires can greatly improve the production yield of the bending region, and overcome a problem that a conventional bending region is prone to break during a bending process.Type: GrantFiled: January 9, 2019Date of Patent: January 18, 2022Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventor: Yongzhen Jia
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Patent number: 11127886Abstract: A flip-chip light LED includes: a substrate; an epitaxial layer on the substrate, wherein, the epitaxial layer comprises: a first semiconductor layer, a second semiconductor layer and a light emitting layer between the first semiconductor layer and the second semiconductor layer; at least one opening structure, which is at the epitaxial layer edge and extends to the substrate surface, making parts of the side wall of the epitaxial layer and the substrate surface exposed, such that the epitaxial layer is divided into an epitaxial bulk layer and a barrier structure; and an insulating layer on the opening structure as the metal electrode isolating layer.Type: GrantFiled: August 13, 2016Date of Patent: September 21, 2021Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Anhe He, Su-hui Lin, Jiansen Zheng, Kangwei Peng, Xiaoxiong Lin, Chen-ke Hsu
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Patent number: 11003870Abstract: The disclosed technology relates generally to apparatuses comprising conductive polymers and more particularly to tags and tag devices comprising a redox-active polymer film, and methods of using and manufacturing the same. In one aspect, an apparatus includes a substrate and a conductive structure formed on the substrate which includes a layer of redox-active polymer film having mobile ions and electrons. The conductive structure further includes a first terminal and a second terminal configured to receive an electrical signal therebetween, where the layer of redox-active polymer is configured to conduct an electrical current generated by the mobile ions and the electrons in response to the electrical signal. The apparatus additionally includes a detection circuit operatively coupled to the conductive structure and configured to detect the electrical current flowing through the conductive structure.Type: GrantFiled: January 9, 2015Date of Patent: May 11, 2021Assignee: Arizona Board of Regents on Behalf of Arizona State UniversityInventors: Cody Friesen, Elise Switzer
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Patent number: 10790454Abstract: The field of the DISCLOSURE lies in active materials for organic image sensors. The present disclosure relates to transparent N materials and/or to transparent P materials and their use in absorption layer(s), photoelectric conversion layer(s) and/or an organic image sensor and methods for their synthesis. The present disclosure also relates to photoelectric conversion layer(s) including an active material according to the present disclosure, to a device, including active material(s) according to the present disclosure or photoelectric conversion layer(s) according to the present disclosure. Moreover, the present disclosure relates to an organic image sensor including photoelectric conversion layer(s) according to the present disclosure.Type: GrantFiled: March 31, 2016Date of Patent: September 29, 2020Assignee: Sony CorporationInventors: Silvia Rosselli, David Danner, Tzenka Miteva, Gabriele Nelles, Vitor Deichmann, William E. Ford, Dennis Chercka, Vladimir Yakutkin, Lars Peter Scheller, Nikolaus Knorr
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Patent number: 9837316Abstract: A thin film transistor includes a polysilicon layer on a substrate, which includes a first area between second and third areas. A polysilicon layer is formed on the substrate, and a source electrode and a drain electrode are formed on the polysilicon layer in the first and third areas. Each of the source electrode and the drain electrode includes a metal silicide layer adjacent the polysilicon layer.Type: GrantFiled: December 2, 2016Date of Patent: December 5, 2017Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Jongchan Lee, Yoonho Khang, Myounghwa Kim, Joonhwa Bae, Myounggeun Cha
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Patent number: 9379299Abstract: An apparatus includes a wafer with a number of openings therein. For each opening, an LED device is coupled to a conductive carrier and the wafer in a manner so that each of the coupled LED device and a portion of the conductive carrier at least partially fill the opening. A method of fabricating an LED device includes forming a number of openings in a wafer. The method also includes coupling light-emitting diode (LED) devices to conductive carriers. The LED devices with conductive carriers at least partially fill each of the openings.Type: GrantFiled: January 23, 2015Date of Patent: June 28, 2016Assignee: EPISTAR CORPORATIONInventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Hung-Yi Kuo, Chyi Shyuan Chern
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Patent number: 9177890Abstract: A three-dimensional integrated circuit comprising top tier nanowire transistors formed on a bottom tier of CMOS transistors, with inter-tier vias, intra-tier vias, and metal layers to connect together the various CMOS transistors and nanowire transistors. The top tier first begins as lightly doped regions on a first wafer, with an oxide layer formed over the regions. Hydrogen ion implantation forms a cleavage interface. The first wafer is flipped and oxide bonded to a second wafer having CMOS devices, and the cleavage interface is thermally activated so that a portion of the lightly doped regions remains bonded to the bottom tier. Nanowire transistors are formed in the top tier layer. The sources and drains for the top tier nanowire transistors are formed by in-situ doping during epitaxial growth. After oxide bonding, the remaining process steps are performed at low temperatures so as not to damage the metal interconnects.Type: GrantFiled: March 7, 2013Date of Patent: November 3, 2015Assignee: QUALCOMM IncorporatedInventor: Yang Du
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Patent number: 9006857Abstract: An IR sensor includes a suspended micro-platform having a support layer and a device layer disposed thereon. IR absorbers are disposed in or on the device layer. IR radiation received by the IR absorbers heats an on-platform junction of each of a plurality of series-connected thermoelectric devices operating in a Seebeck mode, the devices producing a voltage indicative of the received IR. Other thermoelectric devices are used to cool the platform, and a pressure sensing arrangement is used to detect loss of vacuum or pressure leaks.Type: GrantFiled: April 4, 2014Date of Patent: April 14, 2015Inventor: William N. Carr
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Patent number: 8999770Abstract: A semiconductor structure includes a module with a plurality of die regions, a plurality of light-emitting devices disposed upon the substrate so that each of the die regions includes one of the light-emitting devices, and a lens board over the module and adhered to the substrate with glue. The lens board includes a plurality of microlenses each corresponding to one of the die regions, and at each one of the die regions the glue provides an air-tight encapsulation of one of the light-emitting devices by a respective one of the microlenses. Further, phosphor is included as a part of the lens board.Type: GrantFiled: July 24, 2013Date of Patent: April 7, 2015Assignee: TSMC Solid State Lighting Ltd.Inventors: Tien-Ming Lin, Chih-Hsuan Sun, Wei-Yu Yeh
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Patent number: 9000516Abstract: A super-junction device including a unit region is disclosed. The unit region includes a heavily doped substrate; a first epitaxial layer over the heavily doped substrate; a second epitaxial layer over the first epitaxial layer; a plurality of first trenches in the second epitaxial layer; an oxide film in each of the plurality of first trenches; and a pair of first films on both sides of each of the plurality of first trenches, thereby forming a sandwich structure between every two adjacent ones of the plurality of first trenches, the sandwich structure including two first films and a second film sandwiched therebetween, the second film being formed of a portion of the second epitaxial layer between the two first films of a sandwich structure. A method of forming a super-junction device is also disclosed.Type: GrantFiled: September 5, 2013Date of Patent: April 7, 2015Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.Inventor: Shengan Xiao
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Patent number: 8993447Abstract: An apparatus includes a wafer with a number of openings therein. For each opening, an LED device is coupled to a conductive carrier and the wafer in a manner so that each of the coupled LED device and a portion of the conductive carrier at least partially fill the opening. A method of fabricating an LED device includes forming a number of openings in a wafer. The method also includes coupling light-emitting diode (LED) devices to conductive carriers. The LED devices with conductive carriers at least partially fill each of the openings.Type: GrantFiled: April 8, 2013Date of Patent: March 31, 2015Assignee: TSMC Solid State Lighting Ltd.Inventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Hung-Yi Kuo, Chyi Shyuan Chern
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Publication number: 20150076565Abstract: The disclosure provides an ultrahigh-voltage (UHV) semiconductor structure including a first electrical portion, a second electrical portion and a bridged conductive layer. In which, the first electrical portion and the second electrical portion are isolated, and directly connected to each other through the bridged conductive layer. Thus, there is no current leakage occurring in the UHV semiconductor structure disclosed in this disclosure. And a method for manufacturing the UHV semiconductor structure also provides herein.Type: ApplicationFiled: September 13, 2013Publication date: March 19, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Chih CHIANG, Tung-Yang LIN, Chih-Chang CHENG, Ruey-Hsin LIU
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Patent number: 8969143Abstract: A light-emitting device package including a lead frame formed of a metal and on which a light-emitting device chip is mounted; and a mold frame coupled to the lead frame by injection molding. The lead frame includes: a mounting portion on which the light-emitting device chip is mounted; and first and second connection portions that are disposed on two sides of the mounting portion in a first direction and connected to the light-emitting device chip by wire bonding, wherein the first connection portion is stepped with respect to the mounting portion, and a stepped amount is less than a material thickness of the lead frame.Type: GrantFiled: August 7, 2013Date of Patent: March 3, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Daniel Kim, Jae-sung You, Jong-kil Park
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Patent number: 8969134Abstract: A tape capable of laser ablation may be used in the formation of microelectronic interconnects, wherein the tape may be attached to bond pads on a microelectronic device and vias may be formed by laser ablation through the tape to expose at least a portion of corresponding bond pads. The microelectronic interconnects may be formed on the bond pads within the vias, such as by solder paste printing and solder reflow. The laser ablation tape can be removed after the formation of the microelectronic interconnects.Type: GrantFiled: May 10, 2013Date of Patent: March 3, 2015Assignee: Intel CorporationInventors: Xavier F. Brun, Takashi Kumamoto, Sufi Ahmed
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Patent number: 8963199Abstract: An N type well (NW) is formed over a prescribed depth from a main surface of a semiconductor substrate (SUB), and a P type well (PW) and an N type drain region (ND) are formed in the N type well (NW). An N type source region (NS), an N+ type source region (NNS), and a P+ type impurity region (BCR) are formed in the P type well (PW). The N type source region (NS) is formed on a region situated directly below the N+ type source region (NNS), and not on a region situated directly below the P+ type impurity region (BCR), and the P+ type impurity region (BCR) is in direct contact with the P type well (PW).Type: GrantFiled: February 21, 2012Date of Patent: February 24, 2015Assignee: Renesas Electronics CorporationInventor: Shunji Kubo
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Patent number: 8945979Abstract: An organic layer deposition apparatus, a method of manufacturing an organic light-emitting display apparatus by using the same, and an organic light-emitting display apparatus manufactured by the method, and more particularly, an organic layer deposition apparatus that is suitable for use in the mass production of a large substrate, that enables high-definition patterning, and that is capable of controlling a distance between a patterning slit sheet and a substrate that moves, a method of manufacturing an organic light-emitting display apparatus by using the organic layer deposition apparatus, and an organic light-emitting display apparatus manufactured by the method.Type: GrantFiled: March 12, 2013Date of Patent: February 3, 2015Assignee: Samsung Display Co., Ltd.Inventor: Yun-Ho Chang
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Patent number: 8927348Abstract: Provided are a method of manufacturing a group-III nitride semiconductor light-emitting device in which a light-emitting device excellent in the internal quantum efficiency and the light extraction efficiency can be obtained, a group-III nitride semiconductor light-emitting device and a lamp. Included are an epitaxial step of forming a semiconductor layer (30) so as to a main surface (20) of a substrate (2), a masking step of forming a protective film on the semiconductor layer (30), a semiconductor layer removal step of removing the protective film and the semiconductor layer (30) by laser irradiation to expose the substrate (2), a grinding step of reducing the thickness of the substrate (2), a polishing step of polishing the substrate (2), a laser processing step of providing processing marks to the inside of the substrate (2), a division step of creating a plurality of light-emitting devices (1) while forming a division surface of the substrate (2) to have a rough surface.Type: GrantFiled: May 12, 2009Date of Patent: January 6, 2015Assignee: Toyoda Gosei Co., Ltd.Inventors: Susumu Sugano, Hisayuki Miki, Hironao Shinohara
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Patent number: 8906752Abstract: Ink compositions comprising polythiophenes and methicone that are formulated for inkjet printing the hole injecting layer (HIL) of an organic light emitting diode (OLED) are provided. Also provided are methods of inkjet printing the HILs using the ink compositions.Type: GrantFiled: December 4, 2013Date of Patent: December 9, 2014Assignee: Kateeva, Inc.Inventors: Inna Tregub, Rajsapan Jain, Michelle Chan
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Patent number: 8900912Abstract: Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate). In some embodiments of the invention, a system having an array of frontside illuminated (FSI) imaging pixels is bonded to a system having an array of backside illuminated (BSI) imaging pixels, creating a camera assembly with a minimal size (e.g., a reduced thickness compared to prior art solutions). An FSI image sensor wafer may be used as a handle wafer for a BSI image sensor wafer when it is thinned, thereby decreasing the thickness of the overall camera module. According to other embodiments of the invention, two package dies, one a BSI image sensor, the other an FSI image sensor, are stacked on a common substrate such as a printed circuit board, and are operatively coupled together via redistribution layers.Type: GrantFiled: June 26, 2013Date of Patent: December 2, 2014Assignee: OmniVision Technologies, Inc.Inventors: Gang Chen, Ashish Shah, Duli Mao, Hsin-Chih Tai, Howard E. Rhodes
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Patent number: 8871574Abstract: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.Type: GrantFiled: August 5, 2013Date of Patent: October 28, 2014Assignee: Micron Technology, Inc.Inventor: Chandra Mouli
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Patent number: 8853544Abstract: Various aspects of the present invention provide a transfer method for peeling off an MIM structure (comprising lower electrode/dielectric layer/upper electrodes) film formed on a supporting substrate and then transferring onto a transfer substrate with sufficiently uniform and low damage. Various aspects of the present invention also provide a thin film element provided with one or more thin film components which are transferred onto a substrate by using said method.Type: GrantFiled: March 9, 2012Date of Patent: October 7, 2014Assignee: Taiyo Yuden Co., Ltd.Inventors: Ryuichi Kondou, Kenichi Ota
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Patent number: 8779405Abstract: A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.Type: GrantFiled: June 1, 2012Date of Patent: July 15, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Feng Zhou, Frank K. Baker, Jr., Ko-Min Chang, Cheong Min Hong
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Patent number: 8772836Abstract: To provide a semiconductor device in which a rectifying element capable of reducing a leak current in reverse bias when a high voltage is applied and reducing a forward voltage drop Vf and a transistor element are integrally formed on a single substrate. A semiconductor device has a transistor element and a rectifying element on a single substrate. The transistor element has an active layer formed on the substrate and three electrodes (source electrode, drain electrode, and gate electrode) disposed on the active layer. The rectifying element has an anode electrode disposed on the active layer, a cathode electrode which is the drain electrode, and a first auxiliary electrode between the anode electrode and cathode electrode.Type: GrantFiled: March 8, 2011Date of Patent: July 8, 2014Assignee: Sanken Electric Co., Ltd.Inventor: Osamu Machida
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Patent number: 8766367Abstract: A textured thin film transistor is comprised of an insulator sandwiched between a textured gate electrode and a semi-conductor. A source electrode and drain electrode are fabricated on a surface of the semi-conductor. The textured gate electrode is fabricated such that a surface is modified in its texture and/or geometry, such modifications affecting the transistor current.Type: GrantFiled: June 30, 2011Date of Patent: July 1, 2014Assignee: Palo Alto Research Center IncorporatedInventors: Sanjiv Sambandan, Robert A. Street
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Patent number: 8765584Abstract: A semiconductor device and a manufacturing method therefor, wherein, during lift-off, no cracks due to internal stresses occur in the compound semiconductor layer. A method for manufacturing a semiconductor device having a structure in which a semiconductor layer is bonded on a supporting substrate, including: a device region formation step of forming a device region including the semiconductor layer on a growth substrate through a lift-off layer; a columnar member formation step of forming a columnar member on the growth substrate; a bonding step of bonding the tops of the semiconductor layer and the columnar member to a supporting substrate; a lift-off step of separating the bottom face of the semiconductor layer from the growth substrate by removing the lift-off layer, and not separating the columnar member from the growth substrate; and a step of separating the columnar member from the supporting substrate.Type: GrantFiled: July 26, 2011Date of Patent: July 1, 2014Assignee: Dowa Electronics Materials Co., Ltd.Inventors: Yoshitaka Kadowaki, Tatsunori Toyota
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Patent number: 8759164Abstract: In a method for manufacturing an integral imaging device, a layer of curable adhesive is first applied on a flexible substrate and half cured such that the curable adhesive is solidified but is capable of deforming under external forces. Then the curable adhesive is printed into a lenticular lens having a predetermined shape and size using a roll-to-roll processing device and fully cured such that the curable adhesive is capable of withstanding external forces to hold the predetermined shape and size. Last, a light emitting diode display is applied on the flexible substrate opposite to the lenticular lens such that an image plane of the light emitting diode display coincides with a focal plane of the lenticular lens.Type: GrantFiled: June 20, 2012Date of Patent: June 24, 2014Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Chia-Ling Hsu
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Patent number: 8753947Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.Type: GrantFiled: February 4, 2012Date of Patent: June 17, 2014Assignees: NthDegree Technologies Worldwide Inc, NASAInventors: William Johnstone Ray, Mark David Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
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Patent number: 8753946Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.Type: GrantFiled: February 4, 2012Date of Patent: June 17, 2014Assignees: NthDegree Technologies Worldwide Inc, NASA, an agency of the United StatesInventors: William Johnstone Ray, Mark David Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
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Patent number: 8741700Abstract: Methods for making non-volatile switches include depositing gate material in a recess of a substrate; depositing drain metal in a recess of the gate material; planarizing the gate material, drain metal, and substrate; forming sidewalls by depositing material on the substrate around the gate material; forming a flexible conductive element between the sidewalls to establish a gap between the flexible conductive element and the gate material, such that the gap separating the flexible conductive element and the gate material is sized to create a negative threshold voltage at the gate material for opening a circuit; and forming a source terminal in electrical contact with the flexible conductive element.Type: GrantFiled: August 20, 2013Date of Patent: June 3, 2014Assignee: International Business Machines CorporationInventors: Dechao Guo, Shu-Jen Han, Fei Liu, Keith Kwong Hon Wong, Jun Yuan
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Patent number: 8728879Abstract: Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl3, and a pH adjuster.Type: GrantFiled: July 12, 2012Date of Patent: May 20, 2014Assignee: Intermolecular, Inc.Inventors: Bob Kong, Tony Chiang, Chi-I Lang, Zhi-Wen Wen Sun, Jinhong Tong
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Patent number: 8673700Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.Type: GrantFiled: April 27, 2011Date of Patent: March 18, 2014Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Mark L. Rinehimer, Praveen Muraleedharan Shenoy
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Patent number: 8609475Abstract: Methods for forming a NiO film on a substrate for use with a resistive switching memory device are presenting including: preparing a nickel ion solution; receiving the substrate, where the substrate includes a bottom electrode, the bottom electrode utilized as a cathode; forming a Ni(OH)2 film on the substrate, where the forming the Ni(OH)2 occurs at the cathode; and annealing the Ni(OH)2 film to form the NiO film, where the NiO film forms a portion of a resistive switching memory element. In some embodiments, methods further include forming a top electrode on the NiO film and before the forming the Ni(OH)2 film, pre-treating the substrate. In some embodiments, methods are presented where the bottom electrode and the top electrode are a conductive material.Type: GrantFiled: September 4, 2012Date of Patent: December 17, 2013Assignee: Intermolecular, Inc.Inventors: Zhi-Wen Sun, Tony Chiang, Chi-I Lang, Jinhong Tong
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Patent number: 8575012Abstract: A semiconductor device production method includes: forming an insulating film on a semiconductor substrate, forming a concave portion in the insulating film, forming a gate insulating film at bottom of the concave portion, the bottom being on the semiconductor substrate; covering an inner wall surface of the concave portion and a top face of the insulating film with a first gate electrode film that is made of an electrically conductive material containing a first metal; covering the first gate electrode film with a covering film of a material having a second melting point higher than a first melting point of the electrically conductive material, leaving part of the side face of the concave portion uncovered; and performing heat treatment following the covering film formation to allow the first gate electrode film to reflow.Type: GrantFiled: April 28, 2011Date of Patent: November 5, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Masaki Haneda
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Patent number: 8557654Abstract: A punch-through diode and method of fabricating the same are disclosed herein. The punch-through diode may be used as a steering element in a memory device having a reversible resistivity-switching element. For example, a memory cell may include a reversible resistivity-switching element in series with a punch-through diode. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. In other words, the ratio of Ion/Ioff is high. Therefore, the punch-through diode is compatible with bipolar switching in cross-point memory arrays having resistive switching elements.Type: GrantFiled: December 13, 2010Date of Patent: October 15, 2013Assignee: SanDisk 3D LLCInventors: Peter Rabkin, Andrei Mihnea
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Patent number: 8536607Abstract: An LED base plate enabling the LED to emit high luminance white light. The base plate has a reflective surface, and protrusions disposed on the reflective surface have top portions formed with curved surfaces. The protrusions have bottom widths of 2 to 4 micrometers and heights of 1.2 to 1.8 micrometers, with adjacent protrusions having spaces of 0.6 to 3 micrometers. An InGaN epitaxy layer is coated on the reflective surface of the base plate and emits ultraviolet of wavelength in the range of 380 to 410 nanometer when the InGaN epitaxy layer is electrified. Ultraviolet light reflected by the reflective surface of the base plate and the protrusions stimulates and mixes fluorescent compounds of zinc oxide and yttrium aluminum garnet to generate complementary light of ultraviolet light. High luminance white light scatteringly emitted is used for illumination.Type: GrantFiled: February 15, 2012Date of Patent: September 17, 2013Inventor: Yu-Feng Chuang
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Patent number: 8518754Abstract: An organic EL display including a plurality of pixels each having, in order from a substrate side, a first electrode, an organic layer including a light emission layer, and a second electrode; an auxiliary wiring disposed in a periphery region of each of the plurality of pixels and conducted to the second electrode; and another auxiliary wiring disposed apart from the auxiliary wiring at least in a part of outer periphery of a formation region of the auxiliary wiring in a substrate surface.Type: GrantFiled: April 6, 2012Date of Patent: August 27, 2013Assignee: Sony CorporationInventors: Kazunari Takagi, Kazuo Nakamura
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Patent number: 8507328Abstract: A semiconductor structure includes a module with a plurality of die regions, a plurality of light-emitting devices disposed upon the substrate so that each of the die regions includes one of the light-emitting devices, and a lens board over the module and adhered to the substrate with glue. The lens board includes a plurality of microlenses each corresponding to one of the die regions, and at each one of the die regions the glue provides an air-tight encapsulation of one of the light-emitting devices by a respective one of the microlenses. Further, phosphor is included as a part of the lens board.Type: GrantFiled: May 27, 2011Date of Patent: August 13, 2013Assignee: TSMC Solid State Lighting Ltd.Inventors: Tien-Ming Lin, Chih-Hsuan Sun, Wei-Yu Yeh
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Publication number: 20130187173Abstract: In one general aspect, a silicon carbide bipolar junction transistor (BJT) can include a collector region, a base region on the collector region, and an emitter region on the base region. The silicon carbide BJT can include a base contact electrically contacting the base region where the base region having an active part interfacing the emitter region. The silicon carbide BJT can also include an intermediate region of semiconductor material having at least a part extending from the active part of the base region to the base contact where the intermediate region having a doping level higher than a doping level of the active part of the base region.Type: ApplicationFiled: January 11, 2013Publication date: July 25, 2013Applicant: FAIRCHILD SEMICONDUCTOR CORPORATIONInventor: Fairchild Semiconductor Corporation
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Patent number: 8476085Abstract: The present invention discloses a method of fabricating dual trench isolated epitaxial diode array. This method starts with the formation of heavily-doped first conductivity type regions and heavily-doped second conductivity type regions on the substrate, followed by epitaxial growth, then the formation of the isolations between diode array word lines by deep trench etch and the formation of the isolations between bit lines vertical to deep trenches by shallow trench etch, and finally the formation of separate diode array cells in the regions enclosed by deep and shallow trench isolations by ion implantation. This invention also provides a method of preventing the crosstalk current between adjacent word lines and bit lines of epitaxial diode arrays isolated by foregoing dual shallow trenches.Type: GrantFiled: June 23, 2011Date of Patent: July 2, 2013Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of SciencesInventors: Chao Zhang, Zhitang Song, Xudong Wan, Bo Liu, Guanping Wu, Ting Zhang, Zuoya Yang, Zhifeng Xie
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Patent number: 8445319Abstract: A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0<x<2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x<y<2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer.Type: GrantFiled: August 8, 2011Date of Patent: May 21, 2013Assignee: Panasonic CorporationInventors: Yoshihiko Kanzawa, Koji Katayama, Satoru Fujii, Shunsaku Muraoka, Koichi Osano, Satoru Mitani, Ryoko Miyanaga, Takeshi Takagi, Kazuhiko Shimakawa
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Patent number: 8424190Abstract: A method of providing electrostatic discharge (ESD) protection for a read element in a magnetic storage system comprises coupling a first terminal of a shunting device to a first terminal of the read element; coupling a second terminal of the shunting device to a second terminal of the read element; providing a conductive path between the first and second terminals of the shunting device when the read element is disabled; and providing a nonconductive path between the first and second terminals of the shunting device when the read element is enabled.Type: GrantFiled: October 23, 2007Date of Patent: April 23, 2013Assignee: Marvell International Ltd.Inventor: Pantas Sutardja
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Patent number: 8395568Abstract: The present invention provides an electronic apparatus, such as a lighting device comprised of light emitting diodes (LEDs) or a power generating apparatus comprising photovoltaic diodes, which may be created through a printing process, using a semiconductor or other substrate particle ink or suspension and using a lens particle ink or suspension. An exemplary apparatus comprises a base; at least one first conductor; a plurality of substantially spherical or optically resonant diodes coupled to the at least one first conductor; at least one second conductor coupled to the plurality of diodes; and a plurality of substantially spherical lenses suspended in a polymer attached or deposited over the diodes. The lenses and the suspending polymer have different indices of refraction. In some embodiments, the lenses and diodes have a ratio of mean diameters or lengths between about 10:1 and 2:1.Type: GrantFiled: September 15, 2009Date of Patent: March 12, 2013Assignees: NthDegree Technologies Worldwide Inc, The United States of America as represented by the United States National Aeronautics and Space AdministrationInventors: William Johnstone Ray, Mark D. Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
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Patent number: 8384630Abstract: The present invention provides an electronic apparatus, such as a lighting device comprised of light emitting diodes (LEDs) or a power generating apparatus comprising photovoltaic diodes, which may be created through a printing process, using a semiconductor or other substrate particle ink or suspension and using a lens particle ink or suspension. An exemplary apparatus comprises a base; at least one first conductor; a plurality of diodes coupled to the at least one first conductor; at least one second conductor coupled to the plurality of diodes; and a plurality of lenses suspended in a polymer deposited or attached over the diodes. The lenses and the suspending polymer have different indices of refraction. In some embodiments, the lenses and diodes are substantially spherical, and have a ratio of mean diameters or lengths between about 10:1 and 2:1. The diodes may be LEDs or photovoltaic diodes, and in some embodiments, have a junction formed at least partially as a hemispherical shell or cap.Type: GrantFiled: September 15, 2009Date of Patent: February 26, 2013Assignees: NthDegree Technologies Worldwide Inc, NASA, an agency of the United StatesInventors: William Johnstone Ray, Mark D. Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
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Patent number: 8372698Abstract: A semiconductor device having a modified recess channel gate includes active regions defined by a device isolation layer and arranged at regular intervals on a semiconductor substrate, each active region extending in a major axis and a minor axis direction, a trench formed in each active region, the trench including a stepped bottom surface in the minor axis direction of the active region, and a recess gate formed in the trench.Type: GrantFiled: March 14, 2011Date of Patent: February 12, 2013Assignee: Hynix Semiconductor Inc.Inventor: Tae Kyun Kim
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Patent number: 8372697Abstract: Novel silicon dioxide and silicon nitride deposition methods are generally disclosed. In one embodiment, the method includes depositing silicon on the surface of a substrate having a temperature of between about 65° C. and about 350° C. The heated substrate is exposed to a silicon source that is substantially free from an oxidizing agent. The silicon on the surface is then oxidized with an oxygen source that is substantially free from a silicon source. As a result of oxidizing the silicon, a silicon oxide layer forms on the surface of the substrate. Alternatively, or in additionally, a nitrogen source can be provided to produce silicon nitride on the surface of the substrate.Type: GrantFiled: May 7, 2007Date of Patent: February 12, 2013Assignee: University of South CarolinaInventors: Asif Khan, Vinod Adivarahan
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Patent number: 8298875Abstract: A method to fabricate a junction-less transistor comprising: forming at least two regions of semiconductor doping; first region with a relatively high level of dopant concentration and second region with at least 1/10 lower dopant concentration, and etching away a portion of said first region for the formation of the transistor gate.Type: GrantFiled: March 6, 2011Date of Patent: October 30, 2012Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Paul Lim
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Patent number: 8283214Abstract: Methods for forming a NiO film on a substrate for use with a resistive switching memory device are presenting including: preparing a nickel ion solution; receiving the substrate, where the substrate includes a bottom electrode, the bottom electrode utilized as a cathode; forming a Ni(OH)2 film on the substrate, where the forming the Ni(OH)2 occurs at the cathode; and annealing the Ni(OH)2 film to form the NiO film, where the NiO film forms a portion of a resistive switching memory element. In some embodiments, methods further include forming a top electrode on the NiO film and before the forming the Ni(OH)2 film, pre-treating the substrate. In some embodiments, methods are presented where the bottom electrode and the top electrode are a conductive material such as: Ni, Pt, Ir, Ti, Al, Cu, Co, Ru, Rh, a Ni alloy, a Pt alloy, an Ir alloy, a Ti alloy, an Al alloy, a Cu alloy, a Co alloy, an Ru alloy, and an Rh alloy.Type: GrantFiled: December 21, 2007Date of Patent: October 9, 2012Assignee: Intermolecular, Inc.Inventors: Zhi-Wen Sun, Jinhong Tong, Chi-I Lang, Tony Chiang
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Patent number: 8252610Abstract: A method for making a light emitting diode is provided, which includes first providing a light emitting diode chip. The light emitting diode chip includes a substrate and a p-type semiconductor layer, an active layer and an n-type semiconductor layer sequentially formed on the substrate. And then sections with different resistance are formed in the n-type semiconductor layer by implanting ions into the n-type semiconductor layer in an ion implanter. Finally, an electrode pad is deposited on the n-type semiconductor layer. The electrical resistances of the sections increase following an increase of a distance from the electrode pad to the sections.Type: GrantFiled: September 17, 2010Date of Patent: August 28, 2012Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Chih-Chen Lai