Abstract: There is provided a film-forming apparatus, comprising: a process container in which a vacuum atmosphere is formed; a rotary table installed in the process container, the rotary table having substrate mounting regions formed on a side of a top surface of the rotary table and configured to mount a plurality of substrates, and the rotary table including a rotary mechanism configured to rotate the substrate mounting regions around a rotary shaft; a heating mechanism configured to heat the substrates mounted on the substrate mounting regions; a gas supply part installed to face a moving region where the substrates move when the rotary table rotates and including gas discharge holes formed to cross the moving region, the gas discharge holes being configured to discharge a first film-forming gas and a second film-forming gas; and an exhaust part configured to exhaust an interior of the process container.

Abstract: A method for manufacturing an SOI wafer, including steps of: bonding a bond wafer and a base wafer each composed of a silicon wafer at room temperature with a silicon oxide film interposed therebetween; a thinning the bond wafer; and before the bonding step, cleaning the wafers with a hydrophilic cleaning liquid and drying the cleaned wafers by suction drying or spin drying. After the drying step is ended and before the bonding step is started, the wafers are stored until a state where a bonding speed at which the bonding step is to be performed is 20 mm/second or less. The bonding is performed with the bonding speed of 20 mm/second or less. This provides a method for manufacturing an SOI wafer by which an SOI wafer can be manufactured while generation of outer-peripheral micro voids is suppressed in a simple manner.

Abstract: A semiconductor device disclosed herein is provided with: a source electrode; a gate electrode; a drain electrode; a first region of a first conductivity type formed in a range exposed at an upper surface of the semiconductor substrate a second region of a second conductivity type; a third region of the first conductivity type; and a fourth region of the first conductivity type. The fourth region includes: a first drift region formed in a range exposed at the upper surface; a second drift region having a first conductivity type impurity concentration higher than that of the first drift region, and adjacent to the first drift region; and a low concentration drift region having a first conductivity type impurity concentration lower than that of the first drift region. The first drift region is projected to a second region side than the second drift region.

Abstract: A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.

Abstract: A fin-type field effect transistor including at least one fin-type semiconductor structure, a gate strip and a gate insulating layer is provided. The fin-type semiconductor structure is doped with a first type dopant and has a block region with a first doping concentration and a channel region with a second doping concentration. The first doping concentration is larger than the second doping concentration. The blocking region has a height. The channel region is configured above the blocking region. The gate strip is substantially perpendicular to the fin-type semiconductor structure and covers above the channel region. The gate insulating layer is disposed between the gate strip and the fin-type semiconductor structure.

Abstract: A semiconductor device is formed having compatibility with FINFET process flow, while having a large enough junction area of to reduce the discharge ESD current density. Embodiments include forming a removable gate over an N? doped fin on a substrate, forming P+ doped SiGe or Si on an anode side of the fin, and forming N+ doped Si on a cathode side of the fin. The area efficiency of the semiconductor device layout is greatly improved, and, thereby, discharge of ESD current density is mitigated.

Abstract: A device and method for semiconductor fabrication includes forming a buffer layer on a semiconductor substrate and depositing an amorphous elemental layer on the buffer layer. Elements of the elemental layer are diffused through the buffer layer and into the semiconductor layer.

Abstract: In a transistor including an oxide semiconductor film, a metal oxide film for preventing electrification which is in contact with the oxide semiconductor film and covers a source electrode and a drain electrode is formed. Then, oxygen is introduced (added) to the oxide semiconductor film through the metal oxide film and heat treatment is performed. Through these steps of oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor film, so that the oxide semiconductor film is highly purified. Further, by providing the metal oxide film, generation of a parasitic channel on a back channel side of the oxide semiconductor film can be prevented in the transistor.

Abstract: A purpose of the invention is to provide a method for leveling a semiconductor layer without increasing the number and the complication of manufacturing processes as well as without deteriorating a crystal characteristic, and a method for leveling a surface of a semiconductor layer to stabilize an interface between the surface of the semiconductor layer and a gate insulating film, in order to achieve a TFT having a good characteristic. In an atmosphere of one kind or a plural kinds of gas selected from hydrogen or inert gas (nitrogen, argon, helium, neon, krypton and xenon), radiation with a laser beam in the first, second and third conditions is carried out in order, wherein the first condition laser beam is radiated for crystallizing a semiconductor film or improving a crystal characteristic; the second condition laser beam is radiated for eliminating an oxide film; and the third condition laser beam is radiated for leveling a surface of the crystallized semiconductor film.

Abstract: A thin film transistor for a thin film transistor liquid crystal display (TFT-LCD), an array substrate and manufacturing method thereof are provided. The thin film transistor comprises a source electrode, a drain electrode, and a channel region between the source electrode and drain electrode. A source extension region is connected with the source electrode, a drain extension region is connected with the drain electrode, and the source extension region is disposed opposite to the drain extension region to form a channel extension region therebetween.

Abstract: A semiconductor device includes: a substrate; and depletion and enhancement mode JFETs. The depletion mode JFET includes: a concavity on the substrate; a channel layer in the concavity; a first gate region on the channel layer; first source and drain regions on respective sides of the first gate region in the channel layer; first gate, source and drain electrodes. The enhancement mode JFET includes: a convexity on the substrate; the channel layer on the convexity; a second gate region on the channel layer; second source and drain regions on respective sides of the second gate region in the channel layer; second gate, source and drain electrodes. A thickness of the channel layer in the concavity is larger than a thickness of the channel layer on the convexity.

Abstract: The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density, and a method of manufacturing such a semiconductor device. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines on the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.

Abstract: The objective is to develop a device that generates power with high efficiency and utilizes the obtained electrical energy effectively without external combustion energy such as fossil fuels or the like. Electrical energy is obtained by carriers passing through a potential barrier due to a field effect, and thus energy is pre-supplied to the carriers to increase the number of carriers contributing to electrical energy generation, whereby a highly efficient field power generation device can be realized.

Abstract: An object is to provide a semiconductor device having stable electric characteristics in which an oxide semiconductor is used. An oxide semiconductor layer is subjected to heat treatment for dehydration or dehydrogenation treatment in a nitrogen gas or an inert gas atmosphere such as a rare gas (e.g., argon or helium) or under reduced pressure and to a cooling step for treatment for supplying oxygen in an atmosphere of oxygen, an atmosphere of oxygen and nitrogen, or the air (having a dew point of preferably lower than or equal to ?40° C., still preferably lower than or equal to ?50° C.) atmosphere. The oxide semiconductor layer is thus highly purified, whereby an i-type oxide semiconductor layer is formed. A semiconductor device including a thin film transistor having the oxide semiconductor layer is manufactured.

Abstract: A method and apparatus of fabricating a thin film transistor array substrate is disclosed, which is capable of reducing fabrication time owing to a simplified fabrication process, wherein at least one of steps for forming a gate pattern, forming a semiconductor pattern, forming a data pattern, removing an ohmic contact layer pattern exposed between source and drain electrode patterns, and forming a conductive layer pattern is performed by a laser scribing process.

Abstract: A method of producing a solid-state image pickup element includes forming a hole portion, forming a first-conductive type high-concentration impurity region in a bottom wall of the hole portion, and forming a first-conductive type high-concentration impurity-doped element isolation region in a part of a sidewall of the hole portion and connected to the first-conductive type high-concentration impurity region. The method also includes forming a second-conductive type photoelectric conversion region beneath the first-conductive type high-concentration impurity region and adapted to undergo a change in charge amount upon receiving light, and forming a transfer electrode formed on the sidewall of the hole portion through a gate dielectric film.

Abstract: The invention relates to a semiconductor device (10) comprising a semiconductor body (1) with a high-ohmic semi-conductor substrate (2) which is covered with a dielectric layer (3, 4) containing charges, on which dielectric layer one or more passive electronic components (20) comprising conductor tracks (20) are provided, wherein, at the location of the passive elements (20), a region (5) is present at the interface between the semiconductor substrate (2) and the dielectric layer (3, 4), as a result of which the conductivity of an electrically conducting channel induced in the device (10) by the charges is limited at the location of the region (5). According to the invention, the region (5) is formed by deposition and comprises a semi-insulating material. As a result, the device (10) has a very low high-frequency power loss because the inversion channel is formed in the semi-insulating region (5).

Abstract: A charge transfer device 1 has an P-type region, an N-type well provided to the surficial portion of the P-type region, and transfer electrodes having P-type conductivity, provided over the N-type substrate while placing an insulating film in between.

Abstract: A method of forming a charge-coupled device including the steps of forming well or substrate of a first conductivity type; a buried channel of a second conductivity type; a plurality of first gate electrodes; partially coating the first gate electrodes with a mask substantially aligned to an edge of the first gate electrodes; implanting ions of the first conductivity type of sufficient energy to penetrate the first gates and into the buried channel; and a plurality of second gate electrodes covering regions each over the buried channel between the first gate electrodes.

Abstract: A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure.

Abstract: An image sensing device can include one or more image sensing cells. Each image sensing cell can have a charge store element formed from a semiconductor material doped to a first conductivity type. The charge store element can be in contact with a channel region formed from a semiconductor material doped to a second conductivity type. The charge store element can have one or more surfaces for exposure to an image source. Each image sensing cell can also include a charge electrode formed from a semiconductor material doped to the first conductivity type that is separated from the charge store element by a semiconductor material doped to the second conductivity type. In addition, one or more current detection electrodes can be included in each image sensing cell. A current detection electrode can pass a current flowing through the channel region in a read operation. Such an image sensing cell can be compact in size and/or have a large image sensing area.

Abstract: A semiconductor device is fabricated with a selected critical dimension. A gate dielectric layer is formed over a semiconductor body. A gate layer comprised of a conductive material, such as polysilicon, is formed over the gate dielectric layer. The gate layer is patterned to form a gate electrode having a first horizontal dimension. One or more growth-stripping operations are performed to reduce a critical dimension of the gate electrode to a second horizontal dimension, where the second horizontal dimension is less than the first horizontal dimension.

Abstract: Methods and apparatus for screening diverse arrays of materials using infrared imaging techniques are provided. Typically, each of the individual materials on the array will be screened or interrogated for the same material characteristic. Once screened, the individual materials may be ranked or otherwise compared relative to each other with respect to the material characteristic under investigation. According to one aspect, infrared imaging techniques are used to identify the active sites within an array of compounds by monitoring the temperature change resulting from a reaction. This same technique can also be used to quantify the stability of each new material within an array of compounds. According to another aspect, identification and characterization of condensed phase products is achieved, wherein library elements are activated by a heat source serially, or in parallel.

Abstract: A method of manufacturing a thin-film solar cell, comprising the steps of: forming an amorphous silicon film on a substrate; placing a metal element that accelerates the crystallization of silicon in contact with the surface of the amorphous silicon film; subjecting the amorphous silicon film to a heat treatment to obtain a crystalline silicon film; depositing a silicon film to which phosphorus has been added in contact with the crystalline silicon film; and subjecting the crystalline silicon film and the silicon film to which phosphorus has been added to a heat treatment to getter the metal element from the crystalline film.

Abstract: A current-controlling device comprising a first conductor, a second conductor, and a tunneling barrier comprising a first insulating layer between the first conductor and the second conductor. The tunneling barrier electrically isolates the first conductor from the second conductor. At least one mobile charge is positionable within the tunneling barrier. The device also includes a gate, wherein a voltage applied to the gate with respect to the substrate (or with respect to a second gate formed on or in the substrate) modulates or moves the mobile charge to a position between the first conductor and the second conductor within the tunneling barrier, thus deforming the shape of the energy barrier between the first conductor and the second conductor. The deformation can cause a current to flow between the conductors when a voltage is present between them due to quantum mechanical tunneling.

Abstract: A thin film transistor of the present invention is provided with (i) a plurality of divided channel regions formed under a gate electrode, and (ii) divided source regions and divided drain regions between which each of the divided channel regions is sandwiched, the divided source regions being connected with one another, and the divided drain regions being connected with one another. Here, the divided channel regions are so arranged that a spacing between the divided channel regions is smaller than a channel divided width which is a width of one divided channel region, the channel divided width is not more than 50 ?m, and the spacing is not less than 3 ?m. With this arrangement, it is possible to provide a thin film transistor capable of obtaining reliability with reducing the variation in threshold voltage by reducing the self-heating at the channel regions, as well as capable of reducing the increase of a layout area.

Abstract: A flexible metal foil substrate organic light emitting diode (OLED) display and a method for forming the same are provided. The method comprises: supplying a metal foil substrate such as titanium (Ti), Inconel alloy, or Kovar, having a thickness in the range of 10 to 500 microns; planarizing the metal foil substrate surface; depositing an electrical isolation layer having a thickness in the range of 0.5 to 2 microns overlying the planarized metal foil substrate surface; depositing amorphous silicon having a thickness in the range of 25 to 150 nanometers (nm) overlying the electrical insulation layer; from the amorphous silicon, forming polycrystalline silicon overlying the electrical insulation layer; forming thin-film transistors (TFTs) in the polycrystalline silicon; and, forming an electronic circuit using the TFTs, such as an OLED display.

Abstract: The present invention is a structure for a fast-dump gate (FDG) and a fast-dump drain (FDD) for a charge coupled device. It is envisioned that the charge coupled device be a horizontal readout register of a solid-state image sensor. This structure uses a third layer of polysilicon (or other suitable gate material) to form the fast-dump gate which is in addition to the other two layers of gate material used to form the gates in the horizontal readout register. This allows the channel region under the fast-dump gate (FDG) to form without the use of highly-doped channel stop regions thereby eliminating any potential wells or barriers that may result in transfer inefficiency often time found with other structures.

Abstract: A method of fabricating a memory cell is described in which an access transistor is first formed on an SOI substrate. The access transistor contains source and drain regions in a semiconductor material layer of the substrate and at least one gate stack which includes a gate region electrically connected with a word line. At least one capacitor is formed con a first side of the substrate and is electrically connected to one of the source and drain regions. At least one bit line conductor is formed on the reverse or flip side of the substrate, wherein the bit line conductor is electrically connected to the other of the source and drain regions. Self-aligned contact openings are formed through insulative material over the substrate to provide vias for the electrical connections for each of the capacitor and bit line conductor. These contact openings and the deposited contact material are substantially preserved throughout the entire fabrication process.

Abstract: To enhance the withstand voltage of an LD MOS transistor, a method of fabricating a semiconductor device according to the invention is characterized in that a process for forming a drift region is composed of a step for implanting phosphorus ions and arsenic ions different in a diffusion coefficient into the superficial layer of a substrate, a step for forming a selective oxide film (a first gate insulating film) 9A and an element isolation film 9B by selective oxidation and diffusing the phosphorus ions and the arsenic ions and a step for implanting and diffusing boron ions, and in that in the step for forming the selective oxide film 9A and the element isolation film 9B by selective oxidation in a state in which an oxide film and a polycrystalline silicon film are laminated on the substrate, only a drift region formation region is selectively oxidized in a state in which the polycrystalline silicon film is removed.

Abstract: A flat panel display device comprising a thin film semiconductor switching element formed on a surface of a substrate, a display electrode connected with the switching element, a semiconductor layer for auxiliary capacity which is electrically connected with the display electrode, a dielectric layer formed on a surface of the semiconductor layer for auxiliary capacity, and a metal layer formed on a surface of the dielectric layer, wherein the auxiliary capacity is constituted by the semiconductor layer for auxiliary capacity, the dielectric layer, and the metal layer, and the semiconductor layer for auxiliary capacity is implanted all over the surface thereof with a high concentration of impurity ion.

Abstract: The invention relates to a process for manufacturing a device comprising electronic components (20a, 20b) in regions (32a, 32b) of a layer of semi conducting material (12), these regions being insulated from each other.

Abstract: Methods of forming front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon capacitors and metal-insulator-silicon capacitors are provided that are capable of incorporating a high-dielectric constant (k of greater than about 8) into the capacitor structure. The inventive methods provide high capacitance/area devices with low series resistance of the top and bottom electrodes for high frequency responses. The inventive methods provide a significant reduction in chip size, especially in analog and mixed-signal applications where large areas of capacitance are used.

Abstract: A method for forming a thin film transistor (TFT) is disclosed. The invention uses metal electroless plating or chemical displacement processes to form metal clusters adjacent the sidewall of amorphous silicon active region pattern so as to crystallize the amorphous silicon amid the subsequently performed metal induced lateral crystallization (MILC) process. The amorphous silicon is crystallized to form polysilicon having parallel grains. Since the amorphous silicon will crystallize with a specific angle which is measured between the grain orientation and the side wall of the amorphous silicon, a tilt channel connecting the source and drain region of the TFT is utilized to upgrade the electron mobility across the tilt channel, wherein the grain orientation of polysilicon in the tilt channel perpendicular to a gate electrode which is subsequently formed above the tilt channel.

Abstract: A laser irradiating apparatus includes a cylindrical lens group that divides a laser beam and a cylindrical lens that re-couples a laser beam as divided. The cylindrical lens is shaped in a parallelogram whose angles are not a right angle, thereby being capable of dispersing a portion where interference is strengthened in a laser beam to restrain irradiation unevenness.

Abstract: A method for manufacturing a thin film transistor is disclosed. Afterforming a channel region on a surface of a substrate, an insulating layer is deposited on the surface of the substrate to cover the channel region. The insulating layer is pataterned such that a portion of the channel region is exposed. Then, a silicon layer and a metal layer are sequentially deposited on the insulating layer. The silicon and metal layers are etched to define source, drain and gate electrode sections. After doping positive ions on a portion corresponding to a MOS circuit portion, an intermediate insulating layer is deposited on the metal layer while covering the source, drain and gate electrode sections. The intermediate insulating layer is patterned to form a plurality of contact holes. An electrode material is deposited on the intermediate insulating layer and patterned to define a pixel electrode section and a wire section.

Abstract: A method of fabricating a memory cell is described in which an access transistor is first formed on an SOI substrate. The access transistor contains source and drain regions in a semiconductor material layer of the substrate and at least one gate stack which includes a gate region electrically connected with a word line. At least one capacitor is formed on a first side of the substrate and is electrically connected to one of the source and drain regions. At least one bit line conductor is formed on the reverse or flip side of the substrate, wherein the bit line conductor is electrically connected to the other of the source and drain regions. Self-aligned contact openings are formed through insulative material over the substrate to provide vias for the electrical connections for each of the capacitor and bit line conductor. These contact openings and the deposited contact material are substantially preserved throughout the entire fabrication process.

Abstract: A gate electrode having a gate length of 0.4 &mgr;m or less is formed on a semiconductor substrate. Gate length of this gate electrode is measured, and dose of ion implantation for forming the source region and the drain region is variably set according to the gate length measured value so that transistor characteristics relating to the short-channel effect comes to a specified level.

Abstract: A solid-state image sensor and a fabricating method thereof in which poly gates in a horizontal charge coupled device (hereinafter referred to as HCCD) are made to have different lengths to omit a barrier ion implanting process step, thus simplifying the entire process and maximizing the charge-transferring efficiency are disclosed, the solid-state image sensor having an HCCD and VCCDs including a well region of a second conductivity type formed in a semiconductor substrate of a first conductivity type; a HCCD of the first conductivity type formed on the well region of the second conductivity type; and a plurality of polygate electrodes having sequentially different lengths repeatedly formed on the semiconductor substrate.

Abstract: A method and apparatus of forming adjacent, non-overlapping CCD electrodes within an image sensing device such the electrodes are U-shaped. The device provided by the disclosed method employs a substrate with a gate dielectric layer formed on a surface of the substrate with a plurality of phases created within the CCD. A deposited silicon layer is placed on the surface of the CCD and a mask is used to cover areas other than the first set of electrodes. Etching takes places leaving the mask areas to the deposited silicon and a set of side walls to the remaining deposited silicon are then oxidized. A first set of electrodes by forming an electrode layer placed over the CCD. CMP is employed to remove remaining deposited silicon layer as well as portions of the electrode layer such that the side walls remain vertical portions to electrode layer remaining in the side walls. The process is then repeated by placing another electrode material layer and another CMP process leaving two sets of adjacent U-shaped gates.

Abstract: A power MOS device that has increased channel width comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a plurality of doped well regions of a second, opposite conduction type and a plurality of heavily doped source regions of the first conduction type at an etched upper surface of the upper layer that comprises parallel corrugations disposed transversely to the source regions. A gate that separates one source region from another comprises an insulating layer and a conductive material. The corrugations provide an increase in width of a channel underlying the gate and the well and source regions.

Abstract: A charge coupled device is disclosed including: a well formed in a substrate, the well having a conductivity opposite to that of the substrate; a first conductivity type of BCCD region formed on the well; a first lightly doped impurity region formed in a predetermined portion of the first conductivity type of BCCD region; a heavily doped impurity region formed in a predetermined portion of the BCCD region, the heavily doped impurity region having a predetermined distance from the first lightly doped impurity region; a second lightly doped impurity region formed between the first lightly doped impurity region and heavily doped impurity region; a first polysilicon gate formed over a portion of the BCCD region, placed between the first lightly doped impurity region and heavily doped impurity region; and a second polysilicon gate formed over the first lightly doped impurity region. The realization of high speed CCD and simplification of the circuit configuration can be obtained by using one-phase clocking.

Abstract: A method for fabricating polycide gate electrodes wherein voids at the silicide/polysilicon interface are eliminated by thermal annealing is described. A layer of gate silicon oxide is grown over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate silicon oxide layer. A silicide layer is formed overlying the polysilicon layer. The semiconductor substrate is annealed by rapid thermal annealing (RTA). Thereafter, an oxide layer is deposited overlying the silicide layer. Because the silicide layer has been annealed, silicon atoms are prevented from diffusing into the silicide layer and forming voids in the polysilicon layer. The silicide, polysilicon and gate silicon oxide layers are patterned to complete fabrication of a gate electrode in the manufacture of an integrated circuit device.

Abstract: A memory cell having a grooved gate formed in a sub-lithographic groove, and methods of making thereof are disclosed. The groove extends the channel length to include the groove sidewalls and width of the groove. Sidewall sections of the channel located along the gate sidewalls have a larger length than the bottom channel section length located along the gate bottom width. Thus, the memory device is primarily controlled by the sidewall channel sections, instead of the bottom channel section. The groove may be a stepped groove formed by a two step etch to further increase the channel length and may be formed centered along the gate conductor width.

Abstract: To provide a manufacturing method of thin film transistors (TFT) using poly-silicone and having an LDD structure. In particular, the LDD sections of the TFTs are formed in an improved method so as to achieve a high throughput and stable performance of the TFTs. To be specific, the LD region is doped at a low concentration in the ion implantation method which includes mass spectrometry because high controllability over a dose is required. On the other hand, the source and drain regions are doped at a higher concentration than the LD region in the ion showering method which does not include mass spectrometry. Using the ion showering method, poly-crystal silicon can be doped such that less doping damage is caused thereto. This makes it possible to apply a lower temperature for annealing, such as RTA, to activate doped impurities so as to prevent the substrate from being curved.

Abstract: In a heat history initializing step, a heat treatment in performed in an atmosphere including at least one of hydrogen, helium, and argon while the temperature is increased in a range of 700.degree. C. to 1,000.degree. C. at a rate of 15.degree.-1,000.degree. C./min. In a controlled nuclei growing step, a heat treatment is performed in the above atmosphere while the temperature is kept constant in a range of 850.degree. C. to 980.degree. C. for 0.5-60 minutes.