Charge Transfer Device (e.g., Ccd, Etc.) Patents (Class 438/144)
  • Patent number: 11136502
    Abstract: Provided are a method of producing a thiogallate-based fluorescent material, a method of producing a light-emitting device, a thiogallate-based fluorescent material, and a light-emitting device. The method of producing a thiogallate-based fluorescent material includes preparing a first solution containing at least one M1 ion selected from the group consisting of Sr, Be, Mg, Ca, Ba and Zn, and at least one M2 ion selected from the group consisting of Eu and Ce, and a second solution containing a sulfite ion, simultaneously supplying the first solution and the second solution to a reactor to obtain a powder containing a sulfite that contains an element M1 and an element M2, mixing a raw material that contains the powder containing the sulfite that contains the element M1 and the element M2 and a powder containing a gallium compound, with lithium chloride to obtain a mixture, and heat-treating the mixture to obtain a thiogallate-based fluorescent material.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: October 5, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Hirofumi Ooguri
  • Patent number: 9591242
    Abstract: An embodiment image sensor includes a pixel region spaced apart from a black level control (BLC) region by a buffer region. In an embodiment, a light shield is disposed over the BLC region and extends into the buffer region. In an embodiment, the buffer region includes an array of dummy pixels. Such embodiments effectively reduce light cross talk at the edge of the BLC region, which permits more accurate black level calibration. Thus, the image sensor is capable of producing higher quality images.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: March 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Volume Chien, Yun-Wei Cheng, Che-Min Lin, Shiu-Ko JangJian, Chi-Cherng Jeng, Chih-Mu Huang
  • Patent number: 9076705
    Abstract: Certain embodiments provide a solid-state imaging apparatus including a first impurity layer, a second impurity layer, a third impurity layer, and an electrode. The first impurity layer is a photoelectric conversion layer, and is formed to have a constant depth on a semiconductor substrate. The second impurity layer is formed on a surface of the first impurity layer, to have a depth which becomes shallower toward a direction from the first impurity layer to the third impurity layer. The third impurity layer is formed in a position spaced apart from the first impurity layer and the second impurity layer on the surface of the semiconductor substrate. The electrode can transport electric charges from the first impurity layer to the third impurity layer, and is formed between the second impurity layer and the third impurity layer, on the surface of the semiconductor substrate.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: July 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoyuki Arai, Fumiaki Sano
  • Patent number: 9029930
    Abstract: A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Andrew Joseph Kelly, Po-Ruwe Tzng, Pei-Shan Chien, Wei-Hsiung Tseng
  • Patent number: 9018086
    Abstract: The present invention provides a method of forming a semiconductor device having a metal gate. A substrate is provided and a gate dielectric and a work function metal layer are formed thereon, wherein the work function metal layer is on the gate dielectric layer. Then, a top barrier layer is formed on the work function metal layer. The step of forming the top barrier layer includes increasing a concentration of a boundary protection material in the top barrier layer. Lastly, a metal layer is formed on the top barrier layer. The present invention further provides a semiconductor device having a metal gate.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: April 28, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Mao Hsu, Hsin-Fu Huang, Chin-Fu Lin, Min-Chuan Tsai, Wei-Yu Chen, Chien-Hao Chen
  • Patent number: 8987041
    Abstract: Certain embodiments provide method for manufacturing a solid-state imaging device, including forming an electrode and forming a second impurity layer. The electrode is formed on a semiconductor substrate including a first impurity layer of a first conductivity type on a surface. The second impurity layer is a second conductivity type and is formed by implanting an impurity of a second conductivity type into the first impurity layer in an oblique direction with respect to the surface of the semiconductor substrate on the condition that the impurity penetrates an end portion of the electrode, based on a position of the electrode. The second impurity layer is bonded to the first impurity layer to constitute a photodiode, and a portion of the second impurity layer is disposed under the electrode.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ken Tomita, Atsushi Sasaki
  • Patent number: 8969875
    Abstract: The present invention relates to a thin film transistor substrate and method for fabricating the same which can secure an alignment margin and reduce the number of mask steps. A thin transistor substrate according to the present invention includes a gate line and a data line crossing each other to define a pixel, a gate metal pattern under the data line, a thin film transistor having a gate electrode, a source electrode and a drain electrode in the pixel, and a pixel electrode connected to the drain electrode of the thin film transistor by a connection electrode, wherein the data line has a plurality of first slits to disconnect the gate metal pattern from the gate line.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: March 3, 2015
    Assignee: LG Display Co., Ltd.
    Inventor: Seung Hee Nam
  • Patent number: 8956907
    Abstract: There is provided a method of fabricating a field effect transistor including: forming a first oxide semiconductor film on a gate insulation layer disposed on a gate electrode; forming a second oxide semiconductor film on the first oxide semiconductor film, the second oxide semiconductor film differing in cation composition from the first oxide semiconductor film and being lower in electrical conductivity than the first oxide semiconductor film; applying a heat treatment at over 300° C. in an oxidizing atmosphere; forming a third oxide semiconductor film on the second oxide semiconductor film, the third oxide semiconductor film differing in cation composition from the first oxide semiconductor film and being lower in electrical conductivity than the first oxide semiconductor film; applying a heat treatment in an oxidizing atmosphere; and, forming a source electrode and a drain electrode on the third oxide semiconductor film.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: February 17, 2015
    Assignee: FUJIFILM Corporation
    Inventors: Masashi Ono, Masahiro Takata, Fumihiko Mochizuki, Atsushi Tanaka, Masayuki Suzuki
  • Patent number: 8952427
    Abstract: A range image sensor capable of improving its aperture ratio and yielding a range image with a favorable S/N ratio is provided. A range image sensor RS has an imaging region constituted by a plurality of one-dimensionally arranged units on a semiconductor substrate 1 and yields a range image according to a charge amount issued from the units.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: February 10, 2015
    Assignee: Hamamatsu Photonics K.K
    Inventors: Takashi Suzuki, Mitsuhito Mase
  • Patent number: 8940575
    Abstract: There is provided a method of producing a semiconductor device. The method includes the steps of: forming a first hard mask having an opening above a substrate; forming a sacrificial film above a side surface of the opening of the first hard mask; forming a second hard mask in the opening having the sacrificial film above the side surface; removing the sacrificial film after the second hard mask is formed; ion implanting a first conductivity-type impurity through the first hard mask; and ion implanting a second conductivity-type impurity through the first and second hard masks.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: January 27, 2015
    Assignee: Sony Corporation
    Inventor: Yasufumi Miyoshi
  • Patent number: 8785240
    Abstract: Provided is a method of producing a light-emitting apparatus having a field effect transistor for driving an organic EL device, the field effect transistor including an oxide semiconductor containing at least one element selected from In and Zn, the method including the steps of: forming a field effect transistor on a substrate; forming an insulating layer; forming a lower electrode on the insulating layer; forming an organic layer for constituting an organic EL device on the lower electrode; forming an upper electrode on the organic layer; and after the step of forming the semiconductor layer of the field effect transistor and before the step of forming the organic layer, performing heat treatment such that an amount of a component that is desorbable as H2O from the field effect transistor during the step of forming the organic layer is less than 10?5 g/m2.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: July 22, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tomohiro Watanabe
  • Patent number: 8772844
    Abstract: Capacitance between a detection capacitor and a reset transistor is the largest among the capacitances between the detection capacitor and transistors placed around the detection capacitor. In order to reduce this capacitance, it is effective to reduce the channel width of the reset transistor. It is possible to reduce the effective channel width by distributing, in the vicinity of the channel of the reset transistor and the boundary line between an active region and an element isolation region, ions which enhance the generation of carriers of an opposite polarity to the channel.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: July 8, 2014
    Assignee: Wi Lan, Inc.
    Inventors: Motonari Katsuno, Ryouhei Miyagawa, Masayuki Matsunaga
  • Patent number: 8716719
    Abstract: Provided is a solid-state imaging device including: a first-conductivity-type substrate; a second-conductivity-type well formed in a surface side of the first-conductivity-type substrate; a photoelectric conversion area configured with a first-conductivity-type-impurity area formed in the second-conductivity-type well to convert incident light to charges; a first-conductivity-type-charge retaining area configured with the first-conductivity-type-impurity area formed in the second-conductivity-type well to retain the charges converted by the photoelectric conversion area until the charges are read out; a charge voltage conversion area configured with the first-conductivity-type-impurity area formed in the second-conductivity-type well to convert the charges retained in the charge retaining area to a voltage; and a first-conductivity-type-layer area configured by forming a first-conductivity-type-in a convex shape from a boundary between the first-conductivity-type substrate and the second-conductivity-type wel
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: May 6, 2014
    Assignee: Sony Corporation
    Inventors: Yusuke Matsumura, Takashi Machida
  • Patent number: 8703556
    Abstract: A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate and fin structures on the substrate. A sidewall spacer is formed along sidewall of fin structures in the precursor. A portion of fin structure is recessed to form a recessing trench with the sidewall spacer as its upper portion. A semiconductor is epitaxially grown in the recessing trench and continually grown above the recessing trench to form an epitaxial structure.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Andrew Joseph Kelly, Po-Ruwe Tzng, Pei-Shan Chien, Wei-Hsiung Tseng
  • Patent number: 8704325
    Abstract: CMOS pixel sensors with multiple pixel sizes and methods of manufacturing the CMOS pixel sensors with implant dose control are provided. The method includes forming a plurality of pixel sensors in a same substrate and forming a masking pattern over at least one of the plurality of pixel sensors that has a pixel size larger than a non-masked pixel sensor of the plurality of pixel sensors. The method further includes providing a single dosage implant to the plurality of pixel sensors. The at least one of the plurality of pixel sensors with the masking pattern receives a lower dosage than the non-masked pixel sensor.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: April 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Jeffery P. Gambino, Daniel N. Maynard, Richard J. Rassel
  • Patent number: 8697500
    Abstract: A method for manufacturing a solid-state image sensor includes forming a gate electrode structure including a gate electrode on a gate insulating film formed on a semiconductor substrate, and implanting ions into a first region and simultaneously implanting the ions into a second region of the semiconductor substrate via the gate electrode structure and the gate insulating film, wherein the first region is a region where a charge accumulation region is to be formed, and the second region is a region where an extended region that extends from the charge accumulation region to a portion below the gate electrode is to be formed, and a mean projected range of the ions in the step of simultaneous implanting of the ions into the first region and the second region is larger than a sum total of thicknesses of the gate electrode and the gate insulating film.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: April 15, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Junji Iwata
  • Patent number: 8691637
    Abstract: Disclosed herein is a solid-state image pickup device including: a photoelectric conversion section configured to convert incident light into a signal charge; a transfer transistor configured to read the signal charge from the photoelectric conversion section and transfer the signal charge; and an amplifying transistor configured to amplify the signal charge read by the transfer transistor, wherein a compressive stress film having a compressive stress is formed on the amplifying transistor.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: April 8, 2014
    Assignee: Sony Corporation
    Inventor: Shinichi Arakawa
  • Patent number: 8658457
    Abstract: There is provided a method of producing a semiconductor device. The method includes the steps of: forming a first hard mask having an opening above a substrate; forming a sacrificial film above a side surface of the opening of the first hard mask; forming a second hard mask in the opening having the sacrificial film above the side surface; removing the sacrificial film after the second hard mask is formed; ion implanting a first conductivity-type impurity through the first hard mask; and ion implanting a second conductivity-type impurity through the first and second hard masks.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: February 25, 2014
    Assignee: Sony Corporation
    Inventor: Yasufumi Miyoshi
  • Patent number: 8658477
    Abstract: An exposure mask according to an embodiment of the invention includes a first transmission region where a plurality of dots through which light is shielded or transmitted are arrayed into a matrix form having rows and columns and a second transmission region where a plurality of dots through which the light is shielded or transmitted are arrayed into a matrix form having rows and columns and is disposed adjacent to the first transmission region. The dots arrayed in a row or a column of the first transmission region, which is adjacent to the second transmission region, have an area intermediate between areas of dots arrayed on both sides of the row or the column.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: February 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ken Tomita
  • Patent number: 8653529
    Abstract: In a semiconductor device in which a glass substrate is attached to a surface of a semiconductor die with an adhesive layer being interposed therebetween, it is an object to fill a recess portion of an insulation film formed on a photodiode with the adhesive layer without bubbles therein. In a semiconductor die in which an optical semiconductor integrated circuit including a photodiode having a recess portion of an interlayer insulation film in the upper portion, an NPN bipolar transistor, and so on are formed, generally, a light shield film covers a portion except the recess portion region on the photodiode and except a dicing region. In the invention, an opening slit is further formed in the light shield film, extending from the recess portion to the outside of the recess portion, so as to attain the object.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: February 18, 2014
    Assignee: ON Semiconductor Trading, Ltd.
    Inventors: Shinzo Ishibe, Katsuhiko Kitagawa
  • Patent number: 8581306
    Abstract: A nanoscale electron shuttle with two elastically mounted conductors positioned within a gap between conductors produces asymmetrical electron conduction between the conductors when the conductors receive an AC signal to provide for rectification, detection and/or power harvesting.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: November 12, 2013
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Robert H. Blick, Chulki Kim, Jonghoo Park
  • Patent number: 8574941
    Abstract: A method for manufacturing a solid-state imaging device in which a charge generator that detects an electromagnetic wave and generates signal charges is formed on a semiconductor substrate and a negative-charge accumulated layer having negative fixed charges is formed above a detection plane of the charge generator. The method includes the steps of: forming an oxygen-feed film capable of feeding oxygen on the detection plane of the charge generator; forming a metal film that covers the oxygen-feed film on the detection plane of the charge generator; and performing heat treatment for the metal film in an inactive atmosphere to thereby form an oxide of the metal film between the metal film and the oxygen-feed film on the detection plane of the charge generator, the oxide being to serve as the negative-charge accumulated layer.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: November 5, 2013
    Assignee: Sony Corporation
    Inventors: Susumu Hiyama, Tomoyuki Hirano
  • Patent number: 8551810
    Abstract: In a transistor including an oxide semiconductor film, a metal oxide film for preventing electrification which is in contact with the oxide semiconductor film and covers a source electrode and a drain electrode is formed. Then, oxygen is introduced (added) to the oxide semiconductor film through the metal oxide film and heat treatment is performed. Through these steps of oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor film, so that the oxide semiconductor film is highly purified. Further, by providing the metal oxide film, generation of a parasitic channel on a back channel side of the oxide semiconductor film can be prevented in the transistor.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: October 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8536625
    Abstract: An electronic image sensor includes a semiconductor substrate having a first surface configured for accepting illumination to a pixel array disposed in the substrate. An electrically-doped channel region for each pixel is disposed at a second substrate surface opposite the first substrate surface. The channel regions are for collecting photogenerated charge in the substrate. An electrically-doped channel stop region is at the second substrate surface between each channel region. An electrically-doped shutter buried layer, disposed in the substrate at a depth from the second substrate surface that is greater than that of the pixel channel regions, extends across the pixel array. An electrically-doped photogenerated-charge-extinguishment layer, at the first substrate surface, extends across the pixel array.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: September 17, 2013
    Assignee: Massachusetts Institute of Technology
    Inventor: Barry E. Burke
  • Patent number: 8519456
    Abstract: A solid-state image pickup device in which electric charges accumulated in a photodiode conversion element are transferred to a second diffusion layer through a first diffusion layer.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: August 27, 2013
    Assignee: Sony Corporation
    Inventors: Atsushi Masagaki, Ikuhiro Yamamura
  • Patent number: 8383443
    Abstract: A non-uniform gate dielectric charge for pixel sensor cells, e.g., CMOS optical imagers, and methods of manufacturing are provided. The method includes forming a gate dielectric on a substrate. The substrate includes a source/drain region and a photo cell collector region. The method further includes forming a non-uniform fixed charge distribution in the gate dielectric. The method further includes forming a gate structure on the gate dielectric.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: February 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Andres Bryant, William F. Clark, Jr., John J. Ellis-Monaghan, Edward J. Nowak
  • Patent number: 8383448
    Abstract: A method of fabricating an MOS device is provided. First, gates and source/drain regions of transistors are formed on a substrate. A photodiode doped region and a floating node doped region are formed in the substrate. Thereafter, a spacer stacked layer including a bottom layer, an inter-layer and a top layer is formed to cover each gate of the transistors. Afterwards, a first mask layer having an opening exposing at least the photodiode doped region is formed on the substrate, and then the top layer exposed by the opening is removed. Next, the first mask layer is removed, and then a second mask layer is formed on a region correspondingly exposed by the opening. A portion of the top layer and the inter-layer exposed by the second mask layer is removed to form spacers on sidewalls of the gates.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: February 26, 2013
    Assignee: United Microelectronics Corp.
    Inventor: Ching-Hung Kao
  • Patent number: 8372699
    Abstract: A method for forming a semiconductor device includes forming a first semiconductor layer over a substrate, forming a first photoresist layer over the first semiconductor layer, and using only a first single mask patterning the first photoresist layer to form a first patterned photoresist layer. The method further includes using the first patterned photoresist layer etching the first semiconductor layer to form a select gate and forming a charge storage layer over the select gate and a portion of the substrate. The method further includes forming a second semiconductor layer over the charge storage layer, forming a second photoresist layer over the second semiconductor layer, and using only a second single mask patterning the second photoresist layer to form a second patterned photoresist layer. The method further includes forming a control gate by anisotropically etching the second semiconductor layer and then subsequently isotropically etching the second semiconductor layer.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: February 12, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sung-Taeg Kang, Jane A. Yater
  • Patent number: 8362565
    Abstract: A semiconductor device includes: a semiconductor layer; an element isolation region formed in the semiconductor layer for separation between a memory element part and a logic element part; first and second field-effect transistors formed in the memory element part and having first and second gate electrodes on a first surface side of the semiconductor layer and a second surface side opposite to the first surface, respectively, and having a source and drain region in common with each other; a third field-effect transistor formed in the logic element part and having a third gate electrode on the second surface side; and first and second insulating films formed on the semiconductor layer to cover the first field-effect transistor and the second and third field-effect transistors, respectively. The first field-effect transistor and the second field-effect transistor are fully-depleted field-effect transistors. The first gate electrode and the second gate electrode are electrically connected.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: January 29, 2013
    Assignee: Sony Corporation
    Inventor: Hideaki Kuroda
  • Patent number: 8361898
    Abstract: A bonding pad structure for an optoelectronic device. The bonding pad structure includes a carrier substrate having a bonding pad region and an optoelectronic device region. An insulating layer is disposed on the carrier substrate, having an opening corresponding to the bonding pad region. A bonding pad is embedded in the insulating layer under the opening to expose the top surface thereof. A device substrate is disposed on the insulating layer corresponding to the optoelectronic device region. A cap layer covers the device substrate and the insulating layer excluding the opening. A conductive buffer layer is disposed in the opening to directly contact the bonding pad. The invention also discloses a method for fabricating the same.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: January 29, 2013
    Assignee: VisEra Technologies Company Limited
    Inventors: Kai-Chih Wang, Fang-Chang Liu
  • Patent number: 8354292
    Abstract: In a method of manufacturing a CMOS image sensor, a P type epitaxial layer is formed on an N type substrate. A deep P+ type well layer is formed in the P type epitaxial layer. An N type deep guardring well is formed in a photodiode guardring region. The N type deep guardring region makes contact with the N type substrate and also be connected with an operational voltage terminal. A triple well is formed in a photodiode region and a peripheral circuit region. The triple well is used for forming a PMOS and an NMOS having different operational voltages. An isolation region is formed in the photodiode region. The isolation region in the photodiode region has a depth different from a depth of an isolation region in the peripheral circuit region.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: January 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Je Park, Young-Hoon Park, Ui-Sik Kim, Dae-Cheol Seong, Yeo-Ju Yoon, Bo-Bae Kang
  • Patent number: 8334195
    Abstract: CMOS pixel sensors with multiple pixel sizes and methods of manufacturing the CMOS pixel sensors with implant dose control are provided. The method includes forming a plurality of pixel sensors in a same substrate and forming a masking pattern over at least one of the plurality of pixel sensors that has a pixel size larger than a non-masked pixel sensor of the plurality of pixel sensors. The method further includes providing a single dosage implant to the plurality of pixel sensors. The at least one of the plurality of pixel sensors with the masking pattern receives a lower dosage than the non-masked pixel sensor.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: December 18, 2012
    Assignee: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Daniel N. Maynard, Richard J. Rassel
  • Patent number: 8323860
    Abstract: A solid-state imaging device producing method includes the steps of: applying a resist material onto a substrate in which a channel region is formed; forming a resist layer by exposure and development of the resist material using a mask, the resist layer having an opening and a thin-film portion, the mask having a first region through which light is transmitted and a second region through which a smaller quantity of light than that the light transmitted through the first region is transmitted; subjecting the substrate to ion implantation using the resist layer as a mask to form an impurity region; etching the substrate using the resist layer as a mask after the ion implantation to form an alignment mark; and forming an electrode on the impurity region and part of the channel region using the alignment mark as a reference.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: December 4, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shu Sasaki
  • Patent number: 8319878
    Abstract: A solid-state imaging device of the type having photoelectric conversion elements formed in a matrix pattern on a semiconductor substrate, vertical transfer elements each of which reads signal charges from the photoelectric conversion elements arranged in the column direction and transfers the signal charges in the vertical direction, and a horizontal transfer element which transfers in the horizontal direction the signal charges sent from each of the vertical transfer elements, the horizontal transfer element includes: a charge transfer channel; a first transfer electrode; a second transfer electrode; and an interelectrode insulating film; with the first transfer electrode and the second transfer electrode being at the same potential.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: November 27, 2012
    Assignee: Sony Corporation
    Inventors: Takashi Terada, Keisuke Hatano
  • Patent number: 8304776
    Abstract: The present invention relates to a thin film transistor substrate and method for fabricating the same which can secure an alignment margin and reduce the number of mask steps. A thin transistor substrate according to the present invention includes a gate line and a data line crossing each other to define a pixel, a gate metal pattern under the data line, a thin film transistor having a gate electrode, a source electrode and a drain electrode in the pixel, and a pixel electrode connected to the drain electrode of the thin film transistor by a connection electrode, wherein the data line has a plurality of first slits to disconnect the gate metal pattern from the gate line.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: November 6, 2012
    Assignee: LG Display Co., Ltd.
    Inventor: Seung Hee Nam
  • Patent number: 8293561
    Abstract: There is provided an image pickup device, including a photoelectric conversion element converting light into charges, a transfer gate for transferring the converted charges to a floating node, a source follower transistor for outputting a signal based on a voltage of the floating node to a signal line, and a clip circuit clipping the signal line at a first voltage and a second voltage.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: October 23, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takanori Watanabe, Tetsuya Itano, Mahito Shinohara
  • Patent number: 8278131
    Abstract: A method and apparatus for operating an imager pixel that includes the act of applying a relatively small first polarity voltage and a plurality of pulses of a second polarity voltage on the gate of a transfer transistor during a charge integration period.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: October 2, 2012
    Assignee: Micron Technology, Inc.
    Inventor: John Ladd
  • Patent number: 8217431
    Abstract: A solid-state image pickup device for preventing crosstalk between adjacent pixels by providing an overflow barrier at the deep potion of a substrate. A partial P type region is provided at the predetermined position of a lower layer region of the vertical transfer register and a channel stop region. This P type region adjusts potential in the lower layer region of the vertical transfer register and the channel stop region. Accordingly, since the potential in the lower layer region of the vertical transfer register and the channel stop region at both sides of the lower layer region is low, electric charges photoelectrically-converted by the sensor region are blocked by this potential barrier and cannot be diffused easily.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: July 10, 2012
    Assignee: Sony Corporation
    Inventors: Kazushi Wada, Kouichi Harada, Shuji Otsuka, Mitsuru Sato
  • Patent number: 8193031
    Abstract: An object is to provide a semiconductor device having stable electric characteristics in which an oxide semiconductor is used. An oxide semiconductor layer is subjected to heat treatment for dehydration or dehydrogenation treatment in a nitrogen gas or an inert gas atmosphere such as a rare gas (e.g., argon or helium) or under reduced pressure and to a cooling step for treatment for supplying oxygen in an atmosphere of oxygen, an atmosphere of oxygen and nitrogen, or the air (having a dew point of preferably lower than or equal to ?40° C., still preferably lower than or equal to ?50° C.) atmosphere. The oxide semiconductor layer is thus highly purified, whereby an i-type oxide semiconductor layer is formed. A semiconductor device including a thin film transistor having the oxide semiconductor layer is manufactured.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: June 5, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Miyuki Hosoba, Junichiro Sakata, Hiroki Ohara, Shunpei Yamazaki
  • Patent number: 8173476
    Abstract: There is provided an image pickup device, including a photoelectric conversion element converting light into charges, a transfer gate for transferring the converted charges to a floating node, a source follower transistor for outputting a signal based on a voltage of the floating node to a signal line, and a clip circuit clipping the signal line at a first voltage and a second voltage.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: May 8, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takanori Watanabe, Tetsuya Itano, Mahito Shinohara
  • Patent number: 8124443
    Abstract: Diodes having p-type and n-type regions in contact, having at least one of either the p-type region or n-type region including a conjugated organic material doped with an immobile dopant, conjugated organic materials for incorporation into such diodes, and methods of manufacturing such diodes and materials are provided.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: February 28, 2012
    Inventors: Matthew L. Marrocco, Farshad J. Motamedi
  • Patent number: 8119436
    Abstract: An image sensor and a method for manufacturing the same are disclosed. The image sensor can include a semiconductor substrate that includes photodiodes arranged for each unit pixel; an interlayer dielectric layer and metal wirings disposed on the semiconductor substrate; and a photorefractive unit that is formed on the periphery of an optical path incident on the photodiodes. The photorefractive unit has a lower refractive index than the interlayer dielectric layer. The slantly incident light can be incident on the photodiodes, while maintaining the slanted optical path as it is. The light sensitivity of the photodiodes can be improved, thereby improving image quality.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: February 21, 2012
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Seung Ryong Park
  • Patent number: 8115851
    Abstract: A solid-state image capturing apparatus according to the present invention includes: a plurality of photoelectric conversion sections; a charge accumulation section; and a charge readout section, the apparatus further includes: a semiconductor substrate including a plurality of diffusion layers formed thereabove, the diffusion layers constituting the photoelectric conversion sections, the charge accumulation section and the charge readout section; a readout gate electrode formed above the semiconductor substrate and constituting the charge readout section; an insulation sidewall formed on a side surface of the readout gate electrode; and a surface diffusion layer constituting the photoelectric conversion sections, which is positioned in a self-aligning manner with respect to the readout gate electrode by the insulation sidewall.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: February 14, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Akiyoshi Mutoh
  • Patent number: 8114718
    Abstract: Apparatus, systems, and methods are described to assist in reducing dark current in an active pixel sensor. In various embodiments, a potential barrier arrangement is configured to block the flow of charge carriers generated outside a photosensitive region. In various embodiments, a potential well-potential barrier arrangement is formed to direct charge carriers away from the photosensitive region during an integration time.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: February 14, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Chen Xu, Gennadiy Agranov, Igor Karasev
  • Patent number: 8053287
    Abstract: A method of making a backside illuminated sensor is provided. A substrate is provided and a high energy ion implantation is performed over the substrate to implant a first doped region. A layer is formed over the substrate and a self-align high energy ion implantation is performed over the substrate to implant a second doped region over the first doped region. The combined thickness of the first and second doped region is greater than 50 percent of thickness of the substrate and the distance between back surface of the substrate and the first and second doped regions is less than 50 percent of thickness of the substrate. In this way, an enlarged light sensing region is formed through which electrons generated from back surface of the surface may easily reach the pixel.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: November 8, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Hsuan Hsu, Dun-Nian Yaung
  • Patent number: 8031232
    Abstract: The present invention relates to an image pickup apparatus, a method for capturing an image, and a method for designing the image pickup apparatus capable of realizing a fixed focal length image pickup apparatus of high resolution and fine resolution at a low cost by disposing a plurality of image pickup elements therein. An image pickup device 31 is of a focal coincidence type having a plurality of image pickup elements, such as CCD sensors 62-1 to 62-3, arranged in an array.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: October 4, 2011
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Yasushi Tatehira, Tetsushi Kokubo, Kenji Tanaka, Hitoshi Mukai, Hirofumi Hibi, Kazumasa Tanaka
  • Patent number: 8021908
    Abstract: A method and apparatus for operating an imager pixel that includes the act of applying a relatively small first polarity voltage and a plurality of pulses of a second polarity voltage on the gate of a transfer transistor during a charge integration period.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: September 20, 2011
    Assignee: Micron Technology, Inc.
    Inventor: John Ladd
  • Patent number: 8003506
    Abstract: More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region on between adjacent gates, a more complete charge transfer is effected from the charge collecting gate.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: August 23, 2011
    Assignee: Round Rock Research, LLC
    Inventor: Howard E. Rhodes
  • Patent number: 8004020
    Abstract: A solid-state image capturing device includes a plurality of electrode pads for inputting and outputting a signal or voltage from and to the outside, a plurality of photoelectric conversion elements, a planarization film for planarizing the difference in the level on the surface above the plurality of photoelectric conversion elements, a microlens for focusing incident light on each of the plurality of photoelectric conversion elements, and a protection film provided above the microlens and the planarization film, the planarization film and the protection film above the plurality of electrode pads being removed as an opening, where the protection film has a protection film removing area that at least includes an area removed across all or a corner portion of the opening and the image capturing area.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: August 23, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Takayuki Kawasaki
  • Patent number: 7998828
    Abstract: A method of forming a metal ion transistor comprises forming a first electrode in a first isolation layer; forming a second isolation layer over the first isolation layer; forming a first cell region of a low dielectric constant (low-k) dielectric over the first electrode in the second isolation layer, the first cell region isolated from the second isolation layer; forming a cap layer over the second isolation layer and the first cell region, at least thinning the cap layer over the first cell region; depositing a layer of the low-k dielectric over the second isolation layer and the first cell region; forming metal ions in the low-k dielectric layer; patterning the low-k dielectric layer to form a second cell region; sealing the second cell region using a liner; and forming a second electrode contacting the second cell region and a third electrode contacting the second cell region.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: August 16, 2011
    Assignees: International Business Machines Corporation, Infineon Technologies North America
    Inventors: Fen Chen, Armin Fischer