Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions Patents (Class 438/142)
  • Patent number: 10497805
    Abstract: A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate, a gate, a first diffusion region and a second diffusion region. The gate is disposed on the semiconductor substrate and extends along a first direction. The first diffusion region is formed in the semiconductor substrate, and the second diffusion region is formed in the first diffusion region. The first diffusion region has a first portion located underneath the gate and a second portion protruded from a lateral side of the gate, the first portion has a first length parallel to the first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: December 3, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: 10443126
    Abstract: Disclosed herein is a rare-earth oxide coating on a surface of an article with one or more interruption layers to control crystal growth and methods of its formation. The coating may be deposited by atomic layer deposition and/or by chemical vapor deposition. The rare-earth oxides in the coatings disclosed herein may have an atomic crystalline phase that is different from the atomic crystalline phase or the amorphous phase of the one or more interruption layers.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: October 15, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Xiaowei Wu, Jennifer Y. Sun, Michael R. Rice
  • Patent number: 10388745
    Abstract: A method may include providing a transistor structure on a substrate, where the transistor structure includes a semiconductor fin, a source/drain contact forming electrical contact with the semiconductor fin, and a gate conductor, disposed over the semiconductor fin, wherein the source drain contact and gate conductor are disposed in a trench. The method may further include directing angled ions to the trench, wherein the source/drain contact assumes a tapered shape.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: August 20, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventor: Min Gyu Sung
  • Patent number: 10366897
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Patent number: 10347494
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Patent number: 10319596
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Patent number: 10263077
    Abstract: Method for fabricating at least one FET transistor (100a, 100b) comprising: fabrication of at least one first semiconducting portion (114) that will form a channel of the FET transistor, fabrication of second semiconducting portions (122, 124, 126) that will be used to form source and drain regions, such that the first semiconducting portion is located between first ends of the second semiconducting portions and such that second ends of the second semiconducting portions opposite the first ends, are in contact with bearing surfaces, and comprising at least one semiconducting material for which the crystalline structure or the atomic organisation, can be modified when a heat treatment is applied to it; heat treatment generating a modification to the crystalline structure of the semiconducting material of the second semiconducting portions and creating a strain (128) in the first semiconducting portion.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 16, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay Reboh, Remi Coquand
  • Patent number: 10262999
    Abstract: An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Martin M. Frank, Pranita Kerber, Vijay Narayanan
  • Patent number: 10262900
    Abstract: A method for co-integrating wimpy and nominal devices includes growing source/drain regions on semiconductor material adjacent to a gate structure to form device structures with a non-electrically active material. Selected device structures are masked with a block mask. Unmasked device structures are selectively annealed to increase electrical activity of the non-electrically active material to adjust a threshold voltage between the selected device structures and the unmasked device structures.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Nicolas J. Loubet, Xin Miao, Alexander Reznicek
  • Patent number: 10204920
    Abstract: A semiconductor device including a standard cell for implementing a logic element includes a first active region and a second active region extending in a second direction on a substrate and spaced apart from each other in a first direction perpendicular to the second direction, gate electrodes intersecting the first active region and the second active region, and source regions and drain regions formed on the first and second active regions at both sides of each of the gate electrodes. A boundary of the standard cell has a polygonal shape, excluding a quadrilateral shape, when viewed in a plan view. As a result, an area of the standard cell may be reduced to reduce a size of the semiconductor device.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: JinTae Kim, Jaewan Choi
  • Patent number: 10191341
    Abstract: A display device includes a plurality of pixels arranged in a matrix. Each of the plurality of pixels includes a transistor and a pixel electrode arranged above the transistor through a first protective film and a second protective film. Among the plurality of pixels, the pixel electrodes of two pixels adjacent in a column direction are connected to corresponding source electrodes of the two pixels through second and third contact holes respectively. The second and third contact holes are formed in the first protective film within a first contact hole that is formed in the second protective film.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: January 29, 2019
    Assignee: Panasonic Liquid Crystal Display Co., Ltd.
    Inventor: Kikuo Ono
  • Patent number: 10153270
    Abstract: An ESD protection device includes a substrate having an active fin extending in a first direction, a plurality of gate structures extending in a second direction at a given angle with respect to the first direction and partially covering the active fin, an epitaxial layer in a recess on a portion of the active fin between the gate structures, an impurity region under the epitaxial layer, and a contact plug contacting the epitaxial layer. A central portion of the impurity region is thicker than an edge portion of the impurity region, in the first direction. The contact plug lies over the central portion of the impurity region.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: December 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Lim Kang, Hyun-Jo Kim, Jong-Mil Youn, Soo-Hun Hong
  • Patent number: 10134483
    Abstract: A large-scale integrated circuit with built-in self-repair (BISR) circuitry for enabling redundancy repair for embedded memories in each of a plurality of processor cores with embedded built-in self-test (BIST) circuitry. The BISR circuitry receives and decodes BIST data from the embedded memories into fail signature data in a physical-aware form on which repair analysis can be performed. The fail signature data is reformatted into a unified repair format, such that a fuse encoder circuit can be used to encode fuse patterns in that unified repair format for a repair entity for each of the embedded memories. The fuse patterns are reconfigured into the appropriate order for storing in shadow fuse registers associated with the specific embedded memories.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: November 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Devanathan Varadarajan, Sumant Dinkar Kale
  • Patent number: 10128351
    Abstract: Semiconductor devices and methods of manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate; forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming a shielding spacer on a sidewall of the second shielding layer; forming the other of the source and drain regions with the second shielding layer and the shielding spacer as a mask; removing at least a portion of the shielding spacer; and forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of the second shielding layer or a possible remaining portion of the shielding spacer.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: November 13, 2018
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huilong Zhu, Qingqing Liang, Huicai Zhong
  • Patent number: 10032943
    Abstract: A semiconductor structure includes a thin-film device layer, an optoelectronic device disposed in the thin-film device layer, and a surrogate substrate permanently attached to the thin film device layer. The surrogate substrate is optically transparent and has a thermal conductivity of at least 300 W/m-K. The optoelectronic device excitable by visible light transmitted through the surrogate substrate. A method of fabricating the semiconductor structure includes fabricating the optoelectronic device in a device layer thin-film of SiC on a silicon wafer of a first diameter, transferring the device layer thin-film of SiC from the silicon wafer, and permanently bonding the device layer thin-film to a SiC surrogate substrate of a second diameter.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, John U. Knickerbocker, Steven Lorenz Wright, Cornelia Tsang Yang
  • Patent number: 10032777
    Abstract: An array of dynamic random access memory cells includes a first set of memory cell pairs in a first row, a second set of memory cells in a second row, and a first set of bit line contacts in the first row. The second set of memory cell pairs are disposed adjacent to the first set of memory cell pairs, and each two of the memory cell pairs in the second row include a common S/D region. Each of the first set of bit line contacts is electrically coupled to each of the common S/D regions of the memory cell pairs in the second row respectively.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: July 24, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Wen Chen, Chi-Chang Shuai, Hung-Chan Lin, Ting-Hao Chang, Hsien-Hung Tsai
  • Patent number: 10002871
    Abstract: An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: June 19, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Martin M. Frank, Pranita Kerber, Vijay Narayanan
  • Patent number: 9873942
    Abstract: Methods of vapor deposition include multiple vapor sources. A vapor deposition method includes delivering pulses of a vapor containing a first source chemical to a reaction space from at least two separate source vessels simultaneously. The pulses can contain a substantially consistent concentration of the first source chemical. The method can include purging the reaction space of an excess of the first source chemical after the delivering, and delivering pulses of a vapor containing a second source chemical to the reaction space from at least two separate source vessels simultaneously after the purging.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: January 23, 2018
    Assignee: ASM IP Holding B.V.
    Inventors: Christophe Pomarede, Eric Shero, Mohith Verghese, Jan Willem Maes, Chang-Gong Wang
  • Patent number: 9859279
    Abstract: An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Martin M. Frank, Pranita Kerber, Vijay Narayanan
  • Patent number: 9806169
    Abstract: Semiconductor devices and methods for manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask; removing a portion of the second shielding layer which is next to the other of the source and drain regions; forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer; and forming a stressed interlayer dielectric layer on the substrate.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: October 31, 2017
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADAMY OF SCIENCES
    Inventors: Huilong Zhu, Qingqing Liang, Huicai Zhong
  • Patent number: 9799671
    Abstract: Dielectric degradation and electrical shorts due to fluorine radical generation from metallic electrically conductive lines in a three-dimensional memory device can be reduced by forming composite electrically conductive layers and/or using of a metal oxide material for an insulating spacer for backside contact trenches. Each composite electrically conductive layer includes a doped semiconductor material portion in proximity to memory stack structures and a metallic material portion in proximity to a backside contact trench. Fluorine generated from the metallic material layers can escape readily through the backside contact trench. The semiconductor material portions can reduce mechanical stress.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: October 24, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jayavel Pachamuthu, Matthias Baenninger, Stephen Shi, Johann Alsmeier
  • Patent number: 9728464
    Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: August 8, 2017
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Daniel B. Aubertine, Anand S. Murthy, Gaurav Thareja, Tahir Ghani
  • Patent number: 9698269
    Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: July 4, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Wei Hua Tong, Tien-Ying Luo, Yan Ping Shen, Feng Zhou, Jun Lian, Haoran Shi, Min-hwa Chi, Jin Ping Liu, Haiting Wang, Seung Kim
  • Patent number: 9590739
    Abstract: Terahertz external modulator based on high electron mobility transistors belongs to the field of electromagnetic functional devices technology. This invention includes the semiconductor substrate (1), the epitaxial layer (2), and the modulation-unit array (4). The epitaxial layer (2) is set on the semiconductor substrate (1). The modulation-unit (4), the positive electrode (3), and the negative electrode (5) are all set on the epitaxial layer (2). The modulation-unit array includes at least three units with each of them is composed of high electron mobility transistors and metamaterial-structure. The gates of transistors connect to the negative electrode (5), and the sources and drains connect to the positive electrode (3). This invention is used for manipulation of spatial transmission terahertz waves. It could be operated at room temperatures, normal pressures, and non-vacuum condition. It does not need to load on the waveguide, thus is easy to package and use.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: March 7, 2017
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Yaxin Zhang, Shen Qiao, Shixiong Liang, Ziqiang Yang, Zhihong Feng
  • Patent number: 9583483
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kun-Mu Li, Tsz-Mei Kwok, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
  • Patent number: 9547740
    Abstract: An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an alternating fashion. As a result of this sequential sidewall spacer process, the variation in the widths of the lines across the plurality of lines, and the spacing between adjacent lines, depends on the variations in the dimensions of the sidewall spacers. These variations are independent of, and can be controlled over a distribution much less than, the variation in the size of the intermediate mask element caused by the patterning process.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: January 17, 2017
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Xi-Wei Lin
  • Patent number: 9525146
    Abstract: The present invention relates to organic semiconductor compositions and organic semiconductor layers and devices comprising such organic semiconductor compositions. The invention is also concerned with methods of preparing such organic semiconductor compositions and layers and uses thereof. The invention has application particularly in the field of displays such as organic field effect transistors (OFETS), integrated circuits, organic light emitting diodes (OLEDS), photodetectors, organic photovoltaic (OPV) cells, sensors, lasers, memory elements and logic circuits.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: December 20, 2016
    Assignee: Smartkem Limited
    Inventor: Russell Jon Griffiths
  • Patent number: 9514260
    Abstract: A layout design system includes a storage unit storing first and second standard cell designs, and a displacement module that arranges the first and second standard cell designs to generate an intermediate design in accordance with the chip design requirement. A first area for the first standard cell design and a second area for the second standard cell design are separated in the intermediate design by a filler design having no active area. Extended active areas are formed in the filler design in relation to the first standard cell design and second standard cell design.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: December 6, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jin-Tae Kim
  • Patent number: 9502655
    Abstract: A display device includes: a substrate; a pixel defining layer defining a pixel region on the substrate; a first electrode on the pixel region; a light emitting layer on the first electrode; a second electrode on the light emitting layer; a thin film encapsulation layer on the second electrode; a metal pattern on the thin film encapsulation layer and overlapping the pixel defining layer; and a multi-layer thin film layer on the metal pattern and the thin film encapsulation layer.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: November 22, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Soo Youn Kim, Hyun Ho Kim, Seung Hun Kim, Sang Hwan Cho
  • Patent number: 9472466
    Abstract: A semiconductor device according to example embodiments may include a substrate having an NMOS area and a PMOS area, isolation regions and well regions formed in the substrate, gate patterns formed on the substrate between the isolation regions, source/drain regions formed in the substrate between the gate patterns and the isolation regions, source/drain silicide regions formed in the source/drain regions, a tensile stress layer formed on the NMOS area, and a compressive stress layer formed on the PMOS area, wherein the tensile stress layer and compressive stress layer may overlap at a boundary region of the NMOS area and the PMOS area. The semiconductor devices according to example embodiments and methods of manufacturing the same may increase the stress effect on the active region while reducing or preventing surface damage to the active region.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: October 18, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ki-chul Kim
  • Patent number: 9449880
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of first spacers over a substrate. A second spacer of a plurality of second spacers is deposited on sidewalls of each first spacer. In some embodiments, a spacing between adjacent first spacers is configured such that second spacers formed on sidewalls of the adjacent first spacers physically merge to form a merged second spacer. A second spacer cut process may be performed to selectively remove at least one second spacer. In some embodiments, a third spacer of a plurality of third spacers is formed on sidewalls of each second spacer. A third spacer cut process may be performed to selectively remove at least one third spacer. A first etch process is performed on the substrate to form fin regions. The plurality of third spacers mask portions of the substrate during the first etch process.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: September 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Yuan Tseng, Chi-Cheng Hung, Chun-Kuang Chen, Chih-Ming Lai, Huan-Just Lin, Ru-Gun Liu, Tsai-Sheng Gau, Wei-Liang Lin
  • Patent number: 9437546
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: September 6, 2016
    Assignee: Intel Corporation
    Inventors: Bernhard Sell, Oleg Golonzka
  • Patent number: 9437476
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a pattern portion and a flat portion on a substrate, the pattern portion including plural patterns, and the flat portion having a flat surface at a position lower than upper surfaces of the patterns. The method further includes transferring a first film on the substrate to continuously form the first film on the upper surfaces of the patterns and on the flat surface of the flat portion and to form a first air gap between the patterns.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: September 6, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keisuke Nakazawa, Ichiro Mizushima, Shinichi Nakao
  • Patent number: 9391065
    Abstract: Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: July 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Robert J. Gauthier, Jr., Tom C. Lee, You Li, Rahul Mishra, Souvick Mitra, Andreas Scholze
  • Patent number: 9373718
    Abstract: An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in an inverted -symbol shape, wherein the two inclined sidewalls of the first groove are interconnected with the second groove respectively, and the first etching process is substantially different from the second etching process.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: June 21, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Jhen-Cyuan Li, Shui-Yen Lu, Man-Ling Lu, Yu-Cheng Tung, Chung-Fu Chang
  • Patent number: 9362382
    Abstract: A method for forming a semiconductor device, includes steps of: providing a substrate; forming a first seal layer over the substrate; forming a second seal layer atop the first seal layer; forming a patterned photoresist layer on the second seal layer; implanting a dopant into the substrate by using the patterned photoresist layer as a mask; executing a first removing process to remove the patterned photoresist layer, wherein the first seal layer has a higher etch rate than that of the second seal layer in the first removing process; and removing the second seal layer after removing the patterned photoresist layer.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: June 7, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yu-Hsiang Hung, Yen-Liang Wu, Ssu-I Fu, Chih-Kai Hsu, Jyh-Shyang Jenq
  • Patent number: 9343374
    Abstract: Forming a poly-Si device including pulling back spacers prior to silicidation and the resulting device are provided. Embodiments include forming two poly-Si gate stacks on an upper surface of a substrate; forming a hardmask over the second poly-Si gate stack; forming eSiGe with a silicon cap at opposite sides of the first poly-Si gate stack; removing the hardmask; forming nitride spacers at opposite sides of each of the poly-Si gate stacks; forming deep source/drain regions at opposite sides of the second poly-Si gate stack; forming a wet gap fill layer around each of the poly-Si gate stacks to a thickness less than the poly-Si gate stack height from the substrate's upper surface; removing an upper portion of the nitride spacers down to the height of the wet gap fill layer followed by removing the wet gap fill layer; and performing silicidation of the deep source/drain regions and the silicon cap.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: May 17, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jan Hoentschel, Peter Javorka, Stefan Flachowsky, Ralf Richter
  • Patent number: 9299803
    Abstract: Provided is a method of forming a semiconductor device. The method includes providing a substrate having n-type doped source/drain features; depositing a flowable dielectric material layer over the substrate; and performing a wet annealing process to the flowable dielectric material layer. The wet annealing process includes a first portion performed at a temperature below 600 degrees Celsius (° C.) and a second portion performed at temperatures above 850° C. wherein the second portion is performed for a shorter duration than the first portion. In embodiments, the second portion has a spike temperature ramp profile with a peak temperature ranging from about 900° C. to about 1,050° C. and a spike duration ranging from about 0.7 seconds to about 10 seconds. The wet annealing process satisfies thermal budget for converting the flowable dielectric material layer to a dense oxide layer while maintaining tensile strain in an n-channel between the doped source/drain features.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: March 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung Hsiung Tsai, Wei-Yuan Lu
  • Patent number: 9252272
    Abstract: There is set forth herein in one embodiment a FinFET semiconductor device having a fin extending from a bulk silicon substrate, wherein there is formed wrapped around a portion of the fin a gate, and wherein proximate a channel area of the fin aligned to the gate there is formed a local buried oxide region aligned to the gate. In one embodiment, the local buried oxide region is formed below a channel area of the fin.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: February 2, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yanxiang Liu, Min-hwa Chi
  • Patent number: 9252243
    Abstract: In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: February 2, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • Patent number: 9184294
    Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: November 10, 2015
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Anand S. Murthy, Glenn A. Glass, Daniel B. Aubertine, Tahir Ghani, Jack T. Kavalieros, Roza Kotlyar
  • Patent number: 9117704
    Abstract: A semiconductor device of the present invention includes an n-channel first thin film transistor and a p-channel second thin film transistor on one and the same substrate. The first thin film transistor has a first semiconductor layer (27), and the second thin film transistor has a second semiconductor layer (22). The first semiconductor layer (27) and the second semiconductor layer (22) are formed from one and the same film. Each of the first semiconductor layer (27) and the second semiconductor layer (22) has a slope portion (27e, 22e) positioned in the periphery and a main portion (27m, 22m) which is a portion excluding the slope portion. A p-type impurity is introduced into only a part of the slope portion (27e) of the first semiconductor layer with higher density than the main portion (27m) of the first semiconductor layer, the main portion (22m) of the second semiconductor layer, and the slope portion (22e) of the second semiconductor layer.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: August 25, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Naoki Makita, Hiroki Mori, Masaki Saitoh
  • Patent number: 9117766
    Abstract: Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: August 25, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Sanket Sant, Gurtej Sandhu, Neal R. Rueger
  • Patent number: 9105617
    Abstract: One method disclosed herein includes, among other things, forming a line-end protection layer in an opening on an entirety of each opposing, spaced-apart first and second end face surfaces of first and second spaced-apart gate electrode structures, respectively, and forming a sidewall spacer adjacent opposing sidewall surfaces of each of the gate electrode structures but not adjacent the opposing first and second end face surfaces having the line-end protection layer positioned thereon.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: August 11, 2015
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ruilong Xie, Shom Ponoth, Juntao Li
  • Patent number: 9064729
    Abstract: A method is provided for fabricating a junction-less transistor. The method includes providing a semiconductor substrate having a dielectric layer; and forming a semiconductor layer including a first heavily doped layer formed on the dielectric layer, a lightly doped layer formed on the first heavily doped layer and a second heavily doped layer formed on the lightly doped layer. The method also includes etching the semiconductor layer and the dielectric layer to form trenches to expose side surfaces of a portion of the semiconductor layer and a portion of the dielectric layer; and removing the portion of the dielectric layer between the adjacent trenches to form a chamber. Further, the method includes forming a gate structure around the portion of the semiconductor layer between the adjacent trenches; and forming a source region and a drain region in the semiconductor layer at both sides of the gate structure.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: June 23, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Jinhua Liu
  • Patent number: 9048257
    Abstract: A backplane includes: a substrate, a pixel electrode, which includes a transparent conductive material, on the substrate, a capacitor first electrode formed on the same layer as the pixel electrode, a first protection layer covering the capacitor first electrode and an upper edge of the pixel electrode, a gate electrode of a thin film transistor (TFT) formed on the first protection layer, a capacitor second electrode formed on the same layer as the gate electrode, a first insulating layer that covers the gate electrode and the capacitor second electrode, a semiconductor layer that is formed on the first insulating layer and includes a transparent conductive material, a second insulating layer covering the semiconductor layer, source and drain electrodes of the TFT that are formed on the second insulating layer, and a third insulating layer that covers the source and drain electrodes and exposes the pixel electrode.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: June 2, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong-Han Jeong, Chaun-Gi Choi
  • Patent number: 9034741
    Abstract: A semiconductor device and method for manufacturing the same, wherein the method includes fabrication of field effect transistors (FET). The method includes growing a doped epitaxial halo region in a plurality of sigma-shaped source and drain recesses within a semiconductor substrate. An epitaxial stressor material is grown within the sigma-shaped source and drain recesses surrounded by the doped epitaxial halo forming source and drain regions with controlled current depletion towards the channel region to improve device performance. Selective growth of epitaxial regions allows for control of dopants profile and hence tailored and enhanced carrier mobility within the device.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: May 19, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas N. Adam, Keith E. Fogel, Judson R. Holt, Balasubramanian Pranatharthiharan, Alexander Reznicek
  • Patent number: 9029836
    Abstract: In a method for fabricating a graphene structure, there is formed on a fabrication substrate a pattern of a plurality of distinct graphene catalyst materials. In one graphene synthesis step, different numbers of graphene layers are formed on the catalyst materials in the formed pattern. In a method for fabricating a graphene transistor, on a fabrication substrate at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor channel and at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor source, and at a substrate region specified for synthesizing a graphene transistor drain. Then in one graphene synthesis step, at least one layer of graphene is formed at the substrate region for the graphene transistor channel, and at the regions for the transistor source and drain there are formed a plurality of layers of graphene.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: May 12, 2015
    Assignee: President and Fellows of Harvard College
    Inventors: Jung-Ung Park, SungWoo Nam, Charles M. Lieber
  • Patent number: 9029868
    Abstract: A semiconductor apparatus includes a substrate; a buffer layer formed on the substrate; a first semiconductor layer formed on the buffer layer; and a second semiconductor layer formed on the first semiconductor layer. Further, the buffer layer is formed of AlGaN and doped with Fe, the buffer layer includes a plurality of layers having different Al component ratios from each other, and the Al component ratio of a first layer is greater than the Al component ratio of a second layer and a Fe concentration of the first layer is less than the Fe concentration of the second layer, the first and second layers being included in the plurality of layers, and the first layer being formed on a substrate side of the second layer.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: May 12, 2015
    Assignee: Fujitsu Limited
    Inventors: Junji Kotani, Tetsuro Ishiguro, Atsushi Yamada, Norikazu Nakamura
  • Patent number: 9018051
    Abstract: A strain enhanced transistor is provided having a strain inducing layer overlying a gate electrode. The gate electrode has sloped sidewalls over the channel region of the transistor.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics, Inc.
    Inventor: Barry Dove