Abstract: A method of efficiently testing optical chips while still on the wafer is presented. One or more gutters for each chip on the wafer is provided, and either (1) a test signal is applied to the gutter to generate a response from the chip; or (2) a test signal is applied to the chip to generate a response from the gutter, where the gutter is in optical communication with the chip, and can reflect light incident or outgoing light at substantially a ninety degree angle.

Abstract: A method for determining critical dimension variation includes providing a wafer having a grating structure comprising a plurality of lines; illuminating at least a portion of the lines with a light source; measuring light reflected from the illuminated portion of the lines to generate a reflection profile; and determining a critical dimension variation measurement of the lines based on the reflection profile. A metrology tool adapted to receive a wafer having a grating structure comprising a plurality of lines includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the lines. The detector is adapted to measure light reflected from the illuminated portion of the lines to generate a reflection profile. The data processing unit is adapted to determine a critical dimension variation measurement of the lines based on the reflection profile.

Abstract: A confocal three dimensional inspection system, and process for use thereof, allows for rapid inspecting of bumps and other three dimensional (3D) features on wafers, other semiconductor substrates and other large format micro topographies. The sensor eliminates out of focus light using a confocal principal to create a narrow depth response in the micron range.

Abstract: A system and method are provided for collecting, storing, and displaying a plurality of different types of process data, including accumulated and differential particle counts, from remote locations without requiring manual intervention. The system includes a plurality of particle measuring instruments disposed at respective locations distributed about a facility in order to collect particle data. The system also includes a process data collection device for providing process data other than particle data, such as temperature, pressure or humidity level. The system is interconnected with the plurality of particle measuring instruments and the process data collection device by means of a computer network. As such, the particle data and process data can be provided to a computer network for collection and storage. Thereafter, the particle data and the process data can be remotely displayed at a graphic user interface.

Abstract: A correlation between develop inspect (DI) and final inspect (FI) profile parameters are established empirically with test wafers. During production, a wafer is measured at DI phase to obtain DI profile parameters and FI phase profile parameters are predicted according to the DI profile parameters and the established correlation. Each wafer is subsequently measured at FI phase to obtain actual FI profile parameters and the correlation is updated with actual DI and FI profile parameters.

Abstract: The invention relates to a device comprising a process chamber which is arranged in a reaction housing and which can be heated especially by supplying heat to a substrate holder, comprising a gas inlet for the admission of gaseous starting material, whereby the decomposition products thereof are deposited on a substrate maintained by a substrate holder to form a layer, also comprising at least one sensor acting upon the inside of the process chamber for determining layer properties further comprising an electronic control unit for controlling the heating of the process chamber, mass controllers for controlling the flow of the starting materials and a pump for controlling the pressure of the process chamber, characterized in that the electronic control unit forms modified process parameters from deviation values obtained upon growth of the calibrating layer with the aid of stored calibrating parameters, thereby controlling the heating of the process chamber, the flow controllers and the pump upon growth of the

Abstract: A cost-efficient and reliable method for assessing lateral dopant profiles includes the estimation of a reference profile formed below a gate structure of a transistor device. The overlap capacitance is then determined for at least two different overlaps, created by different spacer widths, and the lateral extension of a dopant profile to be measured, is estimated on the basis of a relationship between overlap capacitance and spacer width for the reference dopant profile.

Abstract: A method of making a monitoring pattern to measure a depth and profile of a shallow trench isolation is disclosed. An example method of making a monitoring pattern of a shallow trench isolation profile forms a first pattern on a substrate to monitor a depth of a first shallow trench isolation. In the example method, the first pattern includes a plurality of unequally spaced active regions on the substrate. The example method also forms a second pattern on the substrate to measure electrical effects associated with a depth and a profile of a second shallow trench isolation. In the example method, the second pattern includes a plurality of equally spaced active regions on the substrate and a plurality of contact regions that electrically connect the equally spaced active regions.

Abstract: A system for monitoring a fabrication process is provided. The system includes one or more light sources, each light source directing light to one or more gratings on a wafer. Light reflected from the gratings is collected by a measuring system that processes the collected light. The collected light is indicative of distortion due to stress at respective portions of the wafer. The measuring system provides distortion/stress related data to a processor that determines the acceptability of the distortion of the respective portions of the wafer. The collected light may be analyzed by scatterometry systems to produce scatterometry signatures associated with distortion and to produce feed-forward control information that can be employed to control semiconductor fabrication processes.

Abstract: The present invention includes a method and system for identifying an underlying structure that achieves improved planarization characteristics of layers while minimizing introduction of random and/or systematic noise to the reflected metrology signal.

Abstract: Heights of a sample are calibrated by setting a calibrating substrate on a stage and then irradiating a charged particle beam onto standard marks provided on at least two kinds of surfaces having different substrate heights. Secondary charged particles produced from said irradiated standard marks on the substrate are and detected and a surface height of the irradiated portion of the substrate measured. The difference in height between the standard marks is set to be in a range containing an extent, over the entire sample, to which the height of the sample varies due to warping.

Abstract: Methods and computer program products are provided for analyzing a crystalline structure, such as a wafer or an epitaxial layer in more detail, including the portion of the crystalline structure proximate the edge. The methods and computer program products of one aspect determine the average thickness and the normalized profile of a crystalline structure with enhanced detail. Additionally, the method and computer program product of another aspect represent the profile proximate the edge of the crystalline structure with a pair of lines that are selected to permit the profile of the crystalline structure proximate the edge of the crystalline structure to be characterized in more detail. Further, the method of yet another aspect permits the average edge profile for a plurality of crystalline structure to be defined.

Abstract: A fast method simulates photolithography using conventional image processing techniques. Convolution simulates for blurring; erosion and dilation correct for edge diffraction. In one technique, the source image of the photomask is deconvolved to sharpen it and then dilated to remove edge diffraction. The image is eroded, and then convolved according to the resolution of the stepper at the photomask plane. This aerial image can be further eroded to match the effects of resist and developing. Optional thresholding is done to produce a simulated processed wafer image. In a fast technique, the deconvolution step is eliminated. Dilation and erosion are combined into a single erosion. Where a phase shift mask is involved, a complex convolution is used. Source data can come from the photomask electronic design or from a visual image of the actual photomask. Optimizations include: special microprocessor instructions, floating point pixel values, separable convolution and annular illumination simulation.

Abstract: A method for measuring overlay in semiconductor wafers includes obtaining diffraction based and imaging based measurements of the same target. The two separate measurements are then combined in a way that is consistent to both measurements to obtain an overlay measurement that has high precision and large range.

Abstract: A photolithography step is carried out for exposing/etching a resist film in an etching step. Thereafter a superposition inspection step employing a superposed layer superposition mark and a resist film superposition mark is carried out with a superposition inspection apparatus. In this step, an applied mask confirmation step is simultaneously carried out with the superposition inspection apparatus. Thus, it is possible to provide a method of fabricating a semiconductor device including a superposition inspection step, capable of efficiently confirming an applied mask and improving the fabrication yield for the semiconductor device.

Abstract: A CMOS-compatible FET has a reduced electron affinity polycrystalline or microcrystalline SiC gate that is electrically isolated (floating) or interconnected. The SiC material composition is selected to establish the barrier energy between the SiC gate and a gate insulator. In a memory application, such as a flash EEPROM, the SiC composition is selected to establish a lower barrier energy to reduce write and erase voltages and times or accommodate the particular data charge retention time needed for the particular application. In a light detector or imaging application, the SiC composition is selected to provide sensitivity to the desired wavelength of light. Unlike conventional photodetectors, light is absorbed in the floating gate, thereby ejecting previously stored electrons therefrom. Also unlike conventional photodetectors, the light detector according to the present invention is actually more sensitive to lower energy photons as the semiconductor bandgap is increased.

Abstract: Provided are methods and systems for controlling the concentration of a component in a composition, and semiconductor processing methods and systems. One exemplary method of controlling the concentration of a component in a composition involves: providing a composition which has a liquid portion, wherein the liquid portion contains a component to be monitored; performing an absorption spectroscopy measurement on a sample of the composition; and controlling the concentration of the component in the composition based on the absorption spectroscopy measurement using a feedback control loop. The invention allows for controlling the concentration of a component in a composition, for example, a corrosion inhibitor in a chemical planarization (CMP) chemical, as well as in pre- and post-CMP storage/treatment chemicals, and can provide real time, accurate process control in a simple and robust manner.

Abstract: Upon formation of semiconductor micro patterns, an interlayer alignment error occurs due to asymmetry of each alignment mark. Prior to alignment of a mask with a wafer, the asymmetry of each alignment mark is measured according to the principle of a scatterometry, and the alignment is performed in consideration of the result of measurement to execute exposure. Thus, high-accuracy alignment can be carried out without sacrificing throughput, and the performance of a semiconductor device is improved. Further, manufacturing yields can be enhanced and a reduction in cost can be realized.

Abstract: The present invention describes a structure for and a method of forming a first set and a second set of features in a substrate; covering the first and second set of features with a material; forming a third set of features in the material and removing the material to expose the first set of features, leaving the second set of features embedded below the material; measuring post-etch overlay between the first set and the third set of features; and measuring post-develop overlay between the second set and the third set of features.

Abstract: A semiconductor substrate has a peculiar crystal defect. Crystal defects in a fixed area of a substrate can be treated as data acquired by coding the distribution of the crystal defects. The coded data is utilized for certificate data of an IC card by identifying a semiconductor substrate itself.

Abstract: A method and apparatus for determining defects in a circuit pattern. An image including a circuit pattern is acquired. An outline of the circuit pattern is extracted and a contour image is generated. A shape of a contour in the contour image is evaluated to determine whether a defect exists.

Abstract: A thermopile-based detector for monitoring and/or controlling semiconductor processes, and a method of monitoring and/or controlling semiconductor processes using thermopile-based sensing of conditions in and/or affecting such processes.

Abstract: Systems and methods are described for translating detected wafer defect coordinates to reticle coordinates using CAD data. A wafer inspection image is provided and coordinates of potential defects in the wafer are determined. Then the wafer inspection image is converted into a predetermined image format. CAD data for the device under test is then used to produce a second image, also in the predetermined image format. The CAD-derived image and the wafer-derived image are then aligned, and the coordinates of potential defects in the wafer are converted into CAD coordinates. The CAD coordinates are then used to navigate through the reticle for the wafer in order to locate reticle defects corresponding to the detected wafer defects.

Abstract: The object of the invention is to provide a method of monitoring the chalcogenation process and, in doing so, to enable this process to be controlled and to determine its terminal point.

Abstract: Methods and systems for monitoring semiconductor fabrication processes are provided. A system may include a stage configured to support a specimen and coupled to a measurement device. The measurement device may include an illumination system and a detection system. The illumination system and the detection system may be configured such that the system may be configured to determine multiple properties of the specimen. For example, the system may be configured to determine multiple properties of a specimen including, but not limited to, a presence of macro defects and overlay of a specimen. In this manner, a measurement device may perform multiple optical and/or non-optical metrology and/or inspection techniques.

Abstract: A thermopile-based detector for monitoring and/or controlling semiconductor processes, and a method of monitoring and/or controlling semiconductor processes using thermopile-based sensing of conditions in and/or affecting such processes.

Abstract: A method and a device for measuring in real time the thickness of an integrated circuit layer with the layer to be measured being deposited on an underlying layer. During an engraving operation, the advance of the engraving front generated during the engraving operation is monitored by plotting the optical emission spectrum of the product of the engraving reaction in real time on a spectral component of the underlying layer. A time distribution of the optical emission amplitude of the engraving reaction product is established and the transition of the optical emission amplitude on the distribution as the engraving front passes from the layer to be measured to the underlying layer as established. The thickness of the layer to be measured is thus computed on the basis of the distribution and the transition by a correlation with the transition on the distribution.

Abstract: Semiconductor elements composing a semiconductor device are formed on a semiconductor substrate. Wirings composed of copper or an alloy mainly composed of copper are formed in wiring layers through interlayer insulation films to connect the semiconductor elements to each other. When the wirings are formed, a temperature of the wirings is held in a first temperature zone covering 40° C. of a temperature at which a stress migration is most accelerated.

Abstract: In order to improve a method of analyzing Si—Ge alloys, with which a Raman spectrum of a sample is recorded and Raman frequencies and Raman intensities of the Si—Si modes and the Si—Ge modes of the alloy layer are evaluated, such that any strain and any Ge portion in an alloy layer can be ascertained in a simple and as exact a manner as possible, it is provided for one or more spectrum contributions lying outside the Si—Ge modes and the Si—Si modes to be evaluated as oscillation modes.

Abstract: One embodiment of the present invention is a method of designing underlying structures in a wafer with pads of varying sizes and varying loading factors, and selecting the design of pads that yield a reflected metrology signal closest to the calibration metrology signal and that meet preset standard planarization characteristics. Another embodiment is a method of designing underlying structures with random shapes of varying sizes and varying loading factors. Still another embodiment is the use of periodic structures of varying line-to-space ratios in one or more underlying layers of a wafer, the periodicity of the underlying periodic structure being positioned at an angle relative to the direction of periodicity of the target periodic structure of the wafer.

Abstract: In an alignment or overlay measurement of patterns on a semiconductor wafer an error that occurs during the measurement in one of a predefined number of alignment structures in an exposure field of a corresponding predefined set of exposure fields can be handled by selecting an alignment structure in a substitute exposure field. The latter exposure field need not be part of the predefined set of exposure fields, that is, an inter-field change may be effected. The number of alignment measurements on a wafer remains constant and the quality is increased. Alternatively, when using another alignment structure in the same exposure field—by effecting an intra-field change—the method becomes particularly advantageous when different minimum structure sizes are considered for the substitute targets. Due to the different selectivity in, say, a previous CMP process, such targets might not erode and do not cause an error in a measurement, thus providing an increased alignment or overlay quality.

Abstract: In an exposure method of drawing and exposing a second pattern with a scanner so as to match a first pattern formed on a sample upon exposure with a reduction projection exposure apparatus, a matrix is set on the sample. A distortion correction map representing an offset of a point corresponding to each matrix point on the first pattern from an ideal position is formed. The blocks of the matrix, small for a large offset and large for a small offset, are set when drawing the second pattern while correcting drawing information of the second pattern on the basis of offset information represented by the correction map. The block size of the distortion correction map is not uniformly reduced. A small block size is set for a large distortion, and a large block size is set for a small distortion, thereby reducing the data amount.

Abstract: Radiant energy may be applied to a photochemically susceptible etching or conditioning solution to enable precise control of the removal of material or alteration of the top surface of a wafer during the fabrication of semiconductor integrated circuits. A particular condition may be detected during the course of photoactivated generation of free radicals or molecular activation to control the further generation of said species by controlling the radiant energy exposure of a wafer.

Abstract: A cleaning end point detecting apparatus detects an end point of a cleaning process in which contamination attached to an inner wall of a reaction chamber is removed by introducing a cleaning gas into the chamber to produce a cluster cloud and detached particles. An irradiating unit irradiates a laser beam onto the cluster cloud and the detached particles within the reaction chamber to produce a scattered laser beam. A monitoring unit monitors the scattered laser beam as a two-dimensional image information. A judging unit judges the end point of the cleaning process on the basis of the two-dimensional image information. Preferably, the judging unit judges, as the end point of the cleaning process, a time instant when neither the detached particles nor the cluster cloud are detected on the basis of the two-dimensional image information.

Abstract: A method for forming atomic-scale contacts and atomic-scale gaps between two electrodes is disclosed. The method provides for applying a voltage between two electrodes in a circuit with a resistor. The applied voltage etches metal ions off one electrode and deposits the metal ions onto the second electrode. The metal ions are deposited on the sharpest point of the second electrode, causing the second electrode to grow towards the first electrode until an atomic-scale contact is formed. By increasing the magnitude of the resistor, the etching and deposition process will terminate prior to contact, forming an atomic-scale gap. The atomic-scale contacts and gaps formed according to this method are useful as a variety of nanosensors including chemical sensors, biosensors, hydrogen ion sensors, heavy metal ion sensors, magnetoresistive sensors, and molecular switches.

Abstract: A method of measuring a concentration of a material includes irradiating an infrared light onto a substrate having a layer including a first material and dopants, wherein the infrared light is partially absorbed by and partially transmitted through the substrate including the layer. Intensities of the infrared light absorbed in the first material and the dopants are computed according to light wave numbers by utilizing a difference between intensities of the infrared light before and after transmitting the substrate and layer and by utilizing a difference between intensities of the infrared light absorbed in the substrate and layer and absorbed in only the substrate. Concentrations of the dopants are obtained by utilizing a ratio of light wave number regions corresponding to predetermined intensities of infrared light absorbed in the dopants relative to light wave number regions corresponding to the predetermined intensity of infrared light absorbed in the first material.

Abstract: A method and apparatus for the detection and classification defects in a silicon or semi-conductor structure, in particular using room temperature photoluminescence effects, is described. The method involves directing a high intensity beam of light at a surface of a sample of silicon or semi-conductor structure to be tested producing a photoluminescence image, producing a reflected light image, combining the information in the two images to detect. map and identify and/or characterise micro-defects in the silicon or semi-conductor structure.

Abstract: Methods and systems for monitoring semiconductor fabrication processes are provided. A system may include a stage configured to support a specimen and coupled to a measurement device. The measurement device may include an illumination system and a detection system. The illumination system and the detection system may be configured such that the system may be configured to determine multiple properties of the specimen. For example, the system may be configured to determine multiple properties of a specimen including, but not limited to, a presence of macro and micro defects. In this manner, a measurement device may perform multiple optical and/or non-optical metrology and/or inspection techniques.

Abstract: The invention relates to an inspection system for process equipment for treating substrates, such as, for instance, semiconductor wafers or flat panel displays. The system is provided with a wireless sensor with which the interior of the process device can be inspected. The sensor is provided with a transmitter to transfer a signal, during inspection of the interior of the process device, to a receiver disposed outside the process device. The wireless sensor is arranged on a support having substantially the same dimensions as the substrates to be treated.

Abstract: A multilayer structure which provides for optimization of a configuration of a patterned photoresist is designed. A multilayer structure (20) includes polysilicon (10), a silicon oxide film (11) and an anti-reflective film (12) which are deposited sequentially in the order noted, and a photoresist (13) is provided on the anti-reflective film (12), so that light for exposure is incident on the multilayer structure (20) through the photoresist (13). First, as a step (i), a range of thickness of the silicon oxide film (11) is determined so as to allow an absolute value of a reflection coefficient of the light for exposure at an interface between the anti-reflective film (12) and the photoresist (13) to be equal to or smaller than a first value. Subsequently, as a step (ii), the range of thickness of the silicon oxide film (11) determined in the step (i) is delimited so as to allow an absolute value of a phase of the reflection coefficient to be equal to or larger than a second value.

Abstract: Exposure positions of exposure fields of semiconductor wafers are subsequently corrected individually in order to compensate for processes affecting the locational position of alignment marks and/or oblique measurement structures. Measurement structures are formed preferably in the frame region of product wafers comprising electrical circuits to be formed and their locational positions before and after the effect of the process that has an effect are compared individually for purpose of determining the positional displacement for each relevant exposure field. From this there is determined either directly a “shot”-fine correction value for the individual exposure or at least one nonlinear function for the correction in dependence on the position of the measurement structures on the wafer. The corrections are applied to the exposure fields after alignment to the alignment marks overformed by the process in dependence on their position on the wafer.

Abstract: A top surface of a wafer is provided with an n-type source region, an n-type drain region, and an n-type semiconductor region. Dry etching using a plasma is performed with respect to an interlayer insulating film deposited on the wafer to form openings reaching the respective regions, followed by light etching for removing a damaged layer. In this case, exciting light is supplied intermittently to the n-type semiconductor region. The progression of the removal of the damaged layer and the stage of development of a newly damaged layer are sensed by monitoring the change rate of the intensity of reflected probe light in the presence and absence of the exciting light, resulting in the formation of a semiconductor device having low and equal contact resistance. In-line control using optical evaluation enables the implementation of semiconductor devices with excellent and consistent properties.

Abstract: A system for regulating gate oxide layer formation is provided. The system includes one or more light sources, each light source directing light to one or more gate oxide layers being deposited and/or formed on a wafer. Light reflected from the gate oxide layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the thickness and/or uniformity of the respective gate oxide layers on the wafer. The measuring system provides thickness and/or uniformity related data to a processor that determines the thickness and/or uniformity of the respective gate oxide layers on the wafer. The system also includes a plurality of gate oxide layer formers where each gate oxide former corresponds to a respective portion of the wafer and provides for gate oxide layer formation thereon. The processor selectively controls the gate oxide layer formers to regulate gate oxide layer formation on the respective gate oxide layer formations on the wafer.

Abstract: An exposure apparatus comprising (a) irradiating means for illuminating a mask with laser light from an excimer laser and (b) a projection optical system for projecting a pattern of the mask onto a substrate with the laser light, wherein a characteristic of the projection optical system is measured by use of a harmonic of a predetermined laser, and wherein the laser light from the excimer laser has a wavelength corresponding to that of the harmonic of the predetermined laser.

Abstract: A system and method of for determining multiple uniformity metrics of a semiconductor wafer manufacturing process includes collecting a quantity across each one of a group of semiconductor wafers. The collected quantity data is scaled and a principal component analysis (PCA) is performed on the collected, scaled quantity data to produce a first set of metrics for the first group of semiconductor wafers. The first set of metrics including a first loads matrix and a first scores matrix.

Abstract: A testing structure formed on a photonic integrated circuit including a plurality of first photonic components and having a given functionality corresponding to a given interconnectivity of the first photonic components, the testing structure including: at least one second photonic component being suitable for testing at least one of the first photonic components; and, at least one photonic pathway optically coupling the at least one first photonic component to the at least one second photonic component. The at least one photonic pathway is unique from the given interconnectivity.

Abstract: A method and system in metrology for integrated circuits, for incorporating the effects of small metrology hardware-based and material-based parameter variations into a library of simulated diffraction spectra. In a first embodiment, a method is disclosed for determining metrology hardware specification ranges that correspond to specified CD measurement accuracy. In a second embodiment, a method for modifying a library of simulated diffraction spectra for optimization to the particular parameters of a specific piece of metrology hardware and specific material batches is disclosed.

Abstract: A system for regulating nitrided gate oxide layer formation is provided. The system includes one or more light sources, each light source directing light to one or more nitrided gate oxide layers being deposited and/or formed on a wafer. Light reflected from the nitrided gate oxide layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the nitrogen concentration of the respective nitrided gate oxide layers on the wafer. The measuring system provides nitrogen concentration related data to a processor that determines the nitrogen concentration of the respective nitrided gate oxide layers on the wafer. The system also includes one or more nitrided gate oxide layer formers where a nitride gate oxide former corresponds to a respective portion of the wafer and provides for nitrided gate oxide layer formation thereon.

Abstract: An apparatus for testing a semiconductor die and the method wherein there is provided a package having a cavity therein with a plurality of terminals in the package disposed at the periphery of the cavity. A semiconductor die to be tested and having a plurality of bond pads thereon is disposed in the cavity and an interconnecting layer having electrically conductive paths thereon is also disposed in the cavity, each of the paths having first and second spaced apart regions thereon, the first region of each path being aligned with and contacting a bond pad. An interconnection is provided between the second spaced apart region of each of the paths and one of the plurality of terminals. The second spaced apart region of each of the paths is preferably a bump aligned with and contacting one of the plurality of terminals. A compliant layer is preferably disposed over the interconnecting layer and provides a force causing engagement of at least the first spaced apart regions and the bond pads.

Abstract: The present invention generally provides an apparatus and a method for inspecting a substrate in a processing system. More specifically, a method and apparatus providing embedded substrate monitoring through consolidation of multiple process inspection techniques in semiconductor processing equipment is disclosed. In one aspect, an optical inspection system comprising a light source and an optical receiving device, such as a CCD camera, is used to illuminate and inspect a substrate for various optical signatures. A plurality of optical inspection systems are strategically located in a cluster tool environment in order to collect optical information during processing steps. Taken together, the plurality of optical inspection systems operate as a monitoring system to determine substrate process conditions and routing.