With Measuring Or Testing Patents (Class 438/14)
  • Patent number: 11132791
    Abstract: Devices, systems, and methods obtain a reference image; obtain a test image; globally align the test image to the reference image; select subfields in the test image; align the subfields in the test image with respective areas in the reference image; warp the test image based on the aligning of the subfields; select anchor points in the reference image; select anchor-edge points in the reference image; realign the subfields in the warped test image with respective areas in the reference image based on the anchor points in the reference image and on the anchor-edge points in the reference image; and warp the warped test image based on the realigning of the subfields.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: September 28, 2021
    Assignee: Canon Virginia, Inc.
    Inventors: Xiwu Cao, Nikhil Krishnan, Bradley Scott Denney, Hung Khei Huang
  • Patent number: 11119122
    Abstract: There is provided a method for correcting a relative position between a probe card having a plurality of cantilever-type probes and an object to be inspected having a plurality of electrode pads, including: arranging a first group of cantilever-type probes among the plurality of cantilever-type probes in a first region and a second region; arranging a second group of cantilever-type probes among the plurality of cantilever-type probes in a third region and a fourth region; obtaining needle traces formed on the plurality of electrode pads, which are generated when the first group of cantilever-type probes and the second group of cantilever-type probes that are arranged in the first region, the second region, the third region, and the fourth region, are brought into contact with the plurality of electrode pads; and correcting the relative position between the probe card and the object to be inspected based on the obtained needle traces.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 14, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kunihiro Furuya, Shingo Ishida
  • Patent number: 11114331
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; forming a pad layer adjacent to two sides of trench; forming a dielectric layer to fill the trench; and performing a dry etching process to remove the pad layer and part of the dielectric layer to form a shallow trench isolation (STI). Preferably, the dry etching process comprises a non-plasma etching process.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: September 7, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hao-Hsuan Chang, Hung-Chun Lee, Shu-Ming Yeh, Ting-An Chien, Bin-Siang Tsai
  • Patent number: 11101173
    Abstract: This disclosure relates to a method for using a high volume manufacturing system for processing and measuring workpieces in a semiconductor processing sequence without leaving the system's controlled environment (e.g., sub-atmospheric pressure). The system includes an active interdiction control system to implement corrective processing within the system when a non-conformity is detected. The corrective processing method can include a remedial process sequence to correct the non-conformity or compensate for the non-conformity during subsequent process. The non-conformity may be associated with fabrication measurement data, process parameter data, and/or platform performance data.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: August 24, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Robert Clark, Jeffrey Smith, Kandabara Tapily, Angelique Raley, Qiang Zhao
  • Patent number: 11094556
    Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ya-Wen Yeh, Yu-Tien Shen, Shih-Chun Huang, Po-Chin Chang, Wei-Liang Lin, Yung-Sung Yen, Wei-Hao Wu, Li-Te Lin, Pinyen Lin, Ru-Gun Liu
  • Patent number: 11087954
    Abstract: A wafer inspection system includes a controller in communication with an electron-beam inspection tool. The controller includes circuitry to: acquire, via an optical imaging tool, coordinates of defects on a sample; set a Field of View (FoV) of the electron-beam inspection tool to a first size to locate a subset of the defects; determine a position of each defect of the subset of the defects based on inspection data generated by the electron-beam inspection tool during a scanning of the sample; adjust the coordinates of the defects based on the determined positions of the subset of the defects; and set the FoV of the electron-beam inspection tool to a second size to locate additional defects based on the adjusted coordinates.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: August 10, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Wei Fang, Joe Wang
  • Patent number: 11088037
    Abstract: A semiconductor device includes a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, first and second probe pads electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the substrate and the detecting devices. A method for detecting defects in a semiconductor device includes singulating a die having a substrate, a plurality of detecting devices, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring; probing the first and the second probe pads to determine a connection status of the detecting devices; and recognizing a defect when the connection status of the detecting devices indicates an open circuit.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yang-Che Chen, Wei-Yu Chou, Hong-Seng Shue, Chen-Hua Lin, Huang-Wen Tseng, Victor Chiang Liang, Chwen-Ming Liu
  • Patent number: 11080450
    Abstract: A netlist may include a set of resistance components of an integrated circuit (IC) design, and may specify a length, a width, and a metal layer of each resistance component in the set of resistance components, and physical locations of circuit nodes connected to each resistance component in the set of resistance components. A process description may specify the resistivity and thickness of each metal layer in the IC design. For a resistance component in the set of resistance components, resistivity and thickness of the metal layer of the resistance component may be determined based on the process description, and an inductance component corresponding to the resistance component may be determined based on the length and the width of the resistance component, the resistivity and the thickness of the metal layer of the resistance component, and the physical locations of the circuit nodes connected to the resistance component.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: August 3, 2021
    Assignee: Synopsys, Inc.
    Inventor: Joseph Gregory Rollins
  • Patent number: 11075225
    Abstract: A display device including: a substrate including a display area for displaying an image and a non-display area positioned at a periphery of the display area; a plurality of pixels positioned at the display area; a plurality of data lines connected with the plurality of pixels; and a crack detecting line positioned at the non-display area, wherein the crack detecting line includes: a plurality of unit connectors extending in a first direction, wherein the first direction is parallel to an extending direction of a side of the substrate nearest to the unit connectors; and a plurality of wiring portion units connected to each other through the plurality of unit connectors, wherein the number of wiring portion units is an even number.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: July 27, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hey Jin Shin, Won Kyu Kwak, Seung-Kyu Lee
  • Patent number: 11069674
    Abstract: A semiconductor device includes “n” pairs of pn-junction structures, wherein the i-th pair includes two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected, wherein the pn-junction structure of the i-th type has an i-th junction grading coefficient mi. A first pair of the n pairs of pn-junction structures has a first junction grading coefficient m1 and a second pair of the n pairs of pn-junction structures has a second junction grading coefficient m2. The junction grading coefficients m1, m2 are adjusted to result in generation of a spurious third harmonic signal of the semiconductor device with a signal power level, which is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients m1, m2 are 0.25.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: July 20, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Joost Adriaan Willemen
  • Patent number: 11060895
    Abstract: A gas meter includes a meter body having a meter inlet into which a fluid-to-be-measured is to flow and a meter outlet from which the fluid-to-be-measured is to flow out, and an extended section extending from the meter inlet to an interior of the meter body. The gas meter further includes a flow rate measurement unit inside the meter body, the flow rate measurement unit having a measurement flow passage having a straight tubular shape, a lead-in port and a lead-out port for the fluid-to-be-measured, and a shutoff valve in an internal passage of the extended section. The lead-in port is airtightly connected to the extended section so as to communicate with the internal passage.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: July 13, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masaki Sugiyama, Hiroaki Katase, Naoto Naganuma
  • Patent number: 11054752
    Abstract: An overlay metrology system includes one or more processors coupled to an illumination source to direct illumination to a sample and a detector to capture diffracted orders of radiation from the sample. The system may generate overlay sensitivity calibration parameters based on differential measurements of a calibration target including two overlay target cells on the sample, where first-layer target elements and second-layer target elements of the overlay target cells are distributed with a common pitch along a measurement direction and are misregistered with a selected offset value in opposite directions. The system may further determine overlay measurements based on differential measurements of additional overlay target cells with two wavelengths, where first-layer target elements and second-layer target elements of the additional overlay target cells are distributed with the common pitch and are formed to overlap symmetrically.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: July 6, 2021
    Assignee: KLA Corporation
    Inventors: Eran Amit, Daniel Kandel, Dror Alumot, Amit Shaked, Liran Yerushalmi
  • Patent number: 11036203
    Abstract: A fabrication system for fabricating a three-dimensional object includes processing circuitry. The processing circuitry estimates, according to a fabrication condition and fabrication data, a three-dimensional object to be fabricated according to the fabrication data and corrects the fabrication data according to an estimation result of the three-dimensional object estimated by the processing circuitry.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: June 15, 2021
    Assignee: Ricoh Company, Ltd.
    Inventors: Wataru Sugawara, Hiroshi Maeda, Yoshinobu Takeyama, Tsukasa Matsuoka, Yoichi Ito, Shingo Nagatsuka
  • Patent number: 11036211
    Abstract: Based on at least one manufacturing process characteristics associated with a manufacturing process, a prediction time at which to execute a selected machine learning model selected from multiple trained machine learning models is determined, and at the prediction time, the selected machine learning model is executed. Executing the selected machine learning model predicts a control set point for future values of state variables of the manufacturing process, for controlling the manufacturing process. Based on at least one of the manufacturing process characteristics, a learning time at which to train a machine learning model is determined, and at the learning time, the machine learning model is trained based on historical process data associated with the manufacturing process.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: June 15, 2021
    Assignee: International Business Machines Corporation
    Inventors: Young Min Lee, Edward Pring, Kyong Min Yeo, Nam H Nguyen, Jayant R. Kalagnanam, Christian Makaya, Hui Qi, Dhavalkumar C Patel
  • Patent number: 11010509
    Abstract: Embodiments of the present invention provide a novel method and discretization for animating water waves. The approaches disclosed combine the flexibility of a numerical approach to wave simulation with the stability and visual detail provided by a spectrum-based approach to provide Eulerian methods for simulating large-scale oceans with highly detailed wave features. A graphics processing unit stores a one-dimensional texture referred to as a wave profile buffer that stores pre-computed results at a number of discrete sample points for performing wave height evaluation. The water surface is rendered according to water height values computed using the wave profile, accounting for advection, spatial diffusion, angular diffusion, boundary reflections, and dissipation.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 18, 2021
    Assignee: NVIDIA Corporation
    Inventors: Stefan Jeschke, Matthias Mueller-Fischer, Nuttapong Chentanez, Miles Macklin
  • Patent number: 10997712
    Abstract: Devices, systems, and methods obtain a reference image; obtain a test image; globally align the test image to the reference image; select subfields in the test image; align the subfields in the test image with respective areas in the reference image; warp the test image based on the aligning of the subfields; select anchor points in the reference image; select anchor-edge points in the reference image; realign the subfields in the warped test image with respective areas in the reference image based on the anchor points in the reference image and on the anchor-edge points in the reference image; and warp the warped test image based on the realigning of the subfields.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: May 4, 2021
    Assignee: Canon Virginia, Inc.
    Inventors: Xiwu Cao, Nikhil Krishnan, Bradley Scott Denney, Hung Khei Huang
  • Patent number: 10990023
    Abstract: A method of overlay error measurement includes disposing a reference pattern module over a substrate. The substrate includes first and second overlay measurement patterns in first and second locations. The reference pattern module includes first and second reference patterns. The method includes creating a first overlap of the first reference pattern with the first overlay measurement pattern and a second overlap of the second reference pattern with the second overlay measurement pattern. The method further includes determining a first overlay error between the first reference pattern of the reference pattern module and the first overlay measurement pattern of the substrate and determining a second overlay error between the second reference pattern and the second overlay measurement pattern. The method also includes determining a total overlay error between the first and second overlay measurement patterns of the substrate based on the first and second overlay errors.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Chih Hsieh, Yen-Liang Chen
  • Patent number: 10987909
    Abstract: The present invention provides a method of laminating a film for a dye-sensitized cell. First, a composite film is taken by a robotic arm, in which the composite film includes a release layer, a protective layer and a hot glue layer between the release layer and the protective layer, and the release layer is removed by the robotic arm. Then, the hot glue layer is precisely attached to a substrate by a target positioning step. Next, the protective layer is removed by the robotic arm.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: April 27, 2021
    Assignee: FORMOSA PLASTICS CORPORATION
    Inventors: Ching-Fu Chen, Hao-Wei Chen, Kun-Tai Ho, Wan-Tun Hung, Po-Min Chen, Liang-Kun Huang, Chih-Chou Chang, Yung-Liang Tung, Po-Tsung Hsiao, Ming-De Lu
  • Patent number: 10989747
    Abstract: A device for measuring electrical properties of electrical contacts within an electroplating apparatus has a disc-shaped structure like that of a wafer. Multiple conductive pads are formed to collectively circumscribe an outer periphery of the disc-shaped structure. Adjacently positioned ones of the conductive pads are electrically isolated from each other. The device includes a current source that supplies electric current at a first terminal and sinks electric current at a second terminal. The device includes measurement circuitry, having first and second input terminals, that determines a value of an electrical parameter based on signals present at the first and second input terminals. The device includes switching circuitry for connecting selected ones of the conductive pads to the first and second terminals of the current source and to the first and second input terminals of the measurement circuitry at a given time. The device also includes an onboard power supply.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: April 27, 2021
    Assignee: Lam Research Corporation
    Inventors: Mark E. Emerson, Steven T. Mayer, Lawrence Ossowski
  • Patent number: 10977559
    Abstract: A method and a system are provided for predicting a non-linear relationship between a plurality of parameters in a deep neural network framework. The method comprises receiving, by an application server, a plurality of parameter values associated with the plurality of parameters. The method further comprises selecting, by the application server, an activation function based on a desired output. In an embodiment, the desired output is based on an industry type and an application area of the plurality of parameters. The method further comprises predicting, by the application server, the non-linear relationship between the plurality of parameters by modelling the deep neural network framework based on the selected activation function.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: April 13, 2021
    Assignee: Wipro Limited
    Inventor: Chaitanya Rajendra Zanpure
  • Patent number: 10971347
    Abstract: In order to provide a charged particle beam apparatus capable of stably detecting secondary particles and electromagnetic waves even for a non-conductive sample under high vacuum environment and enabling excellent observation and analysis, the charged particle beam apparatus includes a charged particle gun (12), scanning deflectors (17 and 18) configured to scan a charged particle beam (20) emitted from the charged particle gun (12) onto a sample (21), detectors (40 and 41) configured to detect a scanning control voltage input from an outside into the scanning deflectors, an arithmetic unit (42) configured to calculate, based on the detected scanning control voltage, irradiation pixel coordinates for the charged particle beam; and an irradiation controller (45) configured to control irradiation of the sample with the charged particle beam according to the irradiation pixel coordinates.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: April 6, 2021
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Mitsuhiro Nakamura, Hironori Itabashi, Hirofumi Satou, Tsutomu Saito, Masahiro Sasajima, Natsuki Tsuno, Yohei Nakamura
  • Patent number: 10969220
    Abstract: A method for characterizing a sample, by estimating a plurality of characteristic thicknesses, each being associated with a calibration material, including acquiring an energy spectrum (Sech) transmitted through this sample, located in an X and/or gamma spectral band; for each spectrum of a plurality of calibration spectra (sbase(Lk; Lt)) calculating a likelihood from said calibration spectrum (Sbase(Lk; Lt)), and from the spectrum transmitted through the sample (Sech), each calibration spectrum (Sbase(Lk; Lt)) corresponding to the energy spectrum transmitted through a stack of gauge blocks, each formed of a known thickness of a calibration material; estimating the characteristic thicknesses (L1, L2) associated with the sample according to the criterion of maximum likelihood.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: April 6, 2021
    Assignee: Commissariat a L'Energie Atomique et aux Energies Alternatives
    Inventors: Andrea Brambilla, Alexia Gorecki, Alexandra Potop
  • Patent number: 10970834
    Abstract: A deep learning algorithm is used for defect discovery, such as for semiconductor wafers. A care area is inspected with the wafer inspection tool. The deep learning algorithm is used to identify and classify defects in the care area. This can be repeated for remaining care areas, but similar care areas may be skipped to increase throughput.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: April 6, 2021
    Assignee: KLA-Tencor Corporation
    Inventor: Arpit Yati
  • Patent number: 10950574
    Abstract: A sensor including a system-in-package module, wherein electrical contacts can be contact-connected by way of a mating connector. An associated method and an associated sensor arrangement are also disclosed.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: March 16, 2021
    Inventors: Manfred Goll, Martin Haverkamp, Michael Schulmeister
  • Patent number: 10950508
    Abstract: An ion depth profile control method includes performing reinforcement learning, whereby a similarity between an ion depth profile and a box profile is output as a reward when the similarity is equal to or greater than a set criterion, the ion depth profile being an ion concentration according to a wafer depth in an ion implantation process, and the box profile being a target profile, obtaining at least one process condition of the ion implantation process as a result of the reinforcement learning, and generating a process recipe regarding the at least one process condition.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: March 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seongrak Jeong, Seungmo Kang
  • Patent number: 10948902
    Abstract: Methods and a system include getting, for each variant, input on a probability of occurring and inputs on a variant assigned workload time for a given resource. For each resource of the line, each variant is represented with a graphic object having a first measurable parameter representing the variant probability and a second measurable parameter representing the variant assigned workload time. At least one resource requiring workload balancing on a specific variant is determined by taking into account a combination of the first measurable parameter and the second measurable parameter of the specific variant.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: March 16, 2021
    Assignee: Siemens Industry Software Ltd.
    Inventors: Varda Halaby Senerman, Noga Bar On, Hadar Hillel
  • Patent number: 10916703
    Abstract: A method for pixel patterning and pixel position inspection of an organic light-emitting display device includes: forming, on a substrate using a first mask, a thin film layer of a first color corresponding to a first pixel pattern and a first pixel positioning pattern for inspecting a position of a first pixel; shifting, by a determined pitch, the first mask from a position associated with forming the thin film layer of the first color; aligning the shifted first mask with respect to the substrate; and forming, on the substrate using the shifted first mask, a thin film layer of a second color corresponding to the first pixel pattern and another first pixel positioning pattern for inspecting a position of a second pixel.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: February 9, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sangshin Lee, Dongjin Ha, Mingoo Kang, Ohseob Kwon, Sangmin Yi
  • Patent number: 10908262
    Abstract: Disclosed herein is a scanning ladar transmitter that employs an optical field splitter/inverter to improve the gaze characteristics of the ladar transmitter on desirable portions of a scan area. Also disclosed is the use of scan patterns such as Lissajous scan patterns for a scanning ladar transmitter where a phase drift is induced into the scanning to improve the gaze characteristics of the ladar transmitter on desirable portions of the scan area.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: February 2, 2021
    Assignee: AEYE, INC.
    Inventor: Luis Carlos Dussan
  • Patent number: 10906283
    Abstract: A wafer bonding apparatus including: a lower chuck to which a lower wafer is secured at a peripheral portion of the lower chuck; an upper chuck to which an upper wafer is secured; a bonding initiator for pressuring a central portion of the upper wafer until the central portion of the upper wafer reaches a central portion of the lower wafer, thereby initiating a bonding process of the upper and the lower wafers by deforming the upper wafer; and a bonding controller for controlling a bonding speed between a peripheral portion of the upper wafer and a peripheral portion of the lower wafer such that the upper wafer becomes un-deformed prior to bonding the peripheral portion of the upper wafer and the peripheral portion of the lower wafer.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: February 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Yeong Kim, Jun-Hyung Kim, Hoe-Chul Kim, Hoon-Joo Na, Kwang-Jin Moon
  • Patent number: 10892234
    Abstract: An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed, in a first configuration, to detect a thinning of the substrate via its rear face, and in a second configuration, to detect a DFA attack by fault injection into the integrated circuit.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: January 12, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre Sarafianos, Abderrezak Marzaki
  • Patent number: 10867111
    Abstract: Methods of fabricating semiconductor devices are provided. A method of fabricating a semiconductor device includes selecting a target pattern from a target design layout. The target pattern includes: a target net; a target via that is electrically connected to the target net; and a crossing net that is electrically connected to the target via on a different level from the target net. The method includes analyzing a peripheral pattern that is adjacent the target net. Moreover, the method includes generating a redundant net, and a redundant via that electrically connects the redundant net and the crossing net. Related layout design systems are also provided.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: December 15, 2020
    Inventors: Jae Hwan Kim, Jae Hyun Kang, Byung Chul Shin, Ki Heung Park, Seung Weon Paek
  • Patent number: 10865498
    Abstract: In the present invention, once a polycrystalline silicon rod is grown by the Siemens process, the polycrystalline silicon rod is heat-treated within a temperature range from 750° C. to 900° C. to relieve residual stress in the crystal. According to the experiment of the present inventors, residual stress can be relieved satisfactorily by heat treatment at the above-described low temperature, and in addition, metal contamination cannot be induced and the physical properties of the polycrystalline silicon rod cannot be changed. The above heat treatment can be conducted inside a furnace used to grow the polycrystalline silicon rod, and can also be conducted outside a furnace used to grow the polycrystalline silicon rod. According to the present invention, a polycrystalline silicon rod with residual stress (?) of not more than +20 MPa evaluated by a 2?-sin2? diagram can be obtained.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: December 15, 2020
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Shuichi Miyao, Shigeyoshi Netsu, Tetsuro Okada
  • Patent number: 10860408
    Abstract: A semiconductor die includes a feedback path coupled to the output pin, and an integrity monitor circuit (IMC). The output pin is communicatively coupled to the logic. The IMC is configured to receive a data value. The IMC is further configured to receive measured data value from the output pin routed through the feedback path, compare the data value and the measured data value, and, based on the comparison, determine whether an error has occurred.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: December 8, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Stephen Bowling, Igor Wojewoda, Manivannan Balu
  • Patent number: 10854442
    Abstract: An orientation chamber of a semiconductor substrate processing system is provided. The orientation chamber includes a substrate holder, an orientation detector, and a purging system. The substrate holder is configured to hold a substrate. The orientation detector is configured to detect the orientation of the substrate. The purging system is configured to inject a cleaning gas into the orientation chamber and remove contaminants from the substrate.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Wei-Hua Houng
  • Patent number: 10847429
    Abstract: Provided is a method of detecting photoresist scums and photoresist residues. A carrier is provided. The carrier has a photoresist layer with opening patterns therein. A plasma etching process is performed to the opening patterns of the photoresist layer. Charges are injected to the opening patterns of the photoresist layer. Whether a photoresist scum or residue is present in at least one of the opening patterns is detected.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Chih Wang
  • Patent number: 10846845
    Abstract: Techniques for training an artificial neural network (ANN) using simulated specimen images are described. Simulated specimen images are generated based on data models. The data models describe characteristics of a crystalline material and characteristics of one or more defect types. The data models do not include any image data. Simulated specimen images are input as training data into a training algorithm to generate an artificial neural network (ANN) for identifying defects in crystalline materials. After the ANN is trained, the ANN analyzes captured specimen images to identify defects shown therein.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: November 24, 2020
    Assignee: FEI Company
    Inventors: Ond{hacek over (r)}ej Machek, Tomá{hacek over (s)} Vystav{hacek over (e)}l, Libor Strako{hacek over (s)}, Pavel Potocek
  • Patent number: 10840057
    Abstract: A multiple beam inspection apparatus includes a multi-detector to detect multiple secondary electron beams generated because a target object is irradiated with multiple primary electron beams, and to include plural detection pixels each receiving irradiation of a corresponding one of the multiple secondary electron beams, and having a region which receives irradiation of a corresponding secondary electron beam and is larger than the irradiation spot size of the corresponding secondary electron beam, a shifting mechanism to shift irradiation positions of the multiple secondary electron beams irradiating the plural detection pixels, a determination circuitry to determine whether sensitivity of at least one of the plural detection pixels is degraded, and a setting circuitry to set, when sensitivity of at least one detection pixel is degraded, irradiation position shifting destinations of multiple secondary electron beams, irradiating the plural detection pixels, to be within respective corresponding same detecti
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: November 17, 2020
    Assignee: NuFlare Technology, Inc.
    Inventors: Koichi Ishii, Atsushi Ando
  • Patent number: 10830794
    Abstract: An active wafer prober preheat-precool system comprises a wafer loading unit used to load at least one wafer; a probe card disposed corresponding to the wafer loading unit and used to test the wafer; a carrying mechanism including a central connector corresponding to the wafer loading unit and having a first opening, wherein the probe card is connected with the central connector and faces the wafer loading unit through the first opening; a peripheral connector having a second opening, wherein the central connector is detachably disposed inside the second opening; and a first temperature regulation unit disposed in the peripheral connector; and a control unit electrically connected with the first temperature regulation unit and controlling the first temperature regulation unit to adjust the temperature of the peripheral connector. The present invention also discloses a method for testing wafers.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: November 10, 2020
    Assignee: HERMES-EPITEK CORP.
    Inventor: Wen-Yuan Hsu
  • Patent number: 10818632
    Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: October 27, 2020
    Assignee: Apple Inc.
    Inventors: Vidhya Ramachandran, Jun Zhai, Chonghua Zhong, Kunzhong Hu, Shawn Searles, Joseph T. DiBene, II, Mengzhi Pang
  • Patent number: 10797118
    Abstract: A touch panel, a method for fabricating the same, and a display device are provided. The touch panel includes: a base substrate, a plurality of touch electrode lines, a plurality of cathodes arranged in a matrix, and a plurality of spacers, where each cathode corresponds to at least one of the touch electrode lines, and each spacer includes a first photo spacer and a second photo spacer stacked successively; each touch electrode line includes a first lead part and a second lead part, wherein the first lead part is electrically connected with corresponding one of the cathodes, and the second lead part is configured to electrically connect the first lead part with a corresponding pin on a touch integrated circuit; and the first lead part at least covers the surface of the first photo spacer.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: October 6, 2020
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Shengji Yang, Xue Dong, Xiaochuan Chen, Minghua Xuan, Lei Wang, Pengcheng Lu, Li Xiao, Dongni Liu, Jing Yu
  • Patent number: 10773410
    Abstract: A cut groove having a predetermined depth is formed with a cutting blade along a projected dicing line set on a workpiece. A first preliminary groove is cut in a measurement member and a relational expression with respect to a distance from the preliminary groove bottom and the width of the preliminary groove is determined. An amount of incision into the workpiece is set to be equal to or smaller than a predetermined value from a reference position and the thickness of the workpiece. A second preliminary groove is cut along the projected dicing line, and an image of the second preliminary cut groove is captured. The width of the second preliminary cut groove is measured, and the depth of the second preliminary cut groove is calculated from the width of the second preliminary groove and the relational expression.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: September 15, 2020
    Assignee: DISCO CORPORATION
    Inventors: Atsushi Komatsu, Atsushi Takagi
  • Patent number: 10775780
    Abstract: A causal relationship model building system includes a computer which processes information for building a causal relationship model relating to a manufacturing flow of an object to be controlled. The computer builds the causal relationship model by using monitor data representing a state of each of a plurality of steps of the manufacturing flow, and quality data as a result of an inspection step, and specifies an allowable range of the monitor data so as to satisfy a target value of the quality data, by using the causal relationship model and the target value, from prediction based on a causal relationship between a plurality of pieces of the monitor data. The computer graphically displays information including the causal relationship model and the allowable range of the monitor data on a display screen.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: September 15, 2020
    Assignee: HITACHI, LTD.
    Inventors: Kazuki Horiwaki, Kei Imazawa
  • Patent number: 10748821
    Abstract: A method for measuring pattern placement error (PPE) on a wafer includes receiving a photomask pattern. One or more unit cell patterns are added to the photomask pattern. Each of the unit cell patterns includes at least one reference design pattern and at least one PPE check design pattern. A photomask is fabricated from the photomask pattern with the one or more unit cell patterns added thereto. A wafer is patterned using the fabricated photomask. A microscope image of the patterned wafer is acquired. Pattern placement error is measured as a displacement between the at least one reference design pattern and the at least one PPE check design pattern.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Gyeongseop Kim
  • Patent number: 10748887
    Abstract: The present invention relates to a method for designing a die-based vehicle controller-only semiconductor and a vehicle controller-only semiconductor manufactured by the same, and breaks the conventional semiconductor process to design and manufacture a novel conceptual vehicle controller-only semiconductor, EIP (ECU in Package), through a fusion of a new semiconductor process technique with a controller system technique, thereby obtaining an effect of capable of implementing a high performance/high quality semiconductor in micro-miniature size/ultra-light weight in a short time period.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: August 18, 2020
    Assignee: Hyundai Autron Co., Ltd.
    Inventors: Jae-Ho Chang, Eun-Jung Kim, Jae-Woo Joung
  • Patent number: 10749065
    Abstract: A light-responsive LED (Light Emitting Diode) based on a GaN/CsPbBrxI3-x heterojunction, a preparation method and an application thereof are provided. The light-responsive LED consists of a GaN base layer on a sapphire substrate, an all-inorganic perovskite CsPbBrxI3-x film, an indium electrode and a carbon electrode, forming an In/GaN/CsPbBrxI3-x/C structure, wherein: in the CsPbBrxI3-x film, 0<x<3; the all-inorganic perovskite CsPbBrxI3-x film and the indium electrode are arranged on the GaN base layer in parallel; and the carbon electrode is arranged on the all-inorganic perovskite CsPbBrxI3-x film. The CsPbBrxI3-x film is prepared through a low-temperature anti-solvent method.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: August 18, 2020
    Assignee: HUBEI UNIVERSITY
    Inventors: Hao Wang, Hai Zhou, Guokun Ma, Zehao Song
  • Patent number: 10727071
    Abstract: Provided is a method of analyzing metal contamination of a silicon wafer, the method including etching a surface layer region of the silicon wafer by bringing a surface of a silicon wafer to be analyzed into contact with etching gas that includes hydrogen fluoride gas and nitric acid gas; bringing an exposed surface of the silicon wafer, exposed by the etching, into contact with gas generated from a mixed acid including hydrochloric acid and nitric acid; heating the silicon wafer that has been brought into contact with the gas generated from the mixed acid; bringing the exposed surface, exposed by the etching, of the silicon wafer after the heating into contact with a recovery solution; and analyzing a metal component in the recovery solution that has been brought into contact with the exposed surface, exposed by the etching, of the silicon wafer.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: July 28, 2020
    Assignee: SUMCO CORPORATION
    Inventor: Taisuke Mizuno
  • Patent number: 10697059
    Abstract: Methods and apparatuses for performing atomic layer deposition are provided. A method may include determining an amount of accumulated deposition material currently on an interior region of a deposition chamber interior, wherein the amount of accumulated deposition material changes over the course of processing a batch of substrates; applying the determined amount of accumulated deposition material to a relationship between a number of ALD cycles required to achieve a target deposition thickness, and a variable representing an amount of accumulated deposition material, wherein the applying returns a compensated number of ALD cycles for producing the target deposition thickness given the amount of accumulated deposition material currently on the interior region of the deposition chamber interior; and performing the compensated number of ALD cycles on one or more substrates in the batch.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: June 30, 2020
    Assignee: Lam Research Corporation
    Inventors: Richard Phillips, Chloe Baldasseroni, Nishanth Manjunath
  • Patent number: 10692747
    Abstract: A method for aligning and contacting a first substrate with a second substrate using a plurality of detection units, and a corresponding device for alignment and contact.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: June 23, 2020
    Assignee: EV Group E. Thallner GmbH
    Inventors: Thomas Wagenleitner, Dominik Zinner, Jurgen Markus Suss, Christian Sinn, Jurgen Mallinger
  • Patent number: 10689762
    Abstract: A substrate processing apparatus can suppress particle generation on a substrate, and can reduce a consumption amount of a processing liquid. A substrate processing apparatus 1 includes a processing chamber 30 having a processing space 31 in which a substrate W is processed; a vaporizing tank 60, configured to store the processing liquid therein, having a vaporization space 61 in which the stored processing liquid is allowed to be vaporized; a decompression driving unit 70 configured to decompress the vaporization space 61; and a control unit 18. The control unit 18 vaporizes the processing liquid into the processing gas by decompressing the vaporization space 61 without through the processing space 31, and then, vaporizes the processing liquid into the processing gas by decompressing the vaporization space 61 through the processing space 31, and supplies an inert gas into the vaporization space 61.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: June 23, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akira Murata, Satoshi Kaneko, Kazuki Motomatsu, Kazunori Sakamoto
  • Patent number: 10684929
    Abstract: This disclosure pertains to hardware compute arrays (sometimes called systolic arrays) for applications such as artificial intelligence (AI), machine learning (ML), digital signal processing (DSP), graphics processing units (GPUs), and other computationally intensive applications. More particularly, it pertains to novel and advantageous architecture innovations for efficiently and inexpensively implementing such arrays using multiple integrated circuits. Hardware and methods are disclosed to allow compute arrays to be tested after face-to-face or wafer-to-wafer bonding and without out any pre-bonding test. Defects discovered in the post-bonding testing can be completely or partially healed increasing yields and reducing costs.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 16, 2020
    Assignee: Xcelsis Corporation
    Inventors: Javier A. Delacruz, Steven L. Teig, David Edward Fisch, William C. Plants