Abstract: A susceptor assembly, which is situated in a reactor housing, has at least one wide side plane that faces a process chamber, at least one pocket, and a carrying element that lies in the at least one pocket, for carrying and handling a substrate. An upper face of the carrying element is adjacent to a limiting face of a recess in which the substrate is arranged. A section of the limiting face which runs along a cylinder inner lateral face merges into the upper face of the carrying element, forming a rounded edge or chamfer. To reduce the growth of parasitic deposits on an inner edge of the carrying element, the section of the limiting face which runs along the cylinder inner lateral face has a height which is greater than the material thickness of the substrate, and the radius of the rounded edge is greater than 0.4 mm.

Abstract: The present disclosure provides a method and a device for testing a wafer, an electronic device, and storage medium, wherein the method includes: obtaining plural test sheets; dividing the wafers to be tested in the plurality of test sheets according to individual test items in the plurality of test sheets, and determining the wafers to be tested corresponding to individual divided units; determining a test sequence of the test items to be performed on each wafer to be tested, based on a test sequence condition of the test items in individual test sheets and a test condition of a testing machine corresponding to individual divided units; and testing the wafer to be tested, according to the test sequence of the test items to be performed on any of the wafers to be tested.

Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.

Abstract: A cleaning system capable of improving efficiency of a cleaning operation onto a work area of a machine tool. The cleaning system includes a cleaning nozzle attached to and detached from an attachment device provided in the machine tool, and configured to inject fluid; a robot configured to grip the cleaning nozzle; and a cleaning execution section configured to execute a detaching operation to operate the robot so as to grip the cleaning nozzle attached to the attachment device and detach the cleaning nozzle from the attachment device, and a cleaning operation to move the cleaning nozzle with respect to the work area by the robot, and inject the fluid from the cleaning nozzle to clean the work area.

Abstract: A plasma processing method to detect and process a thickness of the processing target film with high accuracy when a fine shape of the semiconductor wafer surface varies, including detecting a state of a processing target film of a processing target material that is processed inside a vacuum processing chamber; detecting light emission of the plasma; obtaining a differential waveform data of the light emission of the plasma; storing a plurality of pieces of differential waveform pattern data in advance; calculating an estimated value of the film thickness of the processing target film processed on the processing target material by weighting based on differences between the differential waveform data obtained and the plurality of pieces of differential waveform pattern data stored; and determining an end point of processing using the plasma based on the estimated value of the film thickness of the processing target film calculated.

Abstract: The SiC substrate has a warpage factor F of 300 ?m or less, which is obtained from the thickness, the diameter, and a stress at a first outer circumferential end 10 mm inward from an outer circumferential end in the [11-20] direction from a center thereof.

Abstract: A method for adjusting wafer deformation and a semiconductor structure are provided. The method includes the following operations. A deformation position and a deformation degree of a wafer are determined. At least one groove is formed at a back of the wafer according to the deformation position and the deformation degree. A stress film having a stress effect on the wafer deformation is formed at the back of the wafer with the at least one groove, and the stress film covers an inner wall of the at least one groove.

Abstract: An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed to detect a DFA attack by fault injection into the integrated circuit.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller and the memory device communicate using a plurality of flash channels, where each channel is mapped to one or more dies of the memory device. Each of the one or more dies of the memory device are associated with one or more strobes of a strobe cycle of a respective flash channel, where a die is provided power during a respective strobe. The controller is configured to, using a time division peak power management (TD-PPM) operation, change an association of a strobe from a first channel to a strobe of a second channel, which may adjust an amount of power provided to each of the channels and improve performance and latency of the data storage device.

Abstract: A method includes the following steps. A semiconductor wafer including integrated circuit components, seal rings respectively encircling the integrated circuit components and testing structures disposed between the seal rings is provided. A first wafer saw process is performed at least along a first path to singulate the semiconductor wafer into a plurality of first singulated integrated circuit components each including a testing structure among the testing structures. When performing the first wafer saw process, testing pads of the testing structures are located beside the first path, such that a testing pad of a corresponding one of the testing structures in the first singulated integrated circuit component is laterally spaced apart from a sidewall of the first singulated integrated circuit component by a distance.

Abstract: The present disclosure provides a method for manufacturing semiconductor structure, including forming an insulation layer, forming a first via trench in the insulation layer, forming a barrier layer in the first via trench, forming a bottom electrode via in the first via trench, forming a magnetic tunneling junction (MTJ) layer above the bottom electrode via, and performing an ion beam etching operation, including patterning the MTJ layer to form an MTJ and removing a portion of the insulation layer from a top surface.

Abstract: In an embodiment, a system includes: an orientation sensor configured to detect an orientation fiducial on a bevel of a wafer; a pedestal configured to rotate the wafer to allow the orientation sensor to detect the orientation fiducial and place the orientation fiducial at a predetermined orientation position; and a defect sensor configured to detect a wafer defect along a surface of the wafer while rotated by the pedestal.

Abstract: A semiconductor device including a substrate that has a first region and a second region, a plurality of lower conductive patterns on the substrate, the plurality of lower conductive patterns including a first conductive pattern in the first region of the substrate and a second conductive pattern in the second region of the substrate, a magnetic tunnel junction on the first conductive pattern, a contact between the magnetic tunnel junction and the first conductive pattern, a through electrode on the second conductive pattern, and a plurality of upper conductive patterns on the magnetic tunnel junction and the through electrode. The contact includes a first contact on the lower conductive patterns, a second contact on the first contact, and a first barrier layer that covers a bottom surface and a lateral surface of the second contact.

Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

Abstract: Provided is a semiconductor device that allows reduction of a measurement time of a PCMTEG and improvement of productivity in an IC manufacturing process. A PCMTEG region 100 formed on a surface of a semiconductor substrate is divided into a main PCMTEG region 101 and a sub-PCMTEG region 102, and TEGs having specifications for their electrical characteristic values are all collectively arranged in the sub-PCMTEG region 102.

Abstract: The invention discloses a wafer testing device of flip chip VCSEL for testing a wafer having a plurality of light emitting units. The wafer testing device of flip chip VCSEL comprises a wafer testing carrier and a flexible conductive layer. The wafer testing carrier has a first surface. A plurality of testing portions are disposed on the first surface. The flexible conductive layer, detachably disposed on the first surface, are conductive in vertical direction and insulated in horizontal direction. Wherein the wafer is disposed on the flexible conductive layer, and each light emitting unit is electrically connected with one of the testing portions in vertical direction through the flexible conductive layer while testing the wafer.

Abstract: A component joining apparatus, which can realize positioning between a component and a substrate with high accuracy by avoiding influence of thermal expansion of the substrate at the time of joining the component to the substrate by heating at a high temperature, includes a component supply head holding a component and a heating stage heating and holding a substrate, in which a heating region where the heating stage contacts the substrate includes a joining region of the substrate in which the component is joined, and the substrate is larger than the heating stage and a peripheral part of the substrate does not contact the heating stage.

Abstract: A method of detecting and classifying anomalies during semiconductor processing includes executing a wafer recipe a semiconductor processing system to process a semiconductor wafer; monitoring sensor outputs from a sensors that monitor conditions associated with the semiconductor processing system; providing the sensor outputs to models trained to identify when the conditions associated with the semiconductor processing system indicate a fault in the semiconductor wafer; receiving an indication of a fault from at least one of the models; and generating a fault output in response to receiving the indication of the fault.

Abstract: A polishing method is used for polishing a substrate such as a semiconductor wafer to a flat mirror finish. A method of polishing a substrate by a polishing apparatus includes a polishing table (100) having a polishing surface, a top ring (1) for holding a substrate and pressing the substrate against the polishing surface, and a vertically movable mechanism (24) for moving the top ring (1) in a vertical direction. The top ring (1) is moved to a first height before the substrate is pressed against the polishing surface, and then the top ring (1) is moved to a second height after the substrate is pressed against the polishing surface.

Abstract: Disclosed are a method and apparatus for determining electrical characteristics of a transistor, and a computer-readable storage medium. The method for determining electrical characteristics of a transistor includes: determining mobility characteristics of carriers in channels of the transistor at a transistor operating temperature condition; and determining electrical characteristics of the transistor based on the mobility characteristics of the carriers, semiconductor material properties of the transistor, and structural features of the transistor.

Abstract: Systems and methods of enhancing imaging resolution by reducing crosstalk between detection elements of a secondary charged-particle detector in a multi-beam apparatus are disclosed. The multi-beam apparatus may comprise an electro-optical system for projecting a plurality of secondary charged-particle beams from a sample onto a charged-particle detector. The electro-optical system may include a first pre-limit aperture plate comprising a first aperture configured to block peripheral charged-particles of the plurality of secondary charged-particle beams, and a beam-limit aperture array comprising a second aperture configured to trim the plurality of secondary charged-particle beams. The charged-particle detector may include a plurality of detection elements, wherein a detection element of the plurality of detection elements is associated with a corresponding trimmed beam of the plurality of secondary charged-particle beams.

Abstract: Aspects of the disclosure provide methods for polysilicon characterization. The method includes receiving image data of a polysilicon structure formed on a sample substrate. The image data is in a spatial domain and is generated by transmission electron microscopy (TEM). Further, the method includes extracting frequency spectrum of the image data in a frequency domain. Then, the method includes selecting a subset of the frequency spectrum that corresponds to characteristic of first crystal grains that are of a first orientation, and transforming the selected subset of the frequency spectrum to the spatial domain to construct a first spatial image for the first crystal grains of the first orientation.

Abstract: A substrate work system including a work device configured to perform predetermined work on a substrate by use of an exchangeable work unit includes a storage section configured to store the work unit, a maintenance device configured to perform maintenance of the work unit, a conveyance device capable of conveying the work unit, a determination section configured to determine a maintenance time for the work unit used in the work device based on quality information on work quality of the predetermined work, and a control section configured to, when the determination section determines that a maintenance time arrives, cause the conveyance device, the work device, and the maintenance device to unload the work unit, convey the work unit to the work device to exchange with the work unit that has been used, and convey the used-up work unit to the maintenance device.

Abstract: An array of light emitting devices is mounted on a support surface with the transparent growth substrate (e.g., sapphire) facing up. A photoresist layer is then deposited over the top surface of the growth substrate, followed by depositing a reflective material over the top and side surfaces of the light emitting devices to encapsulate the light emitting devices. The top surfaces of the light emitting devices are then ground down to remove the reflective material over the top surface of the photoresist. The photoresist is then dissolved to leave a cavity over the growth substrate having reflective walls. The cavity is then filled with a phosphor. The phosphor-converted light emitting devices are then singulated to form packaged light emitting devices. All side light is reflected back into the light emitting device by the reflective material and eventually exits the light emitting device toward the phosphor. The packaged light emitting devices, when energized, appear as a white dot with no side emission (e.g.

Abstract: High bandwidth time-and-space resolved phase transition microscopy systems configured to detect melt onset in a wafer being processed by laser annealing systems with ultra-short dwell times and spot size.

Abstract: A method for etching a ruthenium film includes a first step of etching the ruthenium film by plasma processing using oxygen-containing gas, and a second step of etching the ruthenium film by plasma processing using chlorine-containing gas. The first step and the second step are alternately performed. In the first step and the second step, the ruthenium film is etched at a target control temperature for a target processing time that are determined based on a pre-obtained relation between an etching amount per one cycle including the first step and the second step as a set, a control temperature of the ruthenium film, and processing times of each of the first step and the second step.

Abstract: An acoustic testing method includes providing an electrical signal to a wafer, receiving a sound wave generated by the acoustic transducer according to the electrical signal, and generating a sensing result for determining an acoustic functionality of the acoustic transducer. The wafer includes a plurality of acoustic transducers, and the electrical signal is provided to an acoustic transducer within the wafer.

Abstract: A test device for a high-speed/high-frequency test. The test device includes: a conductive block which includes a probe hole; at least one signal probe which is supported in an inner wall of the probe hole without contact, includes a first end to be in contact with a testing contact point of the object to be tested, and is retractable in a lengthwise direction; and a coaxial cable which includes a core wire to be in electric contact with a second end of the signal probe. With this test device, the coaxial cable is in direct contact with the signal probe, thereby fully blocking out noise in a test circuit board.

Abstract: A method for determining an overlapping process window (OPW) of an area of interest on a portion of a design layout for a device manufacturing process for imaging the portion onto a substrate, the method including: obtaining a plurality of features in the area of interest; obtaining a plurality of values of one or more processing parameters of the device manufacturing process; determining existence of defects, probability of the existence of defects, or both in imaging the plurality of features by the device manufacturing process under each of the plurality of values; and determining the OPW of the area of interest from the existence of defects, the probability of the existence of defects, or both.

Abstract: High intensity multi-directional FDM 3D printing method for stereo vision monitoring involves intelligent control and computer vision technology. Specifically, it involves multi-directional 3D printing hardware platform construction, stereo vision detection, laser heating to enhance the connection strength between various parts of the model, so as to reduce the use of external support structure as much as possible on the premise of ensuring the printing accuracy, and make the various parts of the model can be well connected to enhance the integrity of the model.

Abstract: The present invention provides an identification key generating device and an identification key generating method. The identification key generating device comprises: a plurality of unit cells provided on a circuit in a semiconductor manufacturing procedure; a reading unit for reading for shorting of each of the unit cells; a digital value generation unit for determining the probability for the shorting of each of the unit cells, and generating a digital value of each of the unit cells on the basis of the reading for shorting from the reading unit; and a selection unit for selecting at least one of the plurality of unit cells, wherein an identification key is generated from a combination of respective digital values generated from the unit cells selected by means of the selection unit.

Abstract: The present disclosure provides a method for measuring an underfill profile of an underfill material in an underfill cavity having a plurality of solder bumps. The method includes the operations of: determining a mesh having a plurality of elements according to the underfill cavity; calculating a reference force according to the underfill cavity; obtaining a driving force and a flow speed of the underfill material according to a plurality of weighting factors and the reference force, wherein the plurality of weighting factors respectively correspond to the plurality of elements; obtaining a plurality of volume fractions respectively corresponding to the plurality of elements according to the flow speed; and obtaining the underfill profile according to the plurality of volume fractions.

Abstract: There is provided a substrate processing method including: reducing an oxide of a ruthenium film by supplying a hydrogen-containing gas to a substrate including the ruthenium film; etching the ruthenium film by supplying an oxygen-containing gas to the substrate so as to oxidize the ruthenium film; and repeating, multiple times, a cycle including reducing the oxide of the ruthenium film and etching the ruthenium film.

Abstract: A method for verifying semiconductor wafers includes receiving a semiconductor wafer including a plurality of layers. A first set of measurement data is obtained for at least one layer of the plurality of layers, where the first set of measurement data includes at least one previously recorded thickness measurement for one or more portions of the at least one layer. The first set of measurement data is compared to a second set of measurement data for the at least one layer. The second set of measurement data includes at least one new thickness measurement for the one or more portions of the at least one layer. The semiconductor wafer is determined to be an authentic wafer based on the second set of measurement data corresponding to the first set of measurement data, otherwise the semiconductor is determined to not be an authentic wafer.

Abstract: An example of a method of micro-transfer printing comprises providing a micro-transfer printable component source wafer, providing a stamp comprising a body and spaced-apart posts, and providing a light source for controllably irradiating each of the posts with light through the body. Each of the posts is contacted to a component to adhere the component thereto. The stamp with the adhered components is removed from the component source wafer. The selected posts are irradiated through the body with the light to detach selected components adhered to selected posts from the selected posts, leaving non-selected components adhered to non-selected posts. In some embodiments, using the stamp, the selected components are adhered to a provided destination substrate. In some embodiments, the selected components are discarded. An example micro-transfer printing system comprises a stamp comprising a body and spaced-apart posts and a light source for selectively irradiating each of the posts with light.

Abstract: The present disclosure relates to a power interface, and more particularly, to a power interface for electrically connecting an object to be tested and a test driving unit. The electric power interface in accordance with an exemplary embodiment includes: a support member; an elastic member fixed to the support member and configured to provide an elastic force in a vertical direction; a first connection terminal disposed on the elastic member; a second connection terminal electrically connected to the first connection terminal; and a flexible sheet has one side fixed to the elastic member and the other side fixed to the support member to restrict a deformation range of the elastic member.

Abstract: Embodiments related to systems and methods for thickness measurement in semiconductor structures are disclosed. For example, a method for thickness detection in a semiconductor structure may include detecting, by at least one processor, a tilt of an image of a stack of layers in the semiconductor structure. The method may also include performing, by the at least one processor, rough boundary line detection on the layers of the stack in the image. The method may further include performing, by the at least one processor, fine thickness detection on the layers of the stack in the image. The rough boundary line detection may detect boundaries of the layers of the stack with a first precision and the fine thickness detection may detect thickness of the layers of the stack with a second precision greater than the first precision. The method may additionally include providing, by the at least one processor, output results of the fine thickness detection.

Abstract: In some embodiments, a field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.

Abstract: Systems, metrology modules and methods are provided, which identify, per wafer site, components of residuals from measurement of metrology metric(s), and optimize measurement parameters for each site, according to the identified residuals' components. Certain embodiments utilize metric landscapes to identify sensitive sites and/or to identify sites exhibiting highest accuracy, and corresponding metrics may be combined over the wafer to further enhance the metrology performance. Zonal analysis may be used to reduce the systematic errors, and disclosed per-site analysis may be used to further reduce the non-systematic error components, and relate the remaining residuals components to process variation over the wafer.

Abstract: A method of producing microelectronic components includes forming a functional layer system; applying a laminar carrier to the functional layer system; attaching a workpiece to a workpiece carrier; utilizing incident radiation of a laser beam is focused in a boundary region between a growth substrate and the functional layer system, and a bond between the growth substrate and the functional layer system in the boundary region is weakened or destroyed; separating a functional layer stack from the growth substrate, wherein a vacuum gripper having a sealing zone that circumferentially encloses an inner region is applied to the reverse side of the growth substrate, a negative pressure is generated in the inner region such that separation of the functional layer stack from the growth substrate is initiated in the inner region; and the growth substrate held on the vacuum gripper is removed from the functional layer stack.

Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.

Abstract: Devices, systems, and methods obtain a reference image; obtain a test image; globally align the test image to the reference image; select subfields in the test image; align the subfields in the test image with respective areas in the reference image; warp the test image based on the aligning of the subfields; select anchor points in the reference image; select anchor-edge points in the reference image; realign the subfields in the warped test image with respective areas in the reference image based on the anchor points in the reference image and on the anchor-edge points in the reference image; and warp the warped test image based on the realigning of the subfields.

Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.

Abstract: Example systems for determining a configuration of a test system execute operations that include receiving first parameters specifying at least part of an operation of a test system; receiving second parameters specifying at least part of a first configuration of the test system; determining a second configuration of the test system based, at least in part, on the first parameters and the second parameters, with the second configuration being determined to impact a cost of test of the test system; generating, by one or more processing devices, data for a graphical user interface representing information about the second configuration and the cost of test; and outputting the data for the graphical user interface for rendering on a display device.

Abstract: Devices, systems, and methods obtain a reference image; obtain a test image; globally align the test image to the reference image; select subfields in the test image; align the subfields in the test image with respective areas in the reference image; warp the test image based on the aligning of the subfields; select anchor points in the reference image; select anchor-edge points in the reference image; realign the subfields in the warped test image with respective areas in the reference image based on the anchor points in the reference image and on the anchor-edge points in the reference image; and warp the warped test image based on the realigning of the subfields.

Abstract: There is provided a method for correcting a relative position between a probe card having a plurality of cantilever-type probes and an object to be inspected having a plurality of electrode pads, including: arranging a first group of cantilever-type probes among the plurality of cantilever-type probes in a first region and a second region; arranging a second group of cantilever-type probes among the plurality of cantilever-type probes in a third region and a fourth region; obtaining needle traces formed on the plurality of electrode pads, which are generated when the first group of cantilever-type probes and the second group of cantilever-type probes that are arranged in the first region, the second region, the third region, and the fourth region, are brought into contact with the plurality of electrode pads; and correcting the relative position between the probe card and the object to be inspected based on the obtained needle traces.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; forming a pad layer adjacent to two sides of trench; forming a dielectric layer to fill the trench; and performing a dry etching process to remove the pad layer and part of the dielectric layer to form a shallow trench isolation (STI). Preferably, the dry etching process comprises a non-plasma etching process.

Abstract: This disclosure relates to a method for using a high volume manufacturing system for processing and measuring workpieces in a semiconductor processing sequence without leaving the system's controlled environment (e.g., sub-atmospheric pressure). The system includes an active interdiction control system to implement corrective processing within the system when a non-conformity is detected. The corrective processing method can include a remedial process sequence to correct the non-conformity or compensate for the non-conformity during subsequent process. The non-conformity may be associated with fabrication measurement data, process parameter data, and/or platform performance data.

Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

Abstract: A semiconductor device includes a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, first and second probe pads electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the substrate and the detecting devices. A method for detecting defects in a semiconductor device includes singulating a die having a substrate, a plurality of detecting devices, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring; probing the first and the second probe pads to determine a connection status of the detecting devices; and recognizing a defect when the connection status of the detecting devices indicates an open circuit.