With Measuring Or Testing Patents (Class 438/14)
  • Patent number: 10797118
    Abstract: A touch panel, a method for fabricating the same, and a display device are provided. The touch panel includes: a base substrate, a plurality of touch electrode lines, a plurality of cathodes arranged in a matrix, and a plurality of spacers, where each cathode corresponds to at least one of the touch electrode lines, and each spacer includes a first photo spacer and a second photo spacer stacked successively; each touch electrode line includes a first lead part and a second lead part, wherein the first lead part is electrically connected with corresponding one of the cathodes, and the second lead part is configured to electrically connect the first lead part with a corresponding pin on a touch integrated circuit; and the first lead part at least covers the surface of the first photo spacer.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: October 6, 2020
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Shengji Yang, Xue Dong, Xiaochuan Chen, Minghua Xuan, Lei Wang, Pengcheng Lu, Li Xiao, Dongni Liu, Jing Yu
  • Patent number: 10775780
    Abstract: A causal relationship model building system includes a computer which processes information for building a causal relationship model relating to a manufacturing flow of an object to be controlled. The computer builds the causal relationship model by using monitor data representing a state of each of a plurality of steps of the manufacturing flow, and quality data as a result of an inspection step, and specifies an allowable range of the monitor data so as to satisfy a target value of the quality data, by using the causal relationship model and the target value, from prediction based on a causal relationship between a plurality of pieces of the monitor data. The computer graphically displays information including the causal relationship model and the allowable range of the monitor data on a display screen.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: September 15, 2020
    Assignee: HITACHI, LTD.
    Inventors: Kazuki Horiwaki, Kei Imazawa
  • Patent number: 10773410
    Abstract: A cut groove having a predetermined depth is formed with a cutting blade along a projected dicing line set on a workpiece. A first preliminary groove is cut in a measurement member and a relational expression with respect to a distance from the preliminary groove bottom and the width of the preliminary groove is determined. An amount of incision into the workpiece is set to be equal to or smaller than a predetermined value from a reference position and the thickness of the workpiece. A second preliminary groove is cut along the projected dicing line, and an image of the second preliminary cut groove is captured. The width of the second preliminary cut groove is measured, and the depth of the second preliminary cut groove is calculated from the width of the second preliminary groove and the relational expression.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: September 15, 2020
    Assignee: DISCO CORPORATION
    Inventors: Atsushi Komatsu, Atsushi Takagi
  • Patent number: 10748887
    Abstract: The present invention relates to a method for designing a die-based vehicle controller-only semiconductor and a vehicle controller-only semiconductor manufactured by the same, and breaks the conventional semiconductor process to design and manufacture a novel conceptual vehicle controller-only semiconductor, EIP (ECU in Package), through a fusion of a new semiconductor process technique with a controller system technique, thereby obtaining an effect of capable of implementing a high performance/high quality semiconductor in micro-miniature size/ultra-light weight in a short time period.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: August 18, 2020
    Assignee: Hyundai Autron Co., Ltd.
    Inventors: Jae-Ho Chang, Eun-Jung Kim, Jae-Woo Joung
  • Patent number: 10748821
    Abstract: A method for measuring pattern placement error (PPE) on a wafer includes receiving a photomask pattern. One or more unit cell patterns are added to the photomask pattern. Each of the unit cell patterns includes at least one reference design pattern and at least one PPE check design pattern. A photomask is fabricated from the photomask pattern with the one or more unit cell patterns added thereto. A wafer is patterned using the fabricated photomask. A microscope image of the patterned wafer is acquired. Pattern placement error is measured as a displacement between the at least one reference design pattern and the at least one PPE check design pattern.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Gyeongseop Kim
  • Patent number: 10749065
    Abstract: A light-responsive LED (Light Emitting Diode) based on a GaN/CsPbBrxI3-x heterojunction, a preparation method and an application thereof are provided. The light-responsive LED consists of a GaN base layer on a sapphire substrate, an all-inorganic perovskite CsPbBrxI3-x film, an indium electrode and a carbon electrode, forming an In/GaN/CsPbBrxI3-x/C structure, wherein: in the CsPbBrxI3-x film, 0<x<3; the all-inorganic perovskite CsPbBrxI3-x film and the indium electrode are arranged on the GaN base layer in parallel; and the carbon electrode is arranged on the all-inorganic perovskite CsPbBrxI3-x film. The CsPbBrxI3-x film is prepared through a low-temperature anti-solvent method.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: August 18, 2020
    Assignee: HUBEI UNIVERSITY
    Inventors: Hao Wang, Hai Zhou, Guokun Ma, Zehao Song
  • Patent number: 10727071
    Abstract: Provided is a method of analyzing metal contamination of a silicon wafer, the method including etching a surface layer region of the silicon wafer by bringing a surface of a silicon wafer to be analyzed into contact with etching gas that includes hydrogen fluoride gas and nitric acid gas; bringing an exposed surface of the silicon wafer, exposed by the etching, into contact with gas generated from a mixed acid including hydrochloric acid and nitric acid; heating the silicon wafer that has been brought into contact with the gas generated from the mixed acid; bringing the exposed surface, exposed by the etching, of the silicon wafer after the heating into contact with a recovery solution; and analyzing a metal component in the recovery solution that has been brought into contact with the exposed surface, exposed by the etching, of the silicon wafer.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: July 28, 2020
    Assignee: SUMCO CORPORATION
    Inventor: Taisuke Mizuno
  • Patent number: 10697059
    Abstract: Methods and apparatuses for performing atomic layer deposition are provided. A method may include determining an amount of accumulated deposition material currently on an interior region of a deposition chamber interior, wherein the amount of accumulated deposition material changes over the course of processing a batch of substrates; applying the determined amount of accumulated deposition material to a relationship between a number of ALD cycles required to achieve a target deposition thickness, and a variable representing an amount of accumulated deposition material, wherein the applying returns a compensated number of ALD cycles for producing the target deposition thickness given the amount of accumulated deposition material currently on the interior region of the deposition chamber interior; and performing the compensated number of ALD cycles on one or more substrates in the batch.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: June 30, 2020
    Assignee: Lam Research Corporation
    Inventors: Richard Phillips, Chloe Baldasseroni, Nishanth Manjunath
  • Patent number: 10689762
    Abstract: A substrate processing apparatus can suppress particle generation on a substrate, and can reduce a consumption amount of a processing liquid. A substrate processing apparatus 1 includes a processing chamber 30 having a processing space 31 in which a substrate W is processed; a vaporizing tank 60, configured to store the processing liquid therein, having a vaporization space 61 in which the stored processing liquid is allowed to be vaporized; a decompression driving unit 70 configured to decompress the vaporization space 61; and a control unit 18. The control unit 18 vaporizes the processing liquid into the processing gas by decompressing the vaporization space 61 without through the processing space 31, and then, vaporizes the processing liquid into the processing gas by decompressing the vaporization space 61 through the processing space 31, and supplies an inert gas into the vaporization space 61.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: June 23, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akira Murata, Satoshi Kaneko, Kazuki Motomatsu, Kazunori Sakamoto
  • Patent number: 10692747
    Abstract: A method for aligning and contacting a first substrate with a second substrate using a plurality of detection units, and a corresponding device for alignment and contact.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: June 23, 2020
    Assignee: EV Group E. Thallner GmbH
    Inventors: Thomas Wagenleitner, Dominik Zinner, Jurgen Markus Suss, Christian Sinn, Jurgen Mallinger
  • Patent number: 10684929
    Abstract: This disclosure pertains to hardware compute arrays (sometimes called systolic arrays) for applications such as artificial intelligence (AI), machine learning (ML), digital signal processing (DSP), graphics processing units (GPUs), and other computationally intensive applications. More particularly, it pertains to novel and advantageous architecture innovations for efficiently and inexpensively implementing such arrays using multiple integrated circuits. Hardware and methods are disclosed to allow compute arrays to be tested after face-to-face or wafer-to-wafer bonding and without out any pre-bonding test. Defects discovered in the post-bonding testing can be completely or partially healed increasing yields and reducing costs.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 16, 2020
    Assignee: Xcelsis Corporation
    Inventors: Javier A. Delacruz, Steven L. Teig, David Edward Fisch, William C. Plants
  • Patent number: 10677841
    Abstract: A composite product testing system including a main management system, a test equipment and a burn-in apparatus is disclosed. The test equipment and the burn-in apparatus are both arranged in a burn-in chamber of the testing system. First, multiple tested products are respectively inserted in multiple gauges of the burn-in chamber, and a burn-in procedure is activated for providing an aging environment. The main management system controls one of the gauges to connect with the test equipment for the test equipment to perform testing on the tested product upon the connected gauge. After the testing is completed, the main management system then controls the gauge to disconnect from the test equipment and re-connect with the burn-in apparatus, so as to monitor the tested product upon the gauge during the burn-in procedure.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: June 9, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chien-Chung Chang, Hung-Pin Yu, Yu-Jen Chen, Wen-Jen Lo, Chih-Yen Liu
  • Patent number: 10642029
    Abstract: Disclosed herein is a compact beam scanner assembly that includes an ellipsoidal reimaging mirror.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: May 5, 2020
    Assignee: AEYE, INC.
    Inventors: Luis Carlos Dussan, David R. Demmer, John Stockton, Allan Steinhardt, David Cook
  • Patent number: 10635576
    Abstract: According to some examples, computer-implemented methods for branch coverage guided symbolic execution for hybrid fuzzing are described. An example computer-implemented method may include receiving a seed input of a binary program under analysis (BPUA) that is discovered during testing by a greybox fuzzer. The method may also include concretely executing the seed input in the BPUA, and collecting a trace resulting from the concrete execution of the seed input. The method may further include determining whether the concrete execution of the seed input discovers a new branch. The method may include, responsive to a determination that the concrete execution of the seed input discovers a new branch, updating a bitmap to indicate that the new branch is discovered, wherein the bitmap is utilized by the greybox fuzzer to maintain a record of discovered branches in BPUA, and providing the seed input to the greybox fuzzer.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: April 28, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Quoc-Sang Phan, Praveen Murthy
  • Patent number: 10614262
    Abstract: A method and system for determining a defect in a critical area in a multi-layer semiconductor substrate is disclosed. A server receives information describing a defect on a first layer of the semiconductor substrate. The server identifies a critical area of a second layer below the first layer of the semiconductor substrate determines a probability of the defect migrating from the first layer to the critical area of the second layer. The server determines, based on the probability, the likelihood of an open or a short occurring as a result of the defect occurring in the critical area. The server provides, based on the likelihood, predictive information to a manufacturing system, wherein corrective action is taken based on the predictive information in order to reduce or eliminate the likelihood of the open or short.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: April 7, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Raman K. Nurani, Anantha R. Sethuraman, Koushik Ragavan, Karanpreet Aujla
  • Patent number: 10585251
    Abstract: An optical modulator and an optical transmission device using the same are provided. The optical modulator includes an optical waveguide substrate where an optical waveguide is formed; a light modulation element, provided in the optical waveguide substrate and including a modulation electrode applying an electric field corresponding to a modulation signal to the optical waveguide; a terminal substrate, disposed near the light modulation element and including terminal resistors that terminate the modulation signal, wherein the optical waveguide substrate, the light modulation element and the terminal substrate are accommodated in a housing; and a heat dissipation auxiliary element, provided between the terminal resistors and the housing. A distance b between the terminal resistors and the heat dissipation element is set to be shorter than a distance a from the terminal resistors to an end on the side of the optical waveguide substrate of the terminal substrate.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: March 10, 2020
    Assignee: SUMITOMO OSAKA CEMENT CO., LTD.
    Inventors: Norikazu Miyazaki, Toru Sugamata
  • Patent number: 10564634
    Abstract: In a method for setting a mounting position of a target substrate, the test substrate is transferred to a second position deviated from a first position. A mask has expected arrangement position where a non-film formation region has a preset width when the target substrate is mounted at the first position and subjected to a film formation. The film is formed on the test substrate at the second position by using the mask. Width of the non-film formation region formed on the test substrate after the film formation is measured. Actual arrangement position of the mask is specified based on a direction and a distance of the deviation of the second position from the first position and the measured width of the non-film formation region. The first position is corrected such that the non-film formation region has the preset width based on the actual arrangement position of the mask.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: February 18, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Yasunobu Suzuki
  • Patent number: 10566533
    Abstract: A method for pixel patterning and pixel position inspection of an organic light-emitting display device includes: forming, on a substrate using a first mask, a thin film layer of a first color corresponding to a first pixel pattern and a first pixel positioning pattern for inspecting a position of a first pixel; shifting, by a determined pitch, the first mask from a position associated with forming the thin film layer of the first color; aligning the shifted first mask with respect to the substrate; and forming, on the substrate using the shifted first mask, a thin film layer of a second color corresponding to the first pixel pattern and another first pixel positioning pattern for inspecting a position of a second pixel.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: February 18, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sangshin Lee, Dongjin Ha, Mingoo Kang, Ohseob Kwon, Sangmin Yi
  • Patent number: 10551247
    Abstract: The present invention relates to methods for analyzing a chemical sample. For instance, the methods herein allow for global analysis of spectroscopy data in order to extract useful chemical properties from complicated multidimensional data. Such analysis can optionally employ data compression to further expedite computer-implemented computation. In particular, the methods herein provide global analysis of data matrices explained by both linear and non-linear terms.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: February 4, 2020
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Mark Van Benthem, James A. Ohlhausen
  • Patent number: 10551174
    Abstract: The present invention includes a preparatory step of providing a calibration work piece having a flat reflecting surface as a work piece, and arranging the reflecting surface to be parallel to a standard optical axis and orthogonal or parallel to pixel array directions of an image capture element; a rotation step of rotating a prism centered on the standard optical axis; a brightness detection step of detecting the brightness of an image captured by the image capture element at each of a plurality of rotation positions of the prism; and a positioning step of aligning the prism at a rotation position where the brightness detected by the brightness detection step is greatest.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: February 4, 2020
    Assignee: MITUTOYO CORPORATION
    Inventor: Yasuhiro Takahama
  • Patent number: 10553641
    Abstract: A light emitting device package includes a substrate for growth having a plurality of light-emitting windows, a plurality of semiconductor light-emitting units corresponding to the plurality of light-emitting windows, each semiconductor light-emitting unit having a first surface contacting the substrate for growth and a second surface opposite the first surface, and each semiconductor light-emitting unit having a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer stacked on each other, a plurality of wavelength conversion units respectively disposed inside the plurality of light-emitting windows, each wavelength conversion unit is configured to provide light having a wavelength different from light emitted by the respective semiconductor light-emitting unit, a metal support layer disposed on at least one surface of each of the plurality of semiconductor light-emitting units and having a lateral surface coplanar with a lateral surface of the substra
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: February 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Hye Yeon, Sung Hyun Sim, Wan Tae Lim, Yong Il Kim, Hanul Yoo
  • Patent number: 10541178
    Abstract: A method of evaluating the quality of a thin film layer may include: forming the thin film layer on a substrate; applying a stress to the thin film layer; and evaluating the quality of the thin film layer. A device for evaluating the quality of the thin film layer may include a stress chamber for applying a stress to the thin film layer and a refractive index measuring unit for evaluating the quality of the thin film layer based on a rate of change of a refractive index.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: January 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Xianyu Wenxu, Yongyoung Park, Kideok Bae, Wooyoung Yang, Changseung Lee
  • Patent number: 10529594
    Abstract: Embodiments of the inventive concept relate to an apparatus for treating a substrate in a high-pressure atmosphere. The apparatus includes a process chamber having an upper body and a lower body that are combined with each other to provide a treatment space therein, an elevation member configured to elevate any one of the upper body and the lower body to an opening location at which the upper body and the lower body is spaced apart or a closing location at which the upper body and the lower body is attached, a clamping member configured to clamp the upper body and the lower body located at the closing location, and a movable member configured to move the clamping member to a locking location at which the clamping member clamps the process chamber or to the release location at which the clamping member is spaced apart from the process chamber.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: January 7, 2020
    Assignee: SEMES CO., LTD.
    Inventors: Do-Youn Lim, Joonho Won, Kisang Eum, Boong Kim, Joo Jib Park
  • Patent number: 10520832
    Abstract: Metrology tools and methods are provided, which estimate the effect of topographic phases corresponding to different diffraction orders, which result from light scattering on periodic targets, and adjust the measurement conditions to improve measurement accuracy. In imaging, overlay error magnification may be reduced by choosing appropriate measurement conditions based on analysis of contrast function behavior, changing illumination conditions (reducing spectrum width and illumination NA), using polarizing targets and/or optical systems, using multiple defocusing positions etc. On-the-fly calibration of measurement results may be carried out in imaging or scatterometry using additional measurements or additional target cells.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: December 31, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Vladimir Levinski, Yuri Paskover, Amnon Manassen, Yoni Shalibo
  • Patent number: 10516725
    Abstract: Roughly described, a technique for approximating a target property of a target material is provided. For each material in a plurality of anchor materials, a correspondence is provided between the value for a predetermined index property of the material and a value for the target property of the material, the values of all the index properties being different. A predictor function is identified in dependence upon the correspondence. A computer system determines a value for the target property for the target material in dependence upon the predictor function and a value for the index property for the target material. The determined value for the target property for the target material is reported to a user. The correspondence can be provided in a database on a non-transitory computer readable medium. The correspondence can be determined experimentally or analytically for each material in a plurality of anchor materials.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: December 24, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Victor Moroz, Stephen Lee Smith, Yong-Seog Oh, Jie Liu, Michael C. Shaughnessy-Culver, Terry Sylvan Kam-Chiu Ma
  • Patent number: 10490458
    Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsu-Hsiu Perng, Kai-Chieh Yang, Zhi-Chang Lin, Teng-Chun Tsai, Wei-Hao Wu
  • Patent number: 10490614
    Abstract: A display device includes a thin film transistor, a gate insulting layer, an interlayer insulating layer, a data line, a spacer, and a pixel. The thin film transistor includes a semiconductor layer and a gate electrode. The semiconductor layer includes a source region and a drain region on respective sides of the channel region. The gate insulating layer is between the semiconductor layer and the gate electrode. The interlayer insulating layer covers the thin film transistor. The data line contacts the semiconductor layer via a hole passing through the gate insulating layer and the interlayer insulating layer. The spacer is on an inner wall of the hole and contacting the data line. The pixel electrode is electrically connected to the thin film transistor.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: November 26, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Subin Bae, Shinil Choi, Changok Kim, Chulmin Bae, Sanggab Kim, Sunghoon Yang, Yeoungkeol Woo, Yugwang Jeong
  • Patent number: 10466596
    Abstract: The present disclosure is directed to a method of determining at least one correctable for a process tool. In an embodiment, the method includes the steps of: measuring one or more parameter values at one or more measurement locations of each field of a selection of measured fields of a wafer; estimating one or more parameter values for one or more locations of each field of a selection of unmeasured fields of the wafer; and determining at least one correctable for a process tool based upon the one or more parameter values measured at the one or more measurement locations of each field of the selection of measured fields of the wafer and the one or more parameter values estimated for the one or more locations of each field of the selection of unmeasured fields of the wafer.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: November 5, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Bill Pierson, Ramkumar Karur-Shanmugam, Chin-Chou Huang, Ady Levy, John Charles Robinson
  • Patent number: 10436829
    Abstract: A device for measuring electrical properties of electrical contacts within an electroplating apparatus has a disc-shaped structure like that of a wafer. Multiple conductive pads are formed to collectively circumscribe an outer periphery of the disc-shaped structure. Adjacently positioned ones of the conductive pads are electrically isolated from each other. The device includes a current source that supplies electric current at a first terminal and sinks electric current at a second terminal. The device includes measurement circuitry, having first and second input terminals, that determines a value of an electrical parameter based on signals present at the first and second input terminals. The device includes switching circuitry for connecting selected ones of the conductive pads to the first and second terminals of the current source and to the first and second input terminals of the measurement circuitry at a given time. The device also includes an onboard power supply.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: October 8, 2019
    Assignee: Lam Research Corporation
    Inventors: Mark E. Emerson, Steven T. Mayer, Lawrence Ossowski
  • Patent number: 10431708
    Abstract: An integrated circuit including ESD device is disclosed. One embodiment includes a semiconductor region being electrically isolated from adjacent semiconductor regions by an isolating region. Both an ESD device and a device configured to emit radiation are formed within the semiconductor region.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: October 1, 2019
    Assignee: Infineon Technologies AG
    Inventors: Michael Mayerhofer, Joost Willemen, David Johnsson
  • Patent number: 10422037
    Abstract: A film formation apparatus and a film formation method that can homogenize the distribution of gas in each zone in a chamber and improve film formation precision are provided. A film formation apparatus according to one embodiment includes: a chamber which includes a plurality of zones into which gas is introduced, and a plurality of discharge ports that discharge the gas located in at least any of the zones and that can individually adjust an opening state; and a transportation unit that transports a substrate so as to pass through the plurality of the zones in the chamber.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: September 24, 2019
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventor: Masato Kon
  • Patent number: 10409171
    Abstract: A process control system may include a controller configured to receive after-development inspection (ADI) data after a lithography step for the current layer from an ADI tool, receive after etch inspection (AEI) overlay data after an exposure step of the current layer from an AEI tool, train a non-zero offset predictor with ADI data and AEI overlay data to predict a non-zero offset from input ADI data, generate values of the control parameters of the lithography tool using ADI data and non-zero offsets generated by the non-zero offset predictor, and provide the values of the control parameters to the lithography tool for fabricating the current layer on the at least one production sample.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: September 10, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Michael E. Adel, Amnon Manassen, William Pierson, Ady Levy, Pradeep Subrahmanyan, Liran Yerushalmi, DongSub Choi, Hoyoung Heo, Dror Alumot, John Charles Robinson
  • Patent number: 10395933
    Abstract: A method for manufacturing a semiconductor wafer including: slicing off a plurality of wafers from an ingot; chamfering outer peripheral portions of the plurality of sliced wafers; and performing double-side polishing to polish both surfaces of each wafer whose outer peripheral portion is held by a carrier, wherein includes performing warp direction adjustment to uniform directions of warps of the plurality of wafers in one direction after the slicing and before the chamfering, and the chamfering and the double-side polishing are performed in a state where the directions of the warps of the plurality of wafers are uniformed in one direction after the warp direction adjustment. Consequently, it is possible to provide the method for manufacturing a semiconductor wafer which can suppress degradation of flatness of the double-side polished wafers even in case of uniforming the directions of the warps of the wafers in one direction before the double-side polishing.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: August 27, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Yoshihiro Usami, Shiro Amagai
  • Patent number: 10388662
    Abstract: A manufacturing method of a semiconductor memory device includes disposing a first stacked body on a substrate, forming a first through via hole in the first stacked body, and determining to remove an upper portion of the first stacked body based on a comparison of a determined value of a width of the first through via hole with a reference value. The method further includes forming a second film in the first through via hole responsive to the determination to remove the upper portion of the first stacked body, removing the upper portion of the first stacked body and a portion of the second film, and disposing a second stacked body on the first stacked body and the second film. The method further includes forming a second through via hole to expose at least a portion of the second film, and removing the second film in the first through via hole.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: August 20, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazunori Horiguchi, Takashi Ohashi
  • Patent number: 10365557
    Abstract: A method, system or computer usable program product for building a fast lithography OPC model that predicts semiconductor manufacturing process outputs on silicon wafers including providing a first principles model of the semiconductor manufacturing process, providing a set of empirical data for storage in memory, utilizing a processor to develop a rigorous model for a process condition from the first principles model and the set of empirical data, and utilizing the processor running the rigorous model to generate emulated data for the process condition to develop a virtual model for predicting the semiconductor manufacturing process outputs.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: July 30, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Artak Isoyan, Lawrence S. Melvin, III
  • Patent number: 10356391
    Abstract: 3D information may be extracted from two 2D images by capturing a first image of a sample at a first orientation. The sample may be titled at a second or different orientation, resulting in a second image of the titled sample to be captured. Third dimension of information may be extracted from the images.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: July 16, 2019
    Assignee: Triad National Security, LLC
    Inventors: Benjamin P. Eftink, Stuart Andrew Maloy
  • Patent number: 10356614
    Abstract: A secure element uses a backup context to restore a deleted electronic Subscriber Identity Module (eSIM) without compromising a trust relationship with a mobile network operator (MNO). A backup copy of a data binary large object (data blob) originally used to instantiate the eSIM is retrieved. The secure element determines if the eSIM within the data blob is uniquely associated with the secure element from a previous installation. The secure element examines the data blob to determine an identifier unique to the eSIM. The identifier can be an integrated circuit card identifier (ICC-ID) or a profile identifier. The secure element searches a table of instantiated eSIMs in the secure memory. If the secure element is able to match the recovered eSIM identifier with an entry in the table, then the secure element installs this eSIM in the secure element.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: July 16, 2019
    Assignee: Apple Inc.
    Inventors: Li Li, Arun G. Mathias
  • Patent number: 10345102
    Abstract: A method for evaluating warpage of a wafer, includes measuring the warpage of the wafer that is in a free state without suction and determining, from measured warpage data, a wafer warpage amount A between two points Q1 and Q2 and a wafer warpage amount B between two points R1 and R2, the points Q1 and Q2 being located on a straight line passing through an arbitrary point P in a wafer plane and a distance “a” away from the point P, the points R1 and R2 being located on the same straight line and a distance “b” away from the point P, the distance “b” differing from the distance “a”, calculating, from the wafer warpage amount A and the wafer warpage amount B, a difference in wafer warpage amount at the point P, and evaluating the warpage on the basis of the difference in wafer warpage amount.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: July 9, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Hisayuki Saito
  • Patent number: 10345371
    Abstract: A method is provided for parameter extraction of a semiconductor device with a multi-finger gate. The method includes measuring gate-to-source and gate-to-drain capacitances and performing 3D simulation to compute fringing capacitances, thereby computing an overlap capacitance between the gate and a source/drain extension region, and computing a length of the source/drain extension region according to the overlap capacitance.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: July 9, 2019
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Jyh-Chyurn Guo, Yen-Ying Lin
  • Patent number: 10338132
    Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring. An integrated circuit device includes a core circuit and a wear-out monitor device. The wear-out monitor device configured to adjust an indication of wear out of the core circuit regardless of whether the core circuit is activated The integrated circuit further includes a sensing circuit coupled to the wear-out monitor device and configured to detect an electrical property of the wear-out monitor device that is indicative of a wear-out level of the core-circuit.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: July 2, 2019
    Assignee: Analog Devices Global
    Inventors: Edward John Coyne, Alan J. O'Donnell, Colm Patrick Heffernan, Kevin B. Manning, Mark Forde, David J. Clarke, Thomas G. O'Dwyer, David Aherne, Michael A. Looby
  • Patent number: 10331027
    Abstract: The present invention provides an imprint apparatus which performs an imprint process for forming a pattern on an imprint material on a substrate using a mold, the apparatus including an obtaining unit configured to obtain each shape of a plurality of shot regions on the substrate before the mold and the shot region as an imprint target on the substrate face each other, a first correction unit configured to correct, for each shot region on the substrate, a shape difference between a pattern of the mold and the shot region, a measurement unit configured to measure a displacement between the pattern of the mold and the shot region on the substrate, a second correction unit configured to correct the displacement, and a control unit configured to control the imprint process.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: June 25, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hiroshi Sato, Hiroshi Morohoshi, Yukio Takabayashi
  • Patent number: 10310490
    Abstract: A method and apparatus for evaluating and controlling a semiconductor manufacturing process having a plurality of process steps in a process flow is described. The method comprises retrieving measurements of process step parameters from a process measurement database. The process step parameters comprise at least one of process step measurement data, process step context data or process step control data. The process step parameters are subsequently associated with one or more of the process steps.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: June 4, 2019
    Assignee: Qoniac GmbH
    Inventors: Stefan Buhl, Martin Rößiger, Boris Habets
  • Patent number: 10288423
    Abstract: A measuring apparatus, for measuring the distance to a surface having fluctuating reflectivity, the measuring apparatus comprising, a measuring light source and sensor unit positioned at an angle to the perpendicular of the surface to allow the light to be reflected to a diffuse target surface in a known position; and a processor unit, wherein the processor unit is adapted to collect and analyze data from the a measuring light source and sensor unit and classify whether the reading of the measuring light source and sensor unit is a direct reading or a reflected reading.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: May 14, 2019
    Assignee: HATCH LTD.
    Inventor: Owen Pearcey
  • Patent number: 10269661
    Abstract: According to an embodiment, a manufacturing system for a semiconductor device includes a first processing device and a second processing device, a measurement section, and an analysis section. The first processing device and the second processing device are adapted to perform a film formation process on a substrate in a wafer. The measurement section is adapted to measure a first value related to a shape of the wafer after film formation by the first processing device, and then measure a second value related to a distortion of the wafer based on the first value. The analysis section is adapted to change a film formation condition of the second processing device based on processing information of the first processing device, the second value, and information of the second processing device.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: April 23, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Kazuhiro Segawa
  • Patent number: 10263542
    Abstract: A plate, a transducer, a method for making a transducer, and a method for operating a transducer are disclosed. An embodiment comprises a plate comprising a first material layer comprising a first stress, a second material layer arranged beneath the first material layer, the second material layer comprising a second stress, an opening arranged in the first material layer and the second material layer, and an extension extending into opening, wherein the extension comprises a portion of the first material layer and a portion of the second material layer, and wherein the extension is curved away from a top surface of the plate based on a difference in the first stress and the second stress.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: April 16, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Alfons Dehe
  • Patent number: 10242319
    Abstract: A baseline predictive maintenance method for a target device (TD) and a computer program product thereof are provided. Fresh samples which are generated when the target device produces workpieces just after maintenance are collected, and a new workpiece sample which is generated when the target device produces a new workpiece is collected. A plurality of modeling samples are used to build a TD baseline model in accordance with a conjecturing algorithm, wherein the modeling samples include the new workpiece sample and the fresh samples. A TD healthy baseline value for the new workpiece is computed by the TD baseline model, and a device health index (DHI), a baseline error index (BEI) and baseline individual similarity indices (ISIB) are computed, thereby achieving the goals of fault detection and classification (FDC) and predictive maintenance (PdM).
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: March 26, 2019
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Fan-Tien Cheng, Yao-Sheng Hsieh, Chung-Ren Wang, Saint-Chi Wang
  • Patent number: 10241502
    Abstract: Methods and computer program products for performing automatically determining when to shut down a fabrication tool, such as a semiconductor wafer fabrication tool, are provided herein. The methods include, for example, creating a measurement vector including process parameters of semiconductor wafers, creating a correlation matrix of correlations between measurements of parameters obtained of each wafer, creating autocorrelation matrixes including correlations between measurements of the parameter obtained for pairs of wafers; creating a combined matrix of correlation and autocorrelation matrixes, obtaining a T2 value from the measurement vector and combined matrix, and stopping a semiconductor wafer fabrication tool if the T2 value exceeds a critical value.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: March 26, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Eugene Barash, James Broc Stirton, Richard Good
  • Patent number: 10242849
    Abstract: A system and method of identifying a selected process point in a multi-mode pulsing process includes applying a multi-mode pulsing process to a selected wafer in a plasma process chamber, the multi-mode pulsing process including multiple cycles, each one of the cycles including at least one of multiple, different phases. At least one process output variable is collected for a selected at least one of the phases, during multiple cycles for the selected wafer. An envelope and/or a template of the collected at least one process output variable can be used to identify the selected process point. A first trajectory for the collected process output variable of a previous phase can be compared to a second trajectory of the process output variable of the selected phase. A multivariate analysis statistic of the second trajectory can be calculated and used to identify the selected process point.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: March 26, 2019
    Assignee: Lam Research Corporation
    Inventors: Yassine Kabouzi, Jorge Luque, Andrew D. Bailey, III, Mehmet Derya Tetiker, Ramkumar Subramanian, Yoko Yamaguchi
  • Patent number: 10224482
    Abstract: A method for pixel patterning and pixel position inspection of an organic light-emitting display device includes: forming, on a substrate using a first mask, a thin film layer of a first color corresponding to a first pixel pattern and a first pixel positioning pattern for inspecting a position of a first pixel; shifting, by a determined pitch, the first mask from a position associated with forming the thin film layer of the first color; aligning the shifted first mask with respect to the substrate; and forming, on the substrate using the shifted first mask, a thin film layer of a second color corresponding to the first pixel pattern and another first pixel positioning pattern for inspecting a position of a second pixel.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: March 5, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sangshin Lee, Dongjin Ha, Mingoo Kang, Ohseob Kwon, Sangmin Yi
  • Patent number: 10215718
    Abstract: An electron beam inspection apparatus includes a stage to mount a substrate to be inspected thereon and to be continuously movable, an electron beam column, while the stage continuously moves, to scan the substrate by irradiating the substrate with multi-beams composed of a plurality of first electron beams in a plurality of beam rows, in each of which corresponding beams of the plurality of first electron beams are arranged at a same pitch in a straight line, such that the center of each of irradiation regions irradiated with the multi-beams does not overlap with the other irradiation regions in a movement direction of the stage, and a detector to detect a secondary electron emitted from the substrate due to irradiation of the multi-beams on the substrate.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: February 26, 2019
    Assignee: NuFlare Technology, Inc.
    Inventor: Atsushi Ando