Abstract: A method of producing an integrated circuit having a vertical MOS transistor includes doping a substrate to form a layer adjacent to its surface and forming a lower doped layer serving as the transistor's first source/drain region. The transistor's channel region is formed by doping a central layer above the lower layer. A second source/drain region is formed by doping an upper layer above the central layer. The upper, central and lower layers form a layer sequence having opposed first and second faces. A connecting structure is formed on the first face to electrically connect the channel region and the substrate. The connecting structure laterally adjoins at least the central layer and the lower layer, and extends into the substrate. A gate dielectric and adjacent gate electrode are formed on the second face.

Abstract: The gate region of a field effect transistor comprises at least one through hole wherein a nanoelement is provided which is electrically coupled to the source and the drain. The nanoelement may have the conductance thereof controlled by means of the gate, such that the nanoelement forms a channel region of the field effect transistor.

Abstract: A trench capacitor with an expanded area for use in a memory cell and a method for making the same are provided. The trench capacitor includes a vertical trench formed in a semiconductor, a doping region formed around a low portion of the trench, a collar isolation layer formed on an inner sidewall of an upper portion of the trench, a doped silicon liner layer formed on a surface of the collar isolation layer, wherein the doped silicon liner layer is electrically connected to the doping region, a dielectric layer formed on a surface of the doped silicon liner layer and inner sidewall of the lower portion of the trench, and a doped silicon material formed inside the trench.

Abstract: A GaInP stacked layer structure 1 having a GaAs single crystal substrate 10 having stacked on the surface thereof at least a buffer layer 11, an electron channel layer 12 composed of GaXIn1-XAs (0≦X≦1), a spacer layer 13 composed of GaInP and an electron supply layer 14 composed of GaInP is disclosed. The electron channel layer 12 contains a compositional gradient region imparted with a gradient by increasing the indium composition ratio (1-X) in the direction of the layer thickness increasing toward the junction interface 12b with the electron supply layer 14 side.

Abstract: J-FET having a first semiconductor region (2, 3), which comprises a first contact (7) with a highly doped contact layer (8) serving as a source disposed between two second contacts (9) serving as a gate on its first surface (4). The three contacts (7, 9) are each connected to a respective second semiconductor region (5, 6). The first and second semiconductor regions (2, 3, 5, 6) are of opposite conductivity types. The second semiconductor regions (5) connected to the second contacts (9) extend in the first semiconductor region (2, 3) below the second semiconductor region (6) that is connected to the first contact (7), with the result that the three second semiconductor regions (5, 6) at least partially overlap in a projection onto a horizontal plane and a channel region (11) is formed between the three second semiconductor regions (5, 6) in the first semiconductor region (2, 3).

Abstract: The invention relates to a method for producing a semiconductor component including semiconductor areas of different conductivity types which are alternately positioned in a semiconductor body. The semiconductor areas of different conductivity types extend at least from one first zone to a position near a second zone. Because of variable doping in trenches and in the trench fillings, an electric field is generated which increases from both the first zone and the second zone.

Abstract: A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer is deposited. This ILD layer is etched to form a source region contact, a drain region contact, a first gate electrode contact, and a second gate electrode contact.

Abstract: The invention includes providing gallium nitride material devices having backside vias and methods to form the devices. The devices include a gallium nitride material formed over a substrate, such as silicon. The device also may include one or more non-conducting layers between the substrate and the gallium nitride material which can aid in the deposition of the gallium nitride material. A via is provided which extends from the backside of the device through the non-conducting layer(s) to enable electrical conduction between an electrical contact deposited within the via and, for example, an electrical contact on the topside of the device. Thus, devices of the invention may be vertically conducting. Exemplary devices include laser diodes (LDs), light emitting diodes (LEDs), power rectifier diodes, FETs (e.g., HFETs), Gunn-effect diodes, and varactor diodes, among others.

Abstract: A method for manufacturing a vertical Schottky diode with a guard ring on a lightly-doped N-type silicon carbide layer, comprising the steps of forming a P-type epitaxial layer on the N-type layer; implanting N-type dopants in areas of the P-type epitaxial layer to neutralize in these areas, across the entire thickness of the epitaxial layer, the P-type dopants to form N-type regions, of dopant concentration lower than that of the epitaxial layer, and delimiting a P-type guard ring; forming on the external periphery of the component an insulating layer partially covering the guard ring; and forming a Schottky contact with the N-type region internal to the guard ring.

Abstract: The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon nanotubes, holes having diameters of several nanometers are formed in an insulating layer and are spaced at intervals of several nanometers. Carbon nanotubes are vertically aligned in the nano-sized holes by chemical vapor deposition, electrophoresis or mechanical compression to be used as channels. A gate is formed in the vicinity of the carbon nanotubes using an ordinary semiconductor manufacturing method, and then a source and a drain are formed at lower and upper parts of each of the carbon nanotubes thereby fabricating the vertical nano-sized transistor having an electrically switching characteristic.

Abstract: Openings are formed in a laminate of a polycrystalline silicon film and an LTO film on a channel layer. While the laminate is used as a mask, impurities are implanted into a place in the channel layer which is assigned to a source region. Also, impurities are implanted into another place in the channel layer which is assigned to a portion of a second gate region. A portion of the polycrystalline silicon film which extends from the related opening is thermally oxidated. The LTO film and the oxidated portion of the polycrystalline silicon film are removed. While a remaining portion of the polycrystalline silicon film is used as a mask, impurities are implanted into a place in the channel layer which is assigned to the second gate region. Accordingly, the source region and the second gate region are formed on a self-alignment basis which suppresses a variation in channel length.

Abstract: A method of fabricating an isolated vertical transistor comprising the following steps. A wafer having a first implanted region selected from the group comprising a source region and a drain region is provided. The wafer further includes STI areas on either side of a center transistor area. The wafer is patterned down to the first implanted region to form a vertical pillar within the center transistor area using a patterned hardmask. The vertical pillar having side walls. A pad dielectric layer is formed over the wafer, lining the vertical pillar. A nitride layer is formed over the pad dielectric layer. The structure is patterned and etched through the nitride layer and the pad dielectric layer; and into the wafer within the STI areas to form STI trenches within the wafer. The STI trenches are filled with insulative material to form STIs within STI trenches. The patterned nitride and pad dielectric layers are removed. The patterned hardmask is removed.

Abstract: A grooved channel Schottky contacted MOSFET has asymmetric source and drain regions. The MOSFET includes an undoped silicon substrate with a background doping concentration of less than about 1017 cm−3. A grooved channel is formed in a first surface of the substrate. A first metal silicide material is formed in a first side of the grooved channel, forming a source region, and a second metal silicide material is formed on a second side of the grooved channel, forming a drain region. A metal gate is formed in the grooved channel. The grooved structure allows the off-state current to be reduced to less than 50 pA/&mgr;m. Further, the feature size can be scaled down to 10 nm without strong short-channel effects (DIBL<0.063) and the gate delay (CV/I) is reduced to 2.4 ps.

Abstract: In a trench MOS gate structure of a semiconductor device where trenches (T) are located between an n-type base layer (1) and an n-type source layer (3), a p-type channel layer (12) is formed adjacent to side walls of the trenches, having an even concentration distribution along a depthwise dimension of the trenches. The p-type channel layer enables saturation current to decrease without a raise of ON-resistance of the device, and resultantly a durability against short-circuit can be enhanced. The n-type source layer formed adjacent to the side walls of the trench also further enhances the durability against short-circuit. Providing contacts of the emitter electrode (7) with the n-type source layer at the side walls of the trenches permits a miniaturization of the device and a reduction of the ON-resistance as well.

Abstract: A method of manufacturing an integrated circuit with a channel region containing germanium. The method can provide a double planar gate structure. The gate structure can be provided over lateral sidewalls of channel region. The semiconductor material containing germanium can increase the charge mobility associated with the transistor. An epitaxy process can form the channel region. A silicon-on-insulator can be used.

Abstract: Openings are formed in a laminate of a polycrystalline silicon film and an LTO film on a channel layer. While the laminate is used as a mask, impurities are implanted into a place in the channel layer which is assigned to a source region. Also, impurities are implanted into another place in the channel layer which is assigned to a portion of a second gate region. A portion of the polycrystalline silicon film which extends from the related opening is thermally oxidated. The LTO film and the oxidated portion of the polycrystalline silicon film are removed. While a remaining portion of the polycrystalline silicon film is used as a mask, impurities are implanted into a place in the channel layer which is assigned to the second gate region. Accordingly, the source region and the second gate region are formed on a self-alignment basis which suppresses a variation in channel length.

Abstract: The invention includes providing gallium nitride material devices having backside vias and methods to form the devices. The devices include a gallium nitride material formed over a substrate, such as silicon. The device also may include one or more non-conducting layers between the substrate and the gallium nitride material which can aid in the deposition of the gallium nitride material. A via is provided which extends from the backside of the device through the non-conducting layer(s) to enable electrical conduction between an electrical contact deposited within the via and, for example, an electrical contact on the topside of the device. Thus, devices of the invention may be vertically conducting. Exemplary devices include laser diodes (LDs), light emitting diodes (LEDs), power rectifier diodes, FETs (e.g., HFETs), Gunn-effect diodes, and varactor diodes, among others.

Abstract: A semiconductor device and a method for forming the semiconductor device, include forming a mandrel, forming spacer wordline conductors on sidewalls of the mandrel, separating, by using a trim mask, adjacent spacer wordline conductors, and providing a contact area to contact alternating ones of pairs of the spacer wordline conductors.

Abstract: A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate.

Abstract: A field effect transistor has a preselected build up resistance with respect to an I-V characteristic of the transistor. In this event, a first GaAs layer is formed on a GaAs substrate. Further, an AlGaAs layer is formed on the first GaAs layer and has a predetermined impurity concentration and a preselected Al composition ratio. Moreover, a gate electrode is placed on the AlGaAs layer to form a schottky contact with the AlGaAs layer. In addition, a second GaAs layers are arranged on both sides of the gate electrode via a recess and are formed on said AlGaAs layer. Finally, source and drain electrodes are formed on the second GaAs layers. With such a structure, the Al composition ratio is determined within a preselected range defined by a relationship between the impurity concentration and the build up resistance.

Abstract: A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer sited. This ILD layer is etched to form a source region contact, a drain region contact, a first gate electrode contact, and a second gate electrode contact.

Abstract: There is disclosed a field effect transistor having a two-stage recess structure formed upon an InP substrate and showing stable device characteristics and a low contact resistance. The FET is manufactured as follows. Upon an InP substrate 101, a channel layer 103, electron supply layers 104 and 105, an undoped InAlAs Schottky layer 106, an n-type InAlAs first cap layer 107 and an n-type InGaAs second cap layer 108 are formed in succession, following which a second recess opening 111 is formed by etching from the surface of the second cap layer to just the surface of said Schottky layer or further to a level to remove a part of the Schottky layer. A first recess opening 110 is formed by side-etching the second cap layer using an etchant of which etching selectively of InGaAs over InAlAs is 30 or more.

Abstract: A high voltage microwave field effect transistor (FET) and method for its manufacture. The FET (10) includes a channel layer (18) formed of compressively strained GaInP. Carrier confinement layers (16), (20) formed of tensile strained (AlGa)InP are formed both above (20) and below (16) the channel layer (20) to confine the carriers to the channel layer (20) and to provide a high breakdown voltage.

Abstract: A method of fabricating a vertical transistor of a memory cell is disclosed. According to this method, a semiconductor substrate is first provided. A pad layer is formed over the substrate. Then, a deep trench is formed in the substrate. In the deep trench, a trench capacitor is formed, a collar oxide layer is then formed on the sidewalls above the trench capacitor. A first conductive layer is formed above the trench capacitor. A second conductive layer is formed to fill the deep trench. The pad layer, the substrate, the first and the second conductive layers and the collar oxide layer are patterned. A first insulating layer is deposited to form the Shallow Trench Isolation. Both sides of the Shallow Trench Isolation and a portion of the second conductive layer are removed to form a buried strap and an opening. The pad layer is removed. A second insulating layer is formed over the substrate and the buried strap, and is removed after forming a well. A third insulating layer is formed on the substrate.

Abstract: A manufacturable GaAs VFET process includes providing a doped GaAs substrate with a lightly doped first epitaxial layer thereon and a heavily doped second epitaxial layer positioned on the first epitaxial layer. A temperature tolerant conductive layer is positioned on the second epitaxial layer and patterned to define a plurality of elongated, spaced apart source areas. Using the patterned conductive layer, a plurality of gate trenches are etched into the first epitaxial layer adjacent the source areas. The bottoms of the gate trenches are implanted and activated to form gate areas. A gate contact is deposited in communication with the implanted gate areas, a source contact is deposited in communication with the patterned conductive layer overlying the source areas, and a drain contact is deposited on the rear surface of the substrate.

Abstract: The method includes patterning a first polysilicon layer on a substrate. A first dielectric having a first via hole is defined over the substrate. A second polysilicon layer is formed along the surface of the first dielectric layer and refilled into the first via hole. Then, an etching is used to etch the layer. A residual portion of the layer is located at the lower portion of the first via hole. An undoped polysilicon is then patterned on the first dielectric layer and along the surface of the first via hole. An isolation structure is then refilled into the first via hole. An oxide layer is formed on the first polysilicon, the first dielectric layer and the upper surface of isolation structure to act as the gate oxide of the TFT. Then, the oxide and the first dielectric layer are etched to define a second via hole. A further polysilicon layer is pattern on the first dielectric layer and refilled into the second via hole for defining the gate.

Abstract: A lateral gate, vertical drift region transistor including a drain positioned on one surface of a substrate and a doped structure having a buried region therein positioned on the other surface of the substrate. The buried region defining a drift region in the doped structure extending vertically from the substrate and further defining a doped region in communication with the drift region and adjacent the surface of the doped structure. A source positioned on the doped structure in communication with the doped region and an implant region positioned in the doped region adjacent the surface and in communication with the source and buried region. An insulating layer positioned on the doped structure with a metal gate positioned on the insulating layer so as to define an inversion region in the implant region extending laterally adjacent the control terminal and communicating with the drift region and the source.

Abstract: A method for forming a trench transistor structure begins by forming a buried layers (12 and 16) and a doped well (22) in a substrate (10) via epitaxial growth processing. A trench region (24) is then etched into the substrate (10) to expose a the layer (12). A conductive sidewall spacer (28) is formed within the trench (24) as a gate electrode. The spacer (28) gates a first transistor (12, 28, 32) located adjacent a first half of the trench (24) and a second transistor (12, 28, 34) located adjacent a second half of the trench (24). Region (12) is a common electrode wherein the channel regions of both the first and second transistor are coupled in a serial manner through the region (12).

Abstract: A method for forming a semiconductor structure on an active area mesa with minimal loss of field oxide deposited in isolation trenches adjacent the mesa. The trench insulating material is protected by an etch barrier layer having at least a partial resistance to etchants used in further device processing steps. The barrier layer may also be deposited over the surface of the substrate to protect it from damage during device processing. The barrier layer may be removed by an etchant having a selectivity for the barrier layer over that of the surrounding device elements. Final processing of the device may be completed once the barrier layer is removed.

Abstract: This is a method of fabricating a lateral gate, vertical drift region transistor including a semiconductor substrate having a drain on the reverse surface. A doped semiconductor layer is formed on the substrate and a high resistivity region is formed adjacent the surface of the doped layer so as to define a vertical drift region in the doped layer. A lateral channel is formed on the high resistivity region and the doped layer so as to communicate with the vertical drift region. A source is positioned on the lateral channel spaced laterally from the vertical drift region and a gate is positioned on the lateral channel between the drift region and the source.

Abstract: A method for forming a diode for use within an integrated circuit, and a diode formed through the method. There is first provided a semiconductor substrate. There is then formed over the semiconductor substrate a dielectric layer. There is then formed upon the dielectric layer a first polysilicon layer, where the first polysilicon layer has a first dopant polarity and a first dopant concentration. There is then formed at least in part overlapping and at least in part in contact with the first polysilicon layer a second polysilicon layer. The second polysilicon layer has a second dopant polarity and a second dopant concentration, where the second dopant polarity is opposite to the first dopant polarity. A first portion of the second polysilicon layer overlapping and in contact within a first portion of the first polysilicon layer forms a junction diode.