Having Schottky Gate (e.g., Mesfet, Hemt, Etc.) Patents (Class 438/167)
  • Patent number: 10283484
    Abstract: A mask is formed over a first conductive portion of a conductive layer to expose a second conductive portion of the conductive layer. An electrolytic process is performed to remove conductive material from a first region and a second region of the second conductive portion. The second region is aligned with the mask relative to an electric field applied by the electrolytic process. The second region separates the first region of the second conductive portion from the first conductive portion. The electrolytic process is concentrated relative to the second region such that removal occurs at a relatively higher rate in the second region than in the first region.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: May 7, 2019
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Arkalgud R. Sitaram
  • Patent number: 10176993
    Abstract: A third semiconductor layer (105) including a third nitride semiconductor is provided between an electrode (110) and a second semiconductor layer (104) including a second nitride semiconductor. The band gap of the second nitride semiconductor is set such that the carrier movement between a first semiconductor layer (103) and the third semiconductor layer (105) via the second semiconductor layer (104) is rate-determined by a diffusion process. The thickness of the second semiconductor layer (104) is set such that the carrier movement between the first semiconductor layer (103) and the third semiconductor layer (105) via the second semiconductor layer (104) is rate-determined by the diffusion process. The carrier movement between the first semiconductor layer (103) and the third semiconductor layer (105) via the second semiconductor layer (104) is rate-determined by a field emission process.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: January 8, 2019
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Dariush Zadeh, Shinichi Tanabe, Noriyuki Watanabe
  • Patent number: 10170563
    Abstract: This invention discloses a gallium nitride based semiconductor power device disposed in a semiconductor substrate. The power device comprises a termination area disposed at a peripheral area of the semiconductor power device comprises a termination structure having at least a guard ring disposed in a trench filled with doped gallium-based epitaxial layer therein.
    Type: Grant
    Filed: February 9, 2013
    Date of Patent: January 1, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Tinggang Zhu
  • Patent number: 10068976
    Abstract: An enhancement mode field-effect transistor (E-FET) for high static performance is provided. A composite barrier layer comprises a lower barrier layer and an upper barrier layer. The upper barrier layer is arranged over the lower barrier layer and has a different polarization than the lower barrier layer. Further, the composite barrier layer comprises a gate opening. A channel layer is arranged under the composite barrier layer, such that a heterojunction is defined at an interface between the channel layer and the composite barrier layer. A gate dielectric layer is arranged over the composite barrier layer and within the gate opening. A gate electrode is arranged over the gate dielectric layer. A method for manufacturing the E-FET is also provided.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: September 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ling Yeh, Man-Ho Kwan, Kuei-Ming Chen, Jiun-Lei Jerry Yu, Chun Lin Tsai
  • Patent number: 9954106
    Abstract: A method of forming a semiconductor structure in which a III-V compound semiconductor channel fin portion is formed on a dielectric material is provided. The method includes forming a III-V material stack on a surface of a bulk semiconductor substrate. Patterning of the III-V material stack is then employed to provide a pre-fin structure that is located between, and in contact with, pre-pad structures. The pre-pad structures are used as an anchoring agent when a III-V compound semiconductor channel layer portion of the III-V material stack and of the pre-fin structure is suspended by removing a topmost III-V compound semiconductor buffer layer portion of the material stack from the pre-fin structure. A dielectric material is then formed within the gap provided by the suspending step and thereafter a fin cut process is employed.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Hemanth Jagannathan, Alexander Reznicek
  • Patent number: 9831310
    Abstract: A compound semiconductor device includes: a compound semiconductor multilayer structure including a first buffer layer composed of AlN; and a second buffer layer composed of AlGaN and formed above the first buffer layer, wherein the second buffer layer contains carbon, and wherein the concentration of carbon in the second buffer layer increases with increasing distance from a lower surface of the second buffer layer toward an upper surface of the second buffer layer.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: November 28, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Junji Kotani, Norikazu Nakamura
  • Patent number: 9564330
    Abstract: The present disclosure relates to an enhancement mode MISFET device. In some embodiments, the MISFET device has an electron supply layer located on top of a layer of semiconductor material. A multi-dielectric layer, having two or more stacked dielectric materials sharing an interface having negative fixed charges, is disposed above the electron supply layer. A metal gate structure is disposed above the multi-dielectric layer, such that the metal gate structure is separated from the electron supply layer by the multi-dielectric layer. The multi-dielectric layer provides fixed charges at interfaces between the separate dielectric materials, which cause the transistor device to achieve a normally off disposition.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Chin Chiu, Hsing-Lien Lin, Cheng-Yuan Tsai
  • Patent number: 9378949
    Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: June 28, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: David F. Brown, Keisuke Shinohara, Miroslav Micovic, Andrea Corrion
  • Patent number: 9356122
    Abstract: The present invention features methods for forming a field effect transistor on a semiconductor substrate having gate, source and drain regions, with the gate region having a lateral gate channel. A plurality of spaced-apart trenches or through semiconductor vias (TSV) each having an electrically conductive plug formed therein in electrical communication with the gate, source and drain regions are configured to lower the resistance of the bottom source. A contact trench is formed adjacent to the source region and shorts the source region and a body region. A source contact is in electrical communication with the source region; and a drain contact in electrical communication with the drain region, with the source and drain contacts being disposed on opposite sides of the lateral gate channel.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: May 31, 2016
    Assignee: Alpha & Omega Semiconductor Incorporatedated
    Inventor: Mallikarjunaswamy Shekar
  • Patent number: 9305858
    Abstract: An array of through-silicon vias (TSVs) are formed in a silicone substrate. The vias can be tapered such that the diameter of the via at the surface of the substrate is larger than the diameter of the via at its bottom, with the diameter varying continuously along its depth. After the via is formed, it is seeded with a thin layer of nanocrystalline diamond (NCD) particles, and a NCD film is grown on the bottom and along the sidewalls of the via. The presence of the diamond-filled vias provides improved thermal management to semiconductor devices formed on the silicon substrate.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: April 5, 2016
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Karl D. Hobart, Marko J. Tadjer, Tatyana I. Feygelson, Bradford B. Pate, Travis J. Anderson
  • Patent number: 9231077
    Abstract: A method of forming a semiconductor device includes forming a first gate layer over a substrate in the NVM region and the logic region; forming an opening in the first gate layer in the NVM region; forming a charge storage layer in the opening; forming a control gate over the charge storage layer in the opening; patterning the first gate layer to form a first patterned gate layer portion over the substrate in the logic region and to form a second patterned gate layer portion over the substrate in the NVM region, wherein the second patterned gate layer portion is adjacent the control gate; forming a dielectric layer over the substrate around the first patterned gate layer portion and around the second patterned gate layer portion and the control gate, and replacing the first patterned gate layer portion with a logic gate comprising metal.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: January 5, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Mehul D. Shroff, Mark D. Hall
  • Patent number: 9214524
    Abstract: A semiconductor device includes a semiconductor substrate, a gate insulating film formed over the semiconductor substrate, a gate electrode formed on the gate insulating film, a first semiconductor layer which is embedded into a portion on both sides of the gate electrode in the semiconductor substrate, and which includes Si and a 4B group element other than Si, and a second semiconductor layer which is embedded into the portion on both sides of the gate electrode in the semiconductor substrate, so as to be superposed on the first semiconductor layer, and which includes Si and a 4B group element other than Si, wherein the gate electrode is more separated from an end of the first semiconductor layer than from an end of the second semiconductor layer.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: December 15, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Naoyoshi Tamura
  • Patent number: 9160326
    Abstract: Providing gate protection to a group III-semiconductor device by delivering gate overdrive immunity is described herein. The gate protection can be achieved by embedding a gate-voltage-controlling second transistor to the gate electrode of a first transistor. In other words, a first gate electrode of the first semiconductor device is in series with a second source electrode of the second semiconductor device, and a second gate electrode of the second semiconductor device is connected to the second source electrode and the first gate electrode.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: October 13, 2015
    Assignee: The Hong Kong University of Science and Technology
    Inventors: Jing Chen, Man Ho Kwan
  • Patent number: 9142636
    Abstract: A III-Nitride field-effect transistor, specifically a HEMT, comprises a channel layer, a barrier layer on the channel layer, an etch stop layer on the cap layer, a dielectric layer on the etch stop layer, a gate recess that extends to the barrier layer, and a gate contact in the gate recess. The etch stop layer may reduce damage associated with forming the recessed gate by not exposing the barrier layer to dry etching. The etch stop layer in the recess is removed and the remaining etch stop layer serves as a passivation layer.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: September 22, 2015
    Assignee: Cree, Inc.
    Inventors: Scott T. Sheppard, Andrew K. Mackenzie, Scott T. Allen, Richard P. Smith
  • Patent number: 9142646
    Abstract: An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: September 22, 2015
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Ferruccio Frisina, Angelo Magri′, Mario Giuseppe Saggio
  • Patent number: 9129827
    Abstract: Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: September 8, 2015
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Van H. Le, Glenn A. Glass, Kelin J. Kuhn, Stephen M. Cea
  • Patent number: 9087925
    Abstract: Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: July 21, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xuefeng Liu, Robert M. Rassel, Steven H. Voldman
  • Patent number: 9059193
    Abstract: A silicon carbide semiconductor element, including: i) an n-type silicon carbide substrate doped with a dopant, such as nitrogen, at a concentration C, wherein the substrate has a lattice constant that decreases with doping; ii) an n-type silicon carbide epitaxially-grown layer doped with the dopant, but at a smaller concentration than the substrate; and iii) an n-type buffer layer doped with the dopant, and arranged between the substrate and the epitaxially-grown layer, wherein the buffer layer has a multilayer structure in which two or more layers having the same thickness are laminated, and is configured such that, based on a number of layers (N) in the multilayer structure, a doping concentration of a K-th layer from a silicon carbide epitaxially-grown layer side is C·K/(N+1).
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: June 16, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichi Ohtsuka, Kenichi Kuroda, Hiroshi Watanabe, Naoki Yutani, Hiroaki Sumitani
  • Patent number: 9041063
    Abstract: High electron mobility transistors (HEMTs) and methods of manufacturing the same. A HEMT may include a source electrode, a gate electrode, a drain electrode, a channel formation layer including at least a 2-dimensional electron gas (2DEG) channel, a channel supplying layer for forming the 2DEG channel in the channel formation layer, a portion of the channel supplying layer including a first oxygen treated region. The channel supplying layer may include a second oxygen treated region that extends from the first oxygen treated region towards the drain electrode, and the depth and concentration of oxygen of the second oxygen treated region may be less than those of the first oxygen treated region.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG ELECTRONCS CO., LTD.
    Inventor: In-jun Hwang
  • Patent number: 9029986
    Abstract: Semiconductor devices are provided with dual passivation layers. A semiconductor layer is formed on a substrate and covered by a first passivation layer (PL-1). PL-1 and part of the semiconductor layer are etched to form a device mesa. A second passivation layer (PL-2) is formed over PL-1 and exposed edges of the mesa. Vias are etched through PL-1 and PL-2 to the semiconductor layer where source, drain and gate are to be formed. Conductors are applied in the vias for ohmic contacts for the source-drain and a Schottky contact for the gate. Interconnections over the edges of the mesa couple other circuit elements. PL-1 avoids adverse surface states near the gate and PL-2 insulates edges of the mesa from overlying interconnections to avoid leakage currents. An opaque alignment mark is desirably formed at the same time as the device to facilitate alignment when using transparent semiconductors.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: May 12, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bruce M. Green, Haldane S. Henry
  • Patent number: 9018635
    Abstract: An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics S.R.L.
    Inventors: Ferruccio Frisina, Angelo Magri', Mario Giuseppe Saggio
  • Patent number: 9006053
    Abstract: Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)<TBCD is created into side walls of TCT and beneath SCD. An embedded Shannon implant region (ESIR) is created into sub-contact trench zone (SCTZ) beneath TCT floor. A metal layer is formed in contact with ESIR, body and source region. The metal layer also fills TCT and covers dielectric region thus completing the MOSFET/SKY with only one-time etching of its TCT.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: April 14, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Ji Pan, Daniel Ng, Sung-Shan Tai, Anup Bhalla
  • Patent number: 8999780
    Abstract: A HEMT device has a substrate; a buffer layer disposed above the substrate; a carrier supplying layer disposed above the buffer layer; a gate element penetrating the carrier supplying layer; and a drain element disposed on the carrier supplying layer. The carrier supplying layer has a non-uniform thickness between the gate element and the drain element, the carrier supplying layer having a relatively greater thickness adjacent the drain element and a relatively thinner thickness adjacent the gate element. A non-uniform two-dimensional electron gas conduction channel is formed in the carrier supplying layer, the two-dimensional electron gas conduction channel having a non-uniform profile between the gate and drain elements.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: April 7, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Sameh G. Khalil, Karim S. Boutros
  • Patent number: 9000496
    Abstract: A FET includes elongated, mutually parallel source regions separated by gate and drain regions. Conductive bridges extend over the gate and drain regions and not in electrical contact therewith to electrically and thermally interconnect the sources. A layer of dielectric is applied over surfaces, and an aperture is defined over the bridges. A thick layer of metal is applied over and in thermal and electrical contact with the bridges. Electrical and thermal connections can be made to the thick metal.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: April 7, 2015
    Assignee: Lockheed Martin Corporation
    Inventors: Peter N. Bronecke, Raymond Albert Fillion, Joshua Isaac Wright, Jesse Berkley Tucker, Laura Jean Meyer
  • Patent number: 8981384
    Abstract: There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes a substrate having a main surface, and a silicon carbide layer. The silicon carbide layer is formed on the main surface of the substrate. The silicon carbide layer includes a side surface as an end surface inclined relative to the main surface. The side surface substantially includes one of a {03-3-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: March 17, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takeyoshi Masuda
  • Patent number: 8975664
    Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device may include a buffer layer disposed on a substrate, the buffer layer including gallium (Ga) and nitrogen (N), a barrier layer disposed on the buffer layer, the barrier layer including aluminum (Al) and nitrogen (N), a regrown structure disposed in and epitaxially coupled with the barrier layer, the regrown structure including nitrogen (N) and at least one of aluminum (Al) or gallium (Ga) and being epitaxially deposited at a temperature less than or equal to 600° C., and a gate terminal disposed in the barrier layer, wherein the regrown structure is disposed between the gate terminal and the buffer layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: March 10, 2015
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Paul A. Saunier, Edward A. Beam, III
  • Patent number: 8969919
    Abstract: A field-effect transistor includes a carrier transport layer made of nitride semiconductor, a gate electrode having first and second sidewall surfaces on first and second sides, respectively, an insulating film formed directly on the gate electrode to cover at least one of the first and second sidewall surfaces, first and second ohmic electrodes formed on the first and second sides, respectively, a passivation film including a first portion extending from the first ohmic electrode toward the gate electrode to cover a surface area between the first ohmic electrode and the gate electrode and a second portion extending from the second ohmic electrode toward the gate electrode to cover a surface area between the second ohmic electrode and the gate electrode, wherein the insulating film is in direct contact with at least the first and second passivation film portions, and has a composition different from that of the passivation film.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: March 3, 2015
    Assignee: Fujitsu Limited
    Inventors: Toshihiro Ohki, Naoya Okamoto
  • Patent number: 8951901
    Abstract: In sophisticated semiconductor devices, the encapsulation of sensitive gate materials, such as a high-k dielectric material and a metal-containing electrode material, which are provided in an early manufacturing stage may be achieved by forming an undercut gate configuration. To this end, a wet chemical etch sequence is applied after the basic patterning of the gate layer stack, wherein at least ozone-based and hydrofluoric acid-based process steps are performed in an alternating manner, thereby achieving a substantially self-limiting removal behavior.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: February 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Berthold Reimer, Falk Graetsch
  • Patent number: 8946012
    Abstract: A method of forming a semiconductor structure having a substrate is disclosed. The semiconductor structure includes a first layer formed in contact with the substrate. The first layer made of a first III-V semiconductor material selected from GaN, GaAs and InP. A second layer is formed on the first layer. The second layer made of a second III-V semiconductor material selected from AlGaN, AlGaAs and AlInP. An interface is between the first layer and the second layer forms a carrier channel. An insulating layer is formed on the second layer. Portions of the insulating layer and the second layer are removed to expose a top surface of the first layer. A metal feature is formed in contact with the carrier channel and the metal feature is annealed to form a corresponding intermetallic compound.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chih Chen, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chun-Wei Hsu, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 8941093
    Abstract: A first electrode, an intrinsic first compound semiconductor layer over the first electrode, a second compound semiconductor layer whose band gap is smaller than that of the first compound semiconductor layer on the first compound semiconductor layer, and a second electrode over the second compound semiconductor layer are provided.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: January 27, 2015
    Assignee: Fujitsu Limited
    Inventor: Tadahiro Imada
  • Patent number: 8940593
    Abstract: An enhancement-mode GaN MOSFET with a low leakage current and an improved reliability is formed by utilizing a SiO2/Si3N4 gate insulation layer on an AlGaN (or InAlGaN) barrier layer. The Si3N4 portion of the SiO2/Si3N4 gate insulation layer significantly reduces the formation of interface states at the junction between the gate insulation layer and the barrier layer, while the SiO2 portion of the SiO2/Si3N4 gate insulation layer significantly reduces the leakage current.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: January 27, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Jamal Ramdani
  • Patent number: 8941118
    Abstract: A III-nitride transistor includes a III-nitride channel layer, a barrier layer over the channel layer, the barrier layer having a thickness of 1 to 10 nanometers, a dielectric layer on top of the barrier layer, a source electrode contacting the channel layer, a drain electrode contacting the channel layer, a gate trench extending through the dielectric layer and barrier layer and having a bottom located within the channel layer, a gate insulator lining the gate trench and extending over the dielectric layer, and a gate electrode in the gate trench and extending partially toward the source and the drain electrodes to form an integrated gate field-plate, wherein a distance between an interface of the channel layer and the barrier layer and the bottom of the gate trench is greater than 0 nm and less than or equal to 5 nm.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: January 27, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Rongming Chu, David F. Brown, Adam J. Williams
  • Patent number: 8933489
    Abstract: An AlGaN/GaN.HEMT includes, a compound semiconductor lamination structure; a p-type semiconductor layer formed on the compound semiconductor lamination structure; and a gate electrode formed on the p-type semiconductor layer, in which Mg being an inert element of p-GaN is introduced into both sides of the gate electrode at the p-type semiconductor layer, and introduced portions of Mg are inactivated.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: January 13, 2015
    Assignee: Transphorm Japan, Inc.
    Inventor: Toshihide Kikkawa
  • Patent number: 8927354
    Abstract: An apparatus in one example comprises an antimonide-based compound semiconductor (ABCS) stack, an upper barrier layer formed on the ABCS stack, and a gate stack formed on the upper barrier layer. The upper barrier layer comprises indium, aluminum, and arsenic. The gate stack comprises a base layer of titanium and tungsten formed on the upper barrier layer.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: January 6, 2015
    Assignees: Northrop Grumman Systems Corporation, The United States of America As Represented by the Secretary of The Navy
    Inventors: Yeong-Chang Chou, Jay Crawford, Jane Lee, Jeffrey Ming-Jer Yang, John Bradley Boos, Nicolas Alexandrou Papanicolaou
  • Patent number: 8916459
    Abstract: A compound semiconductor device having mesa-shaped element region, and excellent characteristics are provided. The compound semiconductor device has: an InP substrate; an epitaxial lamination mesa formed above the InP substrate and including a channel layer, a carrier supply layer above the channel layer and a contact cap layer above the carrier supply layer; ohmic source electrode and drain electrode formed on the cap layer; a recess formed by removing the cap layer between the source and drain electrodes, and exposing the carrier supply layer; an insulating film formed on the cap layer and retracted from an edge of the cap layer away from the recess; a gate electrode extending from the carrier supply layer in the recess to outside of the mesa; and air gap formed by removing side portion of the channel layer facing the gate electrode outside the mesa.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: December 23, 2014
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Takahashi, Kozo Makiyama
  • Patent number: 8916437
    Abstract: A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel, and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: December 23, 2014
    Assignee: Acorn Technologies, Inc.
    Inventors: Daniel E. Grupp, Daniel J. Connelly
  • Patent number: 8912573
    Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: December 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yen Chou, Sheng-De Liu, Fu-Chih Yang, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 8895421
    Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: November 25, 2014
    Assignee: Transphorm Inc.
    Inventors: Primit Parikh, Yuvaraj Dora, Yifeng Wu, Umesh Mishra, Nicholas Fichtenbaum, Rakesh K. Lal
  • Patent number: 8890208
    Abstract: Provided is an epitaxial substrate capable of manufacturing a HEMT device that has excellent two-dimensional electron gas characteristics and is capable of performing normally-off operation. A channel layer is formed of a first group III nitride represented by Inx1Aly1Gaz1N (x1+y1+z1=1) so as to have a composition in a range determined by x1=0 and 0?y1?0.3. A barrier layer is formed of a second group III nitride represented by Inx2Aly2Gaz2N (x2+y2+z2=1) so as to have a composition, in a ternary phase diagram with InN, AlN and GaN being vertices, in a range surrounded by four straight lines determined in accordance with the composition (AlN molar fraction) of the first group III nitride and to have a thickness of 5 nm or less.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: November 18, 2014
    Assignee: NGK Insulators, Ltd.
    Inventors: Makoto Miyoshi, Yoshitaka Kuraoka, Shigeaki Sumiya, Mitsuhiro Tanaka
  • Patent number: 8890212
    Abstract: According to example embodiments, a normally-off high electron mobility transistor (HEMT) includes: a channel layer having a first nitride semiconductor, a channel supply layer on the channel layer, a source electrode and a drain electrode at sides of the channel supply layer, a depletion-forming layer on the channel supply layer, a gate insulating layer on the depletion-forming layer, and a gate electrode on the gate insulation layer. The channel supply layer includes a second nitride semiconductor and is configured to induce a two-dimensional electron gas (2DEG) in the channel layer. The depletion-forming layer is configured has at least two thicknesses and is configured to form a depletion region in at least a partial region of the 2DEG. The gate electrode contacts the depletion-forming layer.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: November 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-chul Jeon, Young-hwan Park, Jae-joon Oh, Kyoung-yeon Kim, Joon-yong Kim, Ki-yeol Park, Jai-kwang Shin, Sun-kyu Hwang
  • Patent number: 8883580
    Abstract: Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: November 11, 2014
    Assignee: Vishay-Siliconix
    Inventors: Deva N. Pattanayak, Kyle Terrill, Sharon Shi, Misha Lee, Yuming Bai, Kam Lui, Kuo-in Chen
  • Patent number: 8872226
    Abstract: Provided is an epitaxial substrate having excellent two-dimensional electron gas characteristics and reduced internal stress due to strains. A channel layer is formed of a first group III nitride represented by Inx1Aly1Gaz1N (x1+y1+z1=1) so as to have a composition in a range determined by x1=0 and 0?y1?0.3. A barrier layer is formed of a second group III nitride represented by Inx2Aly2Gaz2N (x2+y2+z2=1) so as to have a composition, in a ternary phase diagram with InN, AlN and GaN being vertices, in a range surrounded by five straight lines determined in accordance with the composition (AlN molar fraction) of the first group III nitride.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: October 28, 2014
    Assignee: NGK Insulators, Ltd.
    Inventors: Makoto Miyoshi, Yoshitaka Kuraoka, Shigeaki Sumiya, Mitsuhiro Tanaka
  • Patent number: 8872235
    Abstract: An embodiment of a transistor device includes a compound semiconductor material on a semiconductor carrier and a source region and a drain region spaced apart from each other in the compound semiconductor material with a channel region interposed between the source and drain regions. A Schottky diode is integrated with the semiconductor carrier, and contacts extend from the source and drain regions through the compound semiconductor material. The contacts are in electrical contact with the Schottky diode so that the Schottky diode is connected in parallel between the source and drain regions. In another embodiment, the integrated Schottky diode is formed by a region of doped amorphous silicon or doped polycrystalline silicon disposed in a trench structure on the drain side of the device.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: October 28, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Clemens Ostermaier, Oliver Häberlen
  • Patent number: 8866193
    Abstract: According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group semiconductor device may be a III-nitride high electron mobility transistor (HEMT).
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: October 21, 2014
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8859354
    Abstract: A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate, and forming a quantum well layer on the semiconductor substrate. The method also includes forming a potential energy barrier layer on the semiconductor substrate, and forming an isolation structure to isolate different transistor regions. Further, the method includes patterning the transistor region to form trenches by removing portions of the quantum well layer and the potential energy barrier layer corresponding to a source region and a drain region, and filling trenches with a semiconductor material to form a source and a drain. Further, the method also includes forming a gate structure on a portion of the quantum well layer and the potential energy barrier layer corresponding to a gate region.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Manufacturing International Corp
    Inventor: Deyuan Xiao
  • Patent number: 8860087
    Abstract: The present invention relates to a nitride semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a nitride semiconductor device including: a nitride semiconductor layer having a 2DEG channel; a source electrode in ohmic contact with the nitride semiconductor layer; a drain electrode in ohmic contact with the nitride semiconductor layer; a plurality of p-type nitride semiconductor segments formed on the nitride semiconductor layer and each formed lengthways from a first sidewall thereof, which is spaced apart from the source electrode, to a drain side; and a gate electrode formed to be close to the source electrode and in contact with the nitride semiconductor layer between the plurality of p-type semiconductor segments and portions of the p-type semiconductor segments extending in the direction of a source-side sidewall of the gate electrode aligned with the first sidewalls of the p-type nitride semiconductor segments is provided.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: October 14, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Hwan Park, Woo Chul Jeon, Ki Yeol Park, Seok Yoon Hong
  • Publication number: 20140295628
    Abstract: A MOS P-N junction Schottky diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. An ohmic contact and a Schottky contact are formed at different sides of the gate structure. The method for manufacturing such diode device includes several ion-implanting steps to form several doped sub-regions with different implantation depths to constitute the doped regions. The formed MOS P-N junction Schottky diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance.
    Type: Application
    Filed: June 19, 2014
    Publication date: October 2, 2014
    Inventor: Hung-Hsin Kuo
  • Patent number: 8841709
    Abstract: A disclosed semiconductor device includes a semiconductor deposition layer formed over an insulation structure and above a substrate. The device includes a gate formed over a contact region between first and second implant regions in the semiconductor deposition layer. The first and second implant regions both have a first conductivity type, and the gate has a second conductivity type. The device may further include a second gate formed beneath the semiconductor deposition layer.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: September 23, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Wing Chor Chan, Chih Min Hu, Jeng Gong
  • Patent number: 8816408
    Abstract: A compound semiconductor device includes a compound semiconductor laminated structure; a source electrode, a drain electrode, and a gate electrode formed over the compound semiconductor laminated structure; a first protective film formed over the compound semiconductor laminated structure between the source electrode and the gate electrode and including silicon; and a second protective film formed over the compound semiconductor laminated structure between the drain electrode and the gate electrode and including more silicon than the first protective film.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: August 26, 2014
    Assignee: Fujitsu Limited
    Inventors: Kozo Makiyama, Toshihide Kikkawa
  • Patent number: 8815666
    Abstract: Provided is a power device. The power device may include a two-dimensional electron gas (2-DEG) layer in a portion corresponding to a gate electrode pattern since a second nitride layer is further formed on a lower portion of the gate electrode pattern after a first nitride layer is formed and thus, may be capable of performing a normally-OFF operation. Accordingly, the power device may adjust generation of the 2-DEG layer based on a voltage of a gate, and may reduce power consumption. The power device may regrow only the portion corresponding to the gate electrode pattern or may etch a portion excluding the portion corresponding to the gate electrode pattern and thus, a recess process may be omissible, a reproducibility of the power device may be secured, and a manufacturing process may be simplified.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae Hoon Lee