Abstract: After an n-type AlGaN barrier layer (3) is formed over a substrate (1), an n-type GaN contact layer (4) is formed over the n-type AlGaN barrier layer (3). Next, the n-type GaN contact layer (4) is wet-etched with using an etching solution containing an organic alkali agent and an oxidizer while the n-type GaN contact layer (4) is irradiated with an ultraviolet illumination.

Abstract: The compound semiconductor device comprises an i-GaN buffer layer 12 formed on an SiC substrate 10; an n-AlGaN electron supplying layer 16 formed on the i-GaN buffer layer 12; an n-GaN cap layer 18 formed on the n-AlGaN electron supplying layer 16; a source electrode 20 and a drain electrode 22 formed on the n-GaN cap layer 18; a gate electrode 26 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; a first protection layer 24 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; and a second protection layer 30 buried in an opening 28 formed in the first protection layer 24 between the gate electrode 26 and the drain electrode 22 down to the n-GaN cap layer 18 and formed of an insulation film different from the first protection layer.

Abstract: There is provided a manufacturing method of a semiconductor apparatus, including forming an InGaP layer on a substrate, forming a gate electrode having a Ti layer and an Au layer by vapor deposition on an upper surface of the InGaP layer, further forming a GaAs layer on the upper surface of the InGaP layer in a region different from a region in which the gate electrode is formed, and further forming a source electrode and a drain electrode on an upper surface of the GaAs layer. When the gate electrode having the Ti and Au layers is formed on the upper surface of the InGaP layer, the Ti and Au layers are formed with a substrate temperature being set equal to or lower than 180° C.

Abstract: A FET includes a nitride semiconductor in which leak current is reduced and breakdown voltage is improved. The FET is formed from a substrate, a buffer layer made of a nitride semiconductor, a first semiconductor layer made of a nitride semiconductor, and a second semiconductor layer made of a nitride semiconductor, wherein at least the buffer layer and the first semiconductor layer include a p-type dopant. The concentration of the p-type dopant is higher in the buffer layer than that in the first semiconductor layer, and the concentration of the p-type dopant is higher in the first semiconductor layer than that in the second semiconductor layer.

Abstract: Enhanced hole mobility p-type JFET and fabrication methods. A p-type junction field effect transistor including a substrate of n-type, a source region and a drain region formed in the substrate; wherein the source region and the drain region are p-type doped and at least one of the source region and the drain region is formed with silicon-germanium compound (Si1-xGex), a p-type channel disposed between the source and the drain in the substrate; wherein compressive stress is induced in the p-type channel substantially along a channel length by the Si1-xGex, and an n-type gate region within the p-type channel. The n-type gate region is electrically coupled to a gate contact that is operable to modulate a depletion width of the p-type channel.

Abstract: A semiconductor device includes a semiconductor substrate that includes a substrate layer having a first composition of semiconductor material. A source region, drain region, and a channel region are formed in the substrate, with the drain region spaced apart from the source region and the gate region abutting the channel region. The channel region includes a channel layer having a second composition of semiconductor material. Additionally, the substrate layer abuts the channel layer and applies a stress to the channel region along a boundary between the substrate layer and the channel layer.

Abstract: The objective of the present invention is to provide a semiconductor device of a hetero-junction field effect transistor that is capable of obtaining a high output and a high breakdown voltage and a manufacturing method of the same. The present invention is a semiconductor device of a hetero-junction field effect transistor provided with an AlxGa1-xN channel layer with a composition ratio of Al being x (0<x<1) formed on a substrate, an AlyGa1-yN barrier layer with a composition of Al being y (0<y?1) formed on the channel layer, and source/drain electrodes and a gate electrode formed on the barrier layer, wherein the composition ratio y is larger than the composition ratio x.

Abstract: Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates, and methods of forming such substrates and integrated circuits. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.

Abstract: A high electron mobility transistor includes first, second and third compound semiconductor layers. The second compound semiconductor layer has a first interface with the first compound semiconductor layer. The third compound semiconductor layer is disposed over the first compound semiconductor layer. The third compound semiconductor layer has at least one of lower crystallinity and relaxed crystal structure as compared to the second compound semiconductor layer. The gate electrode is disposed over the third compound semiconductor layer. Source and drain electrodes are disposed over the second compound semiconductor layer. The two-dimensional carrier gas layer is generated in the first compound semiconductor layer. The two-dimensional carrier gas layer is adjacent to the first interface. The two-dimensional carrier gas layer either is absent under the third compound semiconductor layer or is reduced in at least one of thickens and carrier gas concentration under the third compound semiconductor layer.

Abstract: Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad oxide, are formed by deposition onto, rather than reaction with and consumption of the surface layer. Alternatively, oxide deposition is preceded by a thermal oxidation step of short duration, e.g., rapid thermal oxidation. Here, the short thermal oxidation consumes little surface Si, and the Si/oxide interface is of high quality. The oxide may then be thickened to a desired final thickness by deposition. Furthermore, the thin thermal oxide may act as a barrier layer to prevent contamination associated with subsequent oxide deposition.

Abstract: A transistor includes: a first semiconductor layer and a second semiconductor layer with a first region and a second region, which are sequentially formed above a substrate; a first p-type semiconductor layer formed on a region of the second semiconductor layer other than the first and second regions; and a second p-type semiconductor layer formed on the first p-type semiconductor layer. The first p-type semiconductor layer is separated from a drain electrode by interposing therebetween a first groove having a bottom composed of the first region, and from a source electrode by interposing therebetween a second groove having a bottom composed of the second region.

Abstract: A semiconductor device and related method of manufacture are disclosed. The semiconductor device comprises a gate electrode formed on a semiconductor substrate, an active region containing spaces formed below the gate electrode, a channel region formed between the gate electrode and the spaces, and source and drain regions formed on opposite sides of the gate electrode within the active region. The spaces are formed by etching a semiconductor layer formed below the gate electrode in the active region.

Abstract: A low-cost field-effect transistor with a moisture-resistant gate covered by a thick moisture-resistant insulating film which suppresses an increase in gate capacitance, and a method of manufacturing the field-effect transistor. The field-effect transistor, has one of a T-shaped gate electrode and ?-shaped gate electrode, a drain electrode, and a source electrode, the source electrode and the drain electrode being electrically connected through an n-doped semiconductor region. The gate, source, and drain electrodes are located on a semiconductor layer which includes an insulating film having a thickness of 50 nm or less and covering a surface of the gate electrode and a surface of the semiconductor layer. A silicon nitride film, deposited by catalytic CVD, covers the insulating film and includes a void volume located between a portion of the gate electrode corresponding to a canopy of an open umbrella and the semiconductor layer.

Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.

Abstract: A junction field effect transistor (JFET) is fashioned where a channel of transistor is buried deeply within the workpiece within which the JFET is formed. Burying the channel below the surface of the workpiece and/or away from overlying conductive materials distances a current that flows in the channel from outside influences, such as the effects of the overlying conductive materials. The deep channel also provides a more regular path for the current flowing therein by moving the channel away from non-uniformities on or near the surface of the workpiece, where said non-uniformities or irregularities would interrupt or otherwise disturb current flowing in a channel that is not as deep. These aspects of the deep channel serve to reduce noise and allow the transistor to operate in a more repeatable and predictable manner, among other things.

Abstract: This invention pertains to an electronic device and to a method for making it. The device is a heterojunction transistor, particularly a high electron mobility transistor, characterized by presence of a 2 DEG channel. Transistors of this invention contain an AlGaN barrier and a GaN buffer, with the channel disposed, when present, at the interface of the barrier and the buffer. Surface treated with ammonia plasma resembles untreated surface. The method pertains to treatment of the device with ammonia plasma prior to passivation to extend reliability of the device beyond a period of time on the order of 300 hours of operation, the device typically being a 2 DEG AlGaN/GaN high electron mobility transistor with essentially no gate lag and with essentially no rf power output degradation.

Abstract: A multi-layer structure for use in the fabrication of integrated circuit devices is adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors. The structure has, on a substrate, a channel layer, spacer layer on the channel layer, a first Schottky layer, a second Schottky layer on the first Schottky layer, and a third Schottky layer on the second Schottky layer, and a contact layer on the third Schottky layer. Etch stops are defined intermediate the first and second Schottky layers, intermediate the second and third Schottky layers, and intermediate the third Schottky layer and the contact layer.

Abstract: There is provided a hetero junction field effect transistor including: a first layer of a nitride based, group III-V compound semiconductor; a second layer of a nitride based, group III-V compound semiconductor containing a rare earth element, overlying the first layer; a pair of third layers of a nitride based, group III-V compound semiconductor, overlying the second layer, the third layers being spaced from each other; a gate electrode disposed between the third layers at least a region of the second layer; and a source electrode overlying one of the third layers and a drain electrode overlying an other of the third layers. A method of fabricating the hetero junction field effect transistor is also provided.

Abstract: A method for making a heterojunction bipolar transistor includes the following steps: forming a heterojunction bipolar transistor by depositing, on a substrate, subcollector, collector, base, and emitter regions of semiconductor material; the step of depositing the subcollector region including depositing a material composition transition from a relatively larger bandgap material nearer the substrate to a relatively smaller bandgap material adjacent the collector; and the step of depositing the collector region including depositing a material composition transition from a relatively smaller bandgap material adjacent the subcollector to a relatively larger bandgap material adjacent the base.

Abstract: A method of fabricating heterojunction devices, in which heterojunction devices are epitaxially formed on active area regions surrounded by field oxide regions and containing embedded semiconductor wells. The epitaxial growth of the heterojunction device layers may be selective or not and the epitaxial layer may be formed so as to contact individually each one of a plurality of heterojunction devices or contact a plurality of heterojunction devices in parallel. This method can be used to fabricate three-terminal devices and vertically stacked devices.

Abstract: A semiconductor device which is capable of operating with a single positive power supply and has a low gate resistance, and a process for production thereof. The semiconductor device includes a channel layer (which constitutes a current channel), a first semiconductor layer formed on said channel layer, a second semiconductor layer in an island-like shape doped with a conductive impurity and formed on said first semiconductor layer, and a gate electrode formed on said second semiconductor layer, wherein said first and second semiconductor layers under said gate electrode have a conductive impurity region formed therein to control the threshold value of current flowing through said channel layer, and the conductive impurity region formed in second semiconductor layer is doped with a conductive impurity more heavily than in the conductive impurity region formed in said first semiconductor layer.

Abstract: Transistors are fabricated by forming a nitride-based semiconductor barrier layer on a nitride-based semiconductor channel layer and forming a protective layer on a gate region of the nitride-based semiconductor barrier layer. Patterned ohmic contact metal regions are formed on the barrier layer and annealed to provide first and second ohmic contacts. The annealing is carried out with the protective layer on the gate region. A gate contact is also formed on the gate region of the barrier layer. Transistors having protective layer in the gate region are also provided as are transistors having a barrier layer with a sheet resistance substantially the same as an as-grown sheet resistance of the barrier layer.

Abstract: To provide a semiconductor device which makes it possible to avoid deterioration in the step coverage property at a gate electrode provided on an operating region and decrease a leakage current between the operating region and the gate electrode. The semiconductor device arranged as a HEMT is made to include an operating region composed of multilayer films, such as a channel layer, an electron supplying layer and other semiconductor layer, and having an island structure independently mesa-isolated from one another. The semiconductor device also includes a gate electrode and an impurity diffusion layer provided on the surface of the operating region, the impurity diffusion layer being doped with an impurity having a conductivity type inverse to the impurity doped into the electron supplying layer.

Abstract: To provide a semiconductor device which makes it possible to avoid deterioration in the step coverage property at a gate electrode provided on an operating region and decrease a leakage current between the operating region and the gate electrode. The semiconductor device arranged as a HEMT is made to include an operating region composed of multilayer films, such as a channel layer, an electron supplying layer and other semiconductor layer, and having an island structure independently mesa-isolated from one another. The semiconductor device also includes a gate electrode and an impurity diffusion layer provided on the surface of the operating region, the impurity diffusion layer being doped with an impurity having a conductivity type inverse to the impurity doped into the electron supplying layer.

Abstract: To provide a semiconductor device which makes it possible to avoid deterioration in the step coverage property at a gate electrode provided on an operating region and decrease a leakage current between the operating region and the gate electrode. The semiconductor device arranged as a HEMT is made to include an operating region composed of multilayer films, such as a channel layer, an electron supplying layer and other semiconductor layer, and having an island structure independently mesa-isolated from one another. The semiconductor device also includes a gate electrode and an impurity diffusion layer provided on the surface of the operating region, the impurity diffusion layer being doped with an impurity having a conductivity type inverse to the impurity doped into the electron supplying layer.

Abstract: An efficient method of fabricating a high-quality microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a microstructure on the detached surface of the carrier substrate by depositing an epitaxial layer on the detached surface of a carrier substrate. Also included is a microstructure fabricated from such method.

Abstract: A BiCMOS semiconductor, and manufacturing method therefore, is provided. A semiconductor substrate having a collector region is provided. A pseudo-gate is formed over the collector region. An emitter window is formed in the pseudo-gate to form an extrinsic base structure. An undercut region beneath a portion of the pseudo-gate is formed to provide an intrinsic base structure in the undercut region. An emitter structure is formed in the emitter window over the intrinsic base structure. An interlevel dielectric layer is formed over the semiconductor substrate, and connections are formed through the interlevel dielectric layer to the collector region, the extrinsic base structure, and the emitter structure. The intrinsic base structure comprises a compound semiconductive material such as silicon and silicon-germanium, or silicon-germanium-carbon, or combinations thereof.

Abstract: Field-Effect Transistor Based on Embedded Cluster Structures and Process for Its Production In field-effect transistors, semiconductor clusters, which can extend from the source region to the drain region and which can be implemented in two ways, are embedded in one or a plurality of layers. In a first embodiment, the semiconductor material of the adjacent channel region can be strained by the clusters and the effective mass can thus be reduced by altering the energy band structure and the charge carrier mobility can be increased. In a second embodiment, the clusters themselves can be used as a canal region. These two embodiments can also appear in mixed forms. The invention can be applied to the Si material system with SiGe clusters or to the GaAs material system with InGaAs clusters or to other material systems.

Abstract: A multi-layer film 10 is formed by stacking a Si1-x1-y1Gex1Cy1 layer (0?x1<1 and 0<y1<1) having a small Ge mole fraction, e.g., a Si0.785Ge0.2C0.015 layer 13, and a Si1-x2-y2Gex2Cy2 layer (0<x2?1 and 0?y2<1) (where x1<x2 and y1>y2) having a high Ge mole fraction, e.g., a Si0.2Ge0.8 layer 12. In this manner, the range in which the multi-layer film serves as a SiGeC layer with C atoms incorporated into lattice sites extends to high degrees in which a Ge mole fraction is high.

Abstract: An architecture for creating a vertical JFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is positioned over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET.

Abstract: A structure and a method for forming the structure, the method including forming a compressively strained semiconductor layer, the compressively strained layer having a strain greater than or equal to 0.25%. A tensilely strained semiconductor layer is formed over the compressively strained layer. The compressively strained layer is substantially planar, having a surface roughness characterized in (i) having an average wavelength greater than an average wavelength of a carrier in the compressively strained layer or (ii) having an average height less than 10 nm.

Abstract: A method for manufacturing a monolithic apparatus including a plurality of materials presenting a plurality of coplanar lands includes the steps of: (a) providing a substrate constructed of a first material and presenting a first land; (b) trenching the substrate to effect a cavity appropriately dimensioned to receive a semiconductor structure in an orientation presenting a second land generally coplanar with the first land; (c) depositing an accommodating layer constructed of a second material on the substrate and within the cavity to establish a workpiece; (d) depositing a composition layer constructed of a third material on the substrate; (e) selectively removing portions of the composition layer and the accommodating layer to establish the semiconductor structure; (f) depositing a cap layer constructed of a fourth material on the workpiece; and (g) removing the cap layer to establish a substantially planar face displaced from the plurality of lands by a predetermined distance.

Abstract: Methods for fabricating multi-layer semiconductor structures including strained material layers using a minimum number of process tools and under conditions optimized for each layer. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Abstract: A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer is deposited. This ILD layer is etched to form a source region contact, a drain region contact, a first gate electrode contact, and a second gate electrode contact.

Abstract: A method is provided for etching quaternary interface layers of InxGa1−xAsyP1−y which are formed between layers of GaAs and InGaP in heterojunction bipolar transistors (HBTs). In accordance with the method, the interface is exposed by etching the GaAs layer with an etchant that is selective to InGaP. The interface is then etched with a dilute aqueous solution of HCl and H2O2 that is selective to InGaP. The controlled etching provided by this methodology allows HBTs to be manufactured with more sophisticated, near ideal designs which may contain multiple GaAs/InGaP interfaces.

Abstract: A field-effect transistor has a composite channel structure having a first channel layer containing GaInP semiconductor and a second channel layer containing GaAs semiconductor. When the electric field is low in the channel, a channel current is primarily conducted in the second channel layer. When the electric field is high, the electrons flowing in the second channel layer move through real space transition to the first channel layer. These electrons conduct in the channel primarily in the first channel layer. Since GaInP semiconductor has a wider forbidden bandwidth than that of GaAs semiconductor, the avalanche breakdown voltage of GaInP semiconductor is higher than that of GaAs semiconductor. When the electric field is high, the conduction electrons travel in this GaInP semiconductor layer. This also improves the avalanche breakdown voltage of the field-effect transistor.

Abstract: A method of growing semi-insulating GaN epilayers by ammonia-molecular beam epitaxy (MBE) through intentional doping with carbon is described. Thick GaN layers of high resistivity are an important element in GaN based heterostructure field-effect transistors. A methane ion source is preferably used as the carbon dopant source.

Abstract: A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 &mgr;m to avoid hot carrier degradation while still achieving performance increases over 0.

Abstract: Provided are a semiconductor device which shows excellent negative differential conductance or negative transconductance and is manufactured without a complicated manufacturing process and a method of manufacturing the same. The semiconductor device includes a channel layer serving as a conduction region and a floating region electrically separated from the channel layer. Provided between the channel layer and the floating region is a quantum well layer constituted with a pair of barrier layers and a quantum well layer sandwiched between the pair of barrier layers. A source electrode and a drain electrode are electrically connected to the channel layer. A gate electrode is provided in an opposite position from the well layer in the floating region. When changing a drain voltage relative to a predetermined gate voltage, drain current characteristics show negative differential conductance.

Abstract: A method of fabricating apparatus, and the apparatus, for providing low voltage temperature compensation in a single power supply HFET including a stack of epitaxially grown compound semiconductor layers with an HFET formed in the stack. A Schottky diode is formed in the stack adjacent the HFET during the formation of the HFET. The HFET and the Schottky diode are formed simultaneously, with a portion of one of the layers of metal forming the gate of the HFET being positioned in contact with a layer of the stack having a low bandgap (e.g. less than 0.8 eV) to provide a turn-on voltage for the Schottky diode of less than 1.8 Volts. The Schottky diode is connected to the gate contact of the HFET by a gate circuit to compensate for changes in current loading in the gate circuit with changes in temperature.

Abstract: There is provided a field effect transistor including a semi-insulating semiconductor substrate formed with a recess at a region in which a gate is to be formed, a gate base layer formed on the recess and composed of one of an InP layer and a plurality of layers including an InP layer, and a gate electrode formed on the gate base layer. The InP layer may be replaced with an InGaP layer, an AlXGa1−XAs (0≦X≦1) layer, an InXGa1−XAs (0≦X≦1) layer, or an InXAl1−XAs (0≦X<0.4 or 0.6<X≦1) layer. The above-mentioned field effect transistor prevents thermal instability thereof caused by impurities such as fluorine entering a donor layer to thereby inactivate donor. As a result, there is presented a highly reliable compound field effect transistor.

Abstract: A method of fabricating a MOSEFT device, which is suitable for fabricating an III-V group semiconductor device. A substrate comprises a buffer layer and a channel layer, wherein silicon oxide is formed on the channel layer by a liquid phase deposition method (LPD) to control the parameters of growth solution. A silicon oxide insulating layer that is formed on the channel layer has a thickness of approximately 40 Å, wherein the silicon oxide insulating layer is used as a gate oxide layer. A source, a drain and a gate are formed on the gate oxide layer. The LPD process is performed in a temperature range from room temperature to 60° C. Thus, the low temperature of the LPD technique will not lead to a negative heat effect on other fabrications or on the wafer, therefore the low temperature will not cause thermal stress, dopant redistribution, dopant diffusion or material interaction, for example.

Abstract: P-type impurities in a gate electrode is positively made to diffuse into a p-type impurity diffusion layer and an electrical p-n junction face in a gate electrode region is formed either within or on the bottom face of the p-type impurity diffusion layer, and thereby the effect that an interface state arising on a regrowth interface has over the p-n junction face can be well suppressed. This results in an improvement in high frequency characteristic of the JFET.

Abstract: An insulated-gate semiconductor element with a trench structure is provided, which has a high breakdown voltage even though a silicon carbide substrate is used that is preferable to obtain a semiconductor element with favorable properties. The surface of a silicon carbide substrate is etched to form a concave portion. Then, a particle beam, for example an ion beam, is irradiated from above, and a defect layer is formed at least in a bottom surface of the concave portion. The substrate is heated in an oxidation atmosphere, and an oxide film is formed at least on a side surface and the bottom surface of the concave portion. Then, a gate electrode is formed on the oxide film.

Abstract: Provided is a method for fabricating a compound semiconductor multilayer epitaxial substrate comprising a plurality of epitaxial layers, comprising the steps of determining at least one of the thickness, impurity concentration, and composition of an epitaxial layer comprising the multilayer epitaxial substrate by theoretical calculation, the theoretical calculation describing on electric field and charge distribution inside the epitaxial layer, and performing epitaxy of the epitaxial layer according to the theoretical calculation of the thickness, impurity concentration and/or composition of the epitaxial layer so that measurable electric characteristics of the substrate predetermined by the calculation are satisfied. The method can reduce the fabrication process and also can be applied to manufacture a multilayer epitaxial substrate having a unique structure.

Abstract: Semiconductor structures and a method of forming semiconductor structures The avalanche breakdown characteristics, such as breakdown voltage and impact ionisation coefficient, of a semiconductor structure can be controlled by controlling the Brillouin-zone-averaged energy bandgap (<Ec>) of the material forming the structure. Consequently, the avalanche breakdown characteristics of a device may be tailored independently of the bandgap Eg. The Brillouin-zone-averaged energy bandgap (<Ec>) may be controlled by controlling the composition of the semiconductor used or by straining its lattice.

Abstract: When a device using GaN semiconductors is made on a hard and chemically stable single-crystal substrate such as sapphire substrate or SiC substrate, a semiconductor device and its manufacturing method ensure high-power output or high-frequency operation of the device by thinning the substrate or making a via hole in the substrate. When a light emitting device using GaN semiconductors is made on a non-conductive single-crystal substrate such as sapphire substrate, the semiconductor device and its manufacturing method reduce the operation voltage of the light emitting device by making a via hole to the substrate. More specifically, after making a GaN FET by growing GaN semiconductor layers on the surface of a sapphire substrate, the bottom surface of the sapphire substrate is processed by lapping, using an abrasive liquid containing a diamond granular abrasive material and reducing the grain size of the abrasive material in some steps, to reduce the thickness of the sapphire substrate to 100 &mgr;m or less.

Abstract: Using a mask opening a gate region, an undoped GaAs layer is selectively etched with respect to an undoped Al0.2Ga0.8As layer by dry etching with introducing a mixture gas of a chloride gas containing only chlorine and a fluoride gas containing only fluorine (e.g. BCl3+SF6 or so forth). By about 100% over-etching is performed for the undoped GaAs layer, etching (side etching) propagates in transverse direction of the undoped GaAs layer. With using the mask, a gate electrode of WSi is formed. Thus, a gap in a width of about 20 nm is formed by etching in the transverse direction on the drain side of the gate electrode. By this, a hetero junction FET having reduced fluctuation of characteristics of an FET, such as a threshold value, lower a rising voltage and higher breakdown characteristics.

Abstract: A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein: surfaces of the buffer layer are c facets of Ga atoms; a channel layer including GaN or InGaN formed on the buffer layer, wherein: surfaces of the channel layer are c facets of Ga or In atoms; an electron donor layer including AlGaN formed on the channel layer, wherein: surfaces of the electron donor layer are c facets of Al or Ga atoms; a source electrode and a drain electrode formed on the electron donor layer; a cap layer including GaN or InGaAlN formed between the source electrode and the drain electrode, wherein: surfaces of the cap layer are c facets of Ga or In atoms and at least a portion of the cap layer is in contact with the electron donor layer; and a gate electrode formed at least a portion of which is in contact with the cap layer.

Abstract: A method of forming a crystalline silicon well over a silicon oxide barrier layer, preferably for use in formation of a tunneling diode. A silicon substrate is provided of predetermined crystallographic orientation. A layer of crystallographic silicon oxide is formed over the silicon substrate and substantially matched to the crystallographic orientation of the silicon substrate. A layer of crystallographic silicon is formed over the silicon oxide layer substantially matched to the crystallographic orientation of the silicon oxide layer. The layer of silicon oxide is formed by the steps of placing the silicon substrate in a chamber having an oxygen ambient and heating the substrate to a temperature in the range of from about 650 to about 750 degrees C. at a pressure of from about 10−4 to about 10−7 until the silicon oxide layer has reached a predetermined thickness.