Abstract: A semiconductor device comprises an active region formed in a semiconductor substrate; a recess region being formed within the active region and defining a protruding portion; and a gate structure formed within the recess region.

Abstract: By consuming a surface portion of polysilicon material or silicon material after implantation and prior to activation of dopants, contaminants may be efficiently removed, thereby significantly enhancing the process uniformity during a subsequent silicidation process. Hence, the defect rate during the silicidation process, for instance “missing silicide” defects, may be significantly reduced, thereby also enhancing the reliability of static RAM cells.

Abstract: A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second conductivity type doping, which is the opposite of the first conductivity doping. Further, the at least one semiconductor channel vertically abuts a top gate region and at least one bottom gate region, both having the second conductivity type doping. The gate electrode, which comprises side gate region, the top gate region, and at least one bottom gate regions, wraps around each of the at least one semiconductor channel to provide tight control of the current, i.e., a low off-current, through the at least one semiconductor channel. By employing multiple channels, the JFET may provide a high on-current.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a semiconductor device formed with a plurality of transistors; forming a first stress layer with a plurality of layers on the semiconductor device; forming a second stress layer with a plurality of layers on another surface of the semiconductor device; covering photo resist on a region of the first stress layer to cover at least one of the transistors; and performing ion implantation on the part of the semiconductor device that is not covered by the photo resist. In another embodiment, the second stress layers can be formed after the ion implantation. The method can simultaneously enhance the device performance of the PMOS and NMOS on the same wafer. It also solves the problem of procedure integration caused by the produced compressive stress and tensile stress.

Abstract: Semiconductor devices (102) and drain extended PMOS transistors (CT1a) are provided, as well as fabrication methods (202) therefor, in which a p-type separation region (130) is formed between an n-buried layer (108) and the transistor backgate (126) to increase breakdown voltage performance without increasing epitaxial thickness.

Abstract: A doubled gate, dynamic storage device and method of fabrication are disclosed. A back (bias gate) surrounds three sides of a semiconductor body with a front gate disposed on the remaining surface. Two different gate insulators and gate materials may be used.

Abstract: A method of forming compressive nitride film is provided. The method includes performing a chemical vapor deposition (CVD) process to form a nitride film on a substrate, and the method is characterized by adding a certain gas, selected from among Ar, N2, Kr, Xe, and mixtures thereof. Due to the addition of the foregoing certain gas, it can increase the compressive stress, thereby increasing PMOS drive current gain.

Abstract: The present invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122) structures laterally formed on opposites sides thereof. A first gate structure (116) is formed along the substrate, laterally adjoining the channel structure orthogonal to the source and drain structures. A second gate structure (118) is formed along the substrate, laterally adjoining the channel structure, orthogonal to the source and drain structures and opposite the first gate stricture.

Abstract: Double gate JFET with reduced area consumption and fabrication method therefore. Double-gate semiconductor device including a substrate having a shallow trench isolator region comprising a first STI and a second STI, a channel region having a first and second channel edges, the channel region formed in the substrate and disposed between and in contact with the first STI and the second STI at the first and second channel edge. The first STI has a first cavity at the first channel edge, and the second STI has a second cavity at the second channel edge. The device further includes a gate electrode region comprising conductive material filling at least one of the first and second cavities. At least one of the first and second cavities is physically configured to provide electrical coupling of the gate electrode region to a back-gate P-N junction.

Abstract: A low on-state resistance power semiconductor device has a shape and an arrangement that increase the channel density and the breakdown voltage The power semiconductor device comprises a plurality of individual cells formed on a semiconductor substrate (62). Each individual cell comprises a plurality of radially extending branches (80) having source regions (37) within base regions (36). The plurality of individual cells are arranged such that at least one branch of each cell extends towards at least one branch of an adjacent cell and wherein the base region (36) of the extending branches merge together to form a single and substantially uniformly doped base region (36) surrounding drain islands (39) at the surface of the semiconductor substrate (62).

Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.

Abstract: A semiconductor device manufacturing method including forming at least a first conductive film and a first insulting film above a semiconductor substrate, forming a plurality of first resist patterns above the first insulating film periodically at first intervals, patterning at least the first insulting film by use of the first resist patterns to form a plurality of mask patterns, each of the mask patterns including the first insulating film, selectively forming a second resist pattern in a space between the mask patterns in such a manner that the second resist pattern is formed in the space corresponding to a region where a second wiring structure wider than the first wiring structure is to be formed, and patterning the first conductive film by use of the second resist pattern and the mask patterns.

Abstract: A multi-finger transistor and method of manufacturing the same are provided. The multi-finger transistor includes two active regions, a multi-finger gate, a plurality of source regions and a plurality of drain regions. The two active regions are defined in a unit cell of a substrate. The multi-finger gate includes a plurality of gate fingers formed in the two active regions and a gate connector between the two active regions. The gate connector connects the gate fingers to each other. The source regions are formed in first portions of the two active regions adjacent to the gate fingers. The drain regions are formed in second portions of the two active regions adjacent to the gate fingers.

Abstract: In a field effect transistor (FET), and a method of fabricating the same, the FET includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a plurality of wire channels electrically connecting the source and drain regions, the plurality of wire channels being arranged in two columns and at least two rows, and a gate dielectric layer surrounding each of the plurality of wire channels and a gate electrode surrounding the gate dielectric layer and each of the plurality of wire channels.

Abstract: A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect transistor, the first drain region of the first transistor accompanying a first load capacitance, the second drain region of the second transistor accompanying a second load capacitance smaller than the first load capacitance, and the first gate insulation film of the first transistor having an average relative dielectric constant higher than that of the second gate insulation film of the second transistor, thereby realizing a high operation speed.

Abstract: Integrated circuit devices are provided including an integrated circuit substrate and first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions. A first gate electrode is provided on the first active region. The first gate electrode has a first portion on the first active region that extends onto the first insulating region and a second portion at an end of the first portion on the first insulating region. A second gate electrode is provided on the second active region. An insulating layer is provided on the first, second and third active regions defining a first gate contact hole that exposes at least a portion of the second portion of the first gate electrode. The first gate electrode is free of a gate contact hole on the first portion of the first gate electrode. A second gate contact hole is provided on the second active region that exposes at least a portion of the second gate electrode.

Abstract: A method of fabricating non-volatile memory is provided. A plurality of first memory cells is formed on the memory cell region of a substrate. Each first memory cell includes a first composite layer, a first gate and a cap layer. There is a gap between two adjacent first memory cells. Then, a plurality of gates is formed in the respective gaps. The gates together with a second composite layer form a plurality of second memory cells. The second memory cells and the first memory cells together constitute a memory cell column. In the meantime, a plurality of gate structures is also formed on the peripheral circuit region. The gates in the gaps and the gates in the peripheral circuit region are formed using the same conductive layers.

Abstract: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255) located between the gate electrodes (250), removing a portion of the spacer material (415) and the protective layer (510) located over the gate electrodes (250). A remaining portion of the spacer material (415) remains over the top surface of the gate electrodes (250) and over the doped region (255), and a portion of the protective layer (510) remains over the doped region (255). The method further comprises removing the remaining portion of the spacer material (415) to form spacer sidewalls on the gate electrodes (250), expose the top surface of the gate electrodes (250), and leave a remnant of the spacer material (415) over the doped region (255).

Abstract: A plurality of first wiring structures of a first width are arranged periodically at first intervals. A second wiring structure is formed next to one of the first wiring structures. The lower part of the second wiring structure has a second width substantially equal to the sum of n times the first width of the first wiring structure (n is a positive integer equal to two or more) and (n?1) times the first interval.

Abstract: A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a trench slanting angle equal to or larger than 80 degrees is formed; and removing a damage portion in such a manner that the damage portion disposed on an inner surface of the trench formed in the semiconductor substrate in the step of forming the trench is etched and removed in hydrogen atmosphere under decompression pressure at a temperature equal to or higher than 1600° C.

Abstract: A method for manufacturing a semiconductor element, comprises: (1) forming a first insulating layer for electric field relaxation that is thicker than a first gate insulating layer in a first channel region of a transistor of a first conductive type that is one of P-type and N-type polarity formed on a semiconductor silicon wafer to surround an edge of a first gate electrode in order to reduce an electric field concentrated to a region surrounding the edge of the first gate electrode because of a voltage applied to the first gate electrode and a first drain region of the transistor of the first conductive type, and forming a second insulating layer for electric field relaxation that is thicker than a second gate insulating layer in a second channel region of a transistor of a second conductive type to surround the edge of the first gate electrode in order to reduce an electric field concentrated to a region surrounding an edge of a second gate electrode because of a voltage applied to the second gate electrod

Abstract: A silicon-on-insulator (SOI) device structure 100 formed using a self-aligned body tie (SABT) process. The SABT process connects the silicon body of a partially depleted (PD) structure to a bias terminal. In addition, the SABT process creates a self-aligned area of silicon around the edge of the active areas, as defined by the standard transistor active area mask, providing an area efficient device layout. By reducing the overall gate area, the speed and yield of the device may be increased. In addition, the process flow minimizes the sensitivity of critical device parameters due to misalignment and critical dimension control. The SABT process also suppresses the parasitic gate capacitance created with standard body tie techniques.

Abstract: A method for making a semiconductor device is described. That method comprises forming a dummy dielectric layer that is at least about 10 angstroms thick on a substrate, and forming a sacrificial layer on the dummy dielectric layer. After removing the sacrificial layer and the dummy dielectric layer to generate a trench that is positioned between first and second spacers, a gate dielectric layer is formed on the substrate at the bottom of the trench, and a metal layer is formed on the gate dielectric layer.

Abstract: Method of manufacturing a semiconductor device, including a first baseline technology electronic circuit (1) and a second option technology electronic circuit (2) as functional parts of a system-on-chip, by: manufacturing the first electronic circuit (1) with a first conductive layer (6; 6) that is patterned by subjecting an exposed layer portion thereof to Reactive Ion Etching (RIE); manufacturing the second electronic circuit (2) with a second conductive layer (6; 8) that is patterned by subjecting an exposed layer portion thereof to RIE; providing a tile structure (25; 26); providing the tile structure (25; 26) with at least one dummy conductive layer (6; 8) produced in the same processing step as the second conductive layer (6; 8); and exposing the dummy conductive layer (6; 8), at least partially, to obtain an exposed dummy layer portion, and RIE-etching of that exposed portion too when the second (6; 8) conductive layer is subjected to RIE.

Abstract: Gate conductors on an integrated circuit are formed with enlarged upper portions which are utilized to electrically connect the gate conductors with other devices. A semiconductor device comprises a gate conductor with an enlarged upper portion which electrically connects the gate conductor to a local diffusion region. Another semiconductor device comprises two gate conductors with enlarged upper portions which merge to create electrically interconnected gate conductors. Methods for forming the above semiconductor devices are also described and claimed.

Abstract: The present invention provides a dual gate transistor and a method for forming the same that results in improved device performance and density. The present invention uses a double gate design to implement a dual gate transistor. A double gate is a gate which is formed on both sides of the transistor body. The present invention thus provides a transistor with two double gates in series that provide improved current control over traditional dual gate designs. The preferred embodiment of the present invention uses a fin type body with dual double-gates. In a fin type structure, the double gates are formed on each side of a thin fin shaped body, with the body being disposed horizontally between the gates.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: The method for fabricating a semiconductor device comprises the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.

Abstract: A gate insulating film is formed on the principal surface of a semiconductor substrate. A silicon film is formed on the gate insulating film. Impurities are doped in the silicon film. In this case, impurities are doped into the silicon film to make a region of the silicon film in the memory cell area have a first impurity concentration and to make a region of the silicon film in the logic circuit area have a second impurity concentration lower than the first impurity concentration. The doped silicon film is patterned. In this case, the silicon film is patterned to leave word lines having the first impurity concentration and serving as gate electrodes in the memory cell area and to leave gate electrodes having the second impurity concentration in the logic circuit area.

Abstract: A gate insulation film is formed on a semiconductor substrate, gate electrodes are formed on the gate insulation film, and source/drain diffusion layers are formed. A silicon nitride films is formed on a side wall of the gate electrodes, a silicon oxide film is formed on the overall surface, and the silicon oxide film is etched back to have the same height as that of the gate electrodes so that the surface is flattened, and then the surface of the gate electrodes are etched by a predetermined thickness to form a first stepped portion from the silicon oxide film, the first stepped portion is filled up by a tungsten film, the surface of the tungsten film is etched by a predetermined thickness so that a second stepped portion is formed, and then the second stepped portion is filled by a silicon nitride films.

Abstract: Methods of forming an integrated circuit device may include forming first and second spaced apart source/drain regions on a surface of a semiconductor substrate. A gate insulating layer can be formed on the semiconductor substrate extending between the first and second spaced apart souce/drain regions. The gate insulating layer can have a reduced thickness at a central portion thereof between the first and second spaced apart source/drain regions. A thickness of the gate insulating layer can increase as it extends toward each of the source/drain regions. A gate electrode can be formed on the gate insulating layer such that the gate insulating layer is between the semiconductor substrate and the gate electrode. Related devices are also discussed.

Abstract: This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.

Abstract: The present invention generally relates to an apparatus and method of carbon nanotube (CNT) gate field effect transistor (FET), which is used to replace the current metal gate of transistor for decreasing the gate width greatly. The carbon nanotube has its own intrinsic characters of metal and semiconductor, so it can be the channel, connector or next-level gate of transistor. Furthermore, the transistor has the structure of exchangeable source and drain, and can be defined the specificity by outside wiring.

Abstract: Multi-gate MOS transistors and fabrication methods are described, in which the transistor semiconductor body thickness or width is lithography independent, allowing scaled triple and quad-gate devices having semiconductor bodies smaller than a lateral gate length dimension. A form structure is provided over a semiconductor wafer starting structure, and spacers are formed along one or more sidewalls of an opening in the form structure. A semiconductor material is deposited in the opening by epitaxial growth or other deposition process, and the form structure and the spacer are removed. A gate structure is then formed along the top and sides of a central portion of the formed semiconductor body. The spacer may be L-shaped, providing an undercut or recess at the bottom of the semiconductor body sidewall, and the gate may be formed in the undercut area to allow fabrication of more than three gates.

Abstract: A power control system (25) uses two separate currents to control a startup operation of the power control system (25). The two currents are shunted to ground to inhibit operation of the power control system (25) and one of the two currents is disabled to minimize power dissipation. The two independently controlled currents are generated by a multiple output current high voltage device (12) responsively to two separate control signals (23, 24).

Abstract: The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

Abstract: A thin film transistor of the present invention is provided with (i) a plurality of divided channel regions formed under a gate electrode, and (ii) divided source regions and divided drain regions between which each of the divided channel regions is sandwiched, the divided source regions being connected with one another, and the divided drain regions being connected with one another. Here, the divided channel regions are so arranged that a spacing between the divided channel regions is smaller than a channel divided width which is a width of one divided channel region, the channel divided width is not more than 50 ?m, and the spacing is not less than 3 ?m. With this arrangement, it is possible to provide a thin film transistor capable of obtaining reliability with reducing the variation in threshold voltage by reducing the self-heating at the channel regions, as well as capable of reducing the increase of a layout area.

Abstract: A BiCMOS semiconductor, and manufacturing method therefore, is provided. A semiconductor substrate having a collector region is provided. A pseudo-gate is formed over the collector region. An emitter window is formed in the pseudo-gate to form an extrinsic base structure. An undercut region beneath a portion of the pseudo-gate is formed to provide an intrinsic base structure in the undercut region. An emitter structure is formed in the emitter window over the intrinsic base structure. An interlevel dielectric layer is formed over the semiconductor substrate, and connections are formed through the interlevel dielectric layer to the collector region, the extrinsic base structure, and the emitter structure. The intrinsic base structure comprises a compound semiconductive material such as silicon and silicon-germanium, or silicon-germanium-carbon, or combinations thereof.

Abstract: A semiconductor integrated circuit device wherein plural field effect transistors having different threshold values are integrated on one chip by forming plural gate electrodes of silicon-germanium mixed crystals having different germanium contents. By varying the germanium content of the gate electrode material, a work function with respect to the channel region can be varied, so a semiconductor integrated circuit device wherein plural field effect transistors having different threshold voltage values are integrated on one chip can be manufactured.

Abstract: The present invention generally relates to an apparatus and method of carbon nanotube (CNT) gate field effect transistor (FET), which is used to replace the current metal gate of transistor for decreasing the gate width greatly. The carbon nanotube has its own intrinsic characters of metal and semiconductor, so it can be the channel, connector or next-level gate of transistor. Furthermore, the transistor has the structure of exchangeable source and drain, and can be defined the specificity by outside wiring.

Abstract: A double-gate semiconductor device includes a substrate, an insulating layer, a fin and two gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. A first gate is formed on the insulating layer and is located on one side of the fin. A portion of the first gate includes conductive material doped with an n-type dopant. The second gate is formed on the insulating layer and is located on the opposite side of the fin as the first gate. A portion of the second gate includes conductive material doped with a p-type dopant.

Abstract: A method of forming gate electrode layer portions having differing widths comprising the following steps. A structure having a gate electrode layer and a hard mask layer thereover and including two or more active areas is provided. The hard mask layer is patterned to form two or more respective hard mask layer portions within the two or more active areas. One or more of the two or more respective hard mask layer portions is/are selectively trimmed to reduce its/their width to a second width leaving at least one the respective hard mask layer portions untrimmed. The gate electrode layer is then patterned.

Abstract: As shown in FIG. 1(a), a gate oxide film 12 is formed on an Si substrate 11. A polysilicon layer 13 is formed thereon. A natural oxide film 14 having an arbitrary thickness is formed on the polysilicon layer 13 after phosphorus is made to diffuse into the polysilicon layer 13 and before a resist layer is coated. Thus, as shown in FIG. 1(b), the natural oxide film 14 present on the polysilicon layer 13 is removed by DHF cleaning (cleaning with dilute HF). Thereafter, a resist layer 15 is coated onto the polysilicon layer 13, and is patterned. A polysilicon gate electrode G is formed by dry-etching using the resist layer 15 as a mask.

Abstract: This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.

Abstract: A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with the a gate dielectric. The N channel gate stack and a portion of the P channel gate stack are etched by a dry etch. The etch of P channel gate stack is completed with a wet etch. The wet etch is very selective to the gate dielectric and to the second metal type so that the N channel transistor is not adversely effected by completing the etch of the P channel gate stack.

Abstract: A semiconductor memory device capable of electrically writing and erasing data has a plurality of cell transistors for storing data, each of the cell transistors having a floating gate electrode and a control gate electrode, and a plurality of select transistors for controlling and selecting the cell transistors. Before the control gate electrodes of the cell transistors are formed, the surface of a substrate directly above channel regions of the select transistors fabricated in the same process as the cell transistors is exposed, and gate insulating films of the select transistors are formed on the exposed surface of the substrate. The control gate electrodes of the cell transistors are formed, and gate electrodes of the select transistors are formed on the gate insulating films.

Abstract: A method of producing a semiconductor device able to prevent outward diffusion of an impurity from a gate electrode and improve the device quality, the method comprising the steps of forming a gate electrode made of a semiconductor layer on a substrate (preferably SOI substrate) via a gate insulating film, forming a first insulating film coating the gate electrode by ALD, forming a second insulating film on a first insulating film, introducing an impurity to a substrate (preferably silicon active layer of the SOI wafer) to form a source/drain region by self-alignment with respect to the gate electrode, and forming an interlayer insulating film on the second insulating film.

Abstract: In semiconductor memories having a surrounding gate configuration, webs, i.e. vertical rectangular pillars made of substrate material, are formed at the surface of a semiconductor substrate and are surrounded by the gate electrodes in a lower region. Conventionally, it is not possible for word lines to make contact with the gate electrodes in the lower region of the webs without at the same time electrically influencing substrate regions at a higher level in the webs or short-circuiting bit lines from their sidewalls, unless complicated methods requiring additional lithography steps are used. A method for the self-aligning, selective contact-connection of the peripheral gate electrodes is performed with the aid of an insulation layer having a smaller layer thickness than the peripheral gate electrodes.

Abstract: A surface geometry for a MOS-gated device is provided that allows device size to be varied in both the x-axis and the y-axis by predetermined increments. The actual device size is set or “programmed” by the metal and pad masks or the contact metal and pad masks. This approach saves both time and expense, since only new contact, metal and pad masks, or new metal and pad mask are required for each new device. Wafers may also be manufactured and stored at an inventory location prior to contact or metal mask, significantly reducing the time required to manufacture new devices. It is also be possible to qualify a family of devices made using this approach without qualifying each device. In addition, the location of the source or the source and gate bonding pads may be easily moved for assembly in a new package or for a new application.

Abstract: A metal gate structure and method of forming the same introduces metal impurities into a first metal layer, made of TiN, for example. The impurities create a surface region of greater etch selectivity that prevents overetching of the TiN during the etching of an overlying tungsten gate during the formation of the metal gate structure. The prevention of the overetching of the TiN protects the gate oxide from undesirable degradation. The provision of aluminum or tantalum as the metal impurities provides adequate etch stopping capability and does not undesirably affect the work function of the TiN.