Making Plural Insulated Gate Field Effect Transistors Of Differing Electrical Characteristics Patents (Class 438/275)
  • Patent number: 11328958
    Abstract: A device includes first and second transistors and first and second isolation structures. The first transistor includes a raised structure, a first gate structure over the raised structure, and a first source/drain structure over the raised structure and adjacent the first gate structure. The first isolation structure surrounds the raised structure and the first source/drain structure of the first transistor. A bottommost surface of the first source/drain structure is spaced apart from a topmost surface of the first isolation structure. The second transistor includes a fin structure, a second gate structure over the raised structure, and a second source/drain structure over the fin structure. The second isolation structure surrounds a bottom of the fin structure of the second transistor. A bottommost surface of the second source/drain structure is in contact with a topmost surface of the second isolation structure.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Barn Chen, Ting-Huang Kuo, Shiu-Ko Jangjian, Chi-Cherng Jeng, Kuang-Yao Lo
  • Patent number: 11276702
    Abstract: Fins lined up in a Y direction, a control gate electrode and a memory gate electrode each extending in the Y direction so as to straddle the fins, a plurality of first plugs electrically connected with a drain region formed in each of the fins, and a plurality of second plugs electrically connected with a source region formed in each of the fins are formed. Here, a N-th plug of the plurality of first plugs lined up in the Y direction is coupled with each of (2N?1)-th and 2N-th fins in the Y direction. Also, a N-th plug of the plurality of second plugs lined up in the Y direction is coupled with each of 2N-th and (2N+1)-th fins in the Y direction.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 15, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshiyuki Kawashima
  • Patent number: 11201209
    Abstract: A method includes providing a semiconductor substrate, and forming a first N-type implant region and a second N-type implant region in the semiconductor substrate. The first N-type implant region and the second N-type implant region are separated by a portion of the semiconductor substrate. The method also includes forming a first P-type implant region in the semiconductor substrate, and performing a heat treatment process on the semiconductor substrate to form an N-type well region and a P-type well region in the semiconductor substrate. The N-type well region has a first portion, a second portion, and a third portion between the first portion and the second portion. The doping concentration of the third portion is lower than the doping concentration of the first portion and the doping concentration of the second portion.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: December 14, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Syed Neyaz Imam, Po-An Chen
  • Patent number: 11152393
    Abstract: A semiconductor device using an SOI (Silicon On Insulator) substrate, capable of preventing malfunction of MISFETs (Metal Insulator Semiconductor Field Effect Transistor) and thus improving the reliability of the semiconductor device. Moreover, the parasitic resistance of the MISFETs is reduced, and the performance of the semiconductor device is improved. An epitaxial layer formed on an SOI layer above an SOI substrate is formed to have a large width so as to cover the ends of the upper surface of an isolation region adjacent to the SOI layer. By virtue of this, contact plugs of which formation positions are misaligned are prevented from being connected to a semiconductor substrate below the SOI layer. Moreover, by forming the epitaxial layer at a large width, the ends of the SOI layer therebelow are prevented from being silicided. As a result, increase in the parasitic resistance of MISFETs is prevented.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: October 19, 2021
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshiki Yamamoto
  • Patent number: 11145506
    Abstract: Methods for selective deposition are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. An inhibitor, such as a polyimide layer, is selectively formed from vapor phase reactants on the first surface relative to the second surface. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the first surface. The first surface can be metallic while the second surface is dielectric. Accordingly, material, such as a dielectric transition metal oxides and nitrides, can be selectively deposited on metallic surfaces relative dielectric surfaces using techniques described herein.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: October 12, 2021
    Assignee: ASM IP HOLDING B.V.
    Inventors: Jan Willem Hub Maes, Michael Eugene Givens, Suvi P. Haukka, VamsI Paruchuri, Ivo Johannes Raaijmakers, Shaoren Deng, Andrea Illiberi, Eva E. Tois, Delphine Longrie
  • Patent number: 11127861
    Abstract: An embodiment includes an apparatus comprising: a thin film transistor (TFT) comprising: source and drain contacts; first and second gate contacts: a semiconductor material, comprising a channel, between the first and second gate contacts; and a first dielectric layer, between the first and second gate contacts, to fix charged particles. Other embodiments are described herein.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: September 21, 2021
    Assignee: Intel Corporation
    Inventor: Abhishek A. Sharma
  • Patent number: 11088136
    Abstract: A semiconductor device and method of forming the same are provided. The semiconductor device includes a substrate, a growth promoting region, a first gate stack, and a second gate stack. The substrate includes a first region and a second region. The growth promoting region is located in a surface of the substrate in the first region. The growth promoting region includes a first implantation species, and a surface of the substrate in the second region is free of the first implantation species. The first gate stack includes a first gate dielectric layer on the substrate in the first region. The second gate stack includes a second gate dielectric layer on the substrate in the second region.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
  • Patent number: 11081357
    Abstract: A method for fabricating a semiconductor device includes: forming a gate structure including a source side and a drain side over a substrate, wherein a dielectric material and a columnar crystal grain material are stacked over the substrate; doping a chemical species on the drain side of the gate structure; and exposing the gate structure doped with the chemical species to a re-growth process in order to thicken the dielectric material on the drain side of the gate structure.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: August 3, 2021
    Assignee: SK hynix Inc.
    Inventor: Seon-Haeng Lee
  • Patent number: 11069821
    Abstract: A semiconductor device and its manufacturing method are presented. The manufacturing method entails: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region that are mutually exclusive from one another, with a first oxide layer on the first and the second regions; conducting a nitriding process on the semiconductor substrate to form a nitride barrier layer on the first oxide layer on the first and the second regions; removing the first oxide layer on the second region; and conducting an oxidation process to form a second oxide layer on the second region.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: July 20, 2021
    Inventors: Guo Bin Yu, Xiao Ping Xu
  • Patent number: 11043564
    Abstract: Integrated circuit devices may include active regions spaced apart from each other in a direction. The active regions may include a first pair of active regions, a second pair of active regions, and a third pair of active regions. The first pair of active regions may be spaced apart from each other by a first distance in the direction, the second pair of active regions may be spaced apart from each other by the first distance in the direction, and the third pair of active regions may be spaced apart from each other by the first distance in the direction. The second pair of active regions may be spaced apart from the first pair of active regions and the third pair of active regions by a second distance in the direction, and the first distance may be shorter than the second distance.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: June 22, 2021
    Inventors: Jung Ho Do, Seung Hyun Song
  • Patent number: 10990014
    Abstract: A method of patterning a substrate may include providing a blanket photoresist layer on the substrate; performing an ion implantation procedure of an implant species into the blanket photoresist layer, the implant species comprising an enhanced absorption efficiency at a wavelength in the extreme ultraviolet (EUV) range; and subsequent to the performing the ion implantation procedure, performing a patterned exposure to expose the blanket photoresist layer to EUV radiation.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: April 27, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Tristan Y. Ma, Huixiong Dai, Anthony Renau, John Hautala, Joseph Olson
  • Patent number: 10910423
    Abstract: The present technology relates to a solid-state imaging device, a manufacturing method, and an electronic device, which can improve sensitivity while improving color mixing. The solid-state imaging device includes a first wall provided between a pixel and a pixel arranged two-dimensionally to isolate the pixels, in which the first wall includes at least two layers including a light shielding film of a lowermost layer and a low refractive index film of which refractive index is lower than the light shielding film. The present technology can be applied to, for example, a solid-state imaging device, an electronic device having an imaging function, and the like.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: February 2, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yuka Nakamoto, Yukihiro Sayama, Nobuyuki Ohba, Sintaro Nakajiki
  • Patent number: 10796899
    Abstract: Semiconductor devices having silicon doping for laser splash protection, along with associated methods and systems, are disclosed herein. In one embodiment, a semiconductor device includes a silicon layer and a circuitry layer with a plurality of semiconductor devices. A doped silicon region is formed on a front side of the silicon layer upon which the circuitry layer is deposited. The doped silicon region is positioned under the circuitry layer. The doped silicon region has a dopant concentration of at least 1015 cm?3.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Angelo Oria Espina
  • Patent number: 10714585
    Abstract: A method for fabricating a gate-all-around field-effect-transistor device includes forming a plurality of first stacked structures, each including a first sacrificial layer and a first semiconductor layer; forming a first dummy gate structure across the first stacked structures and partially covering the top and the sidewall surfaces of each first stacked structure, and a first sidewall spacer on each sidewall surface of the first dummy gate structures; forming a first source/drain doped layer, and a dielectric structure exposing the top surfaces of the first dummy gate structure and each first sidewall spacer; removing the first dummy gate structure to form a first trench; removing a portion of the first sacrificial layer to form a first via which partially exposes the first source/drain doped layer; forming a first barrier layer on the first source/drain doped layer; and forming a first gate structure to fill the first trench and the first via.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: July 14, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10643906
    Abstract: An embodiment of the invention comprises a method of forming a transistor comprising forming a gate construction having an elevationally-outermost surface of conductive gate material that is lower than an elevationally-outer surface of semiconductor material that is aside and above both sides of the gate construction. Tops of the semiconductor material and the conductive gate material are covered with masking material, two pairs of two opposing sidewall surfaces of the semiconductor material are laterally exposed above both of the sides of the gate construction. After the covering, the semiconductor material that is above both of the sides of the gate construction is subjected to monolayer doping through each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs and forming there-from doped source/drain regions above both of the sides of the gate construction.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventors: David K. Hwang, John A. Smythe, Haitao Liu, Richard J. Hill, Deepak Chandra Pandey
  • Patent number: 10629704
    Abstract: A semiconductor device in which the retention characteristics of a rewritable memory cell packaged together with a field effect transistor including a metal gate electrode are improved and a method for manufacturing the semiconductor device. The semiconductor device includes a field effect transistor with a metal gate electrode and a rewritable memory cell. The manufacturing method includes the step of replacing a dummy gate electrode with the metal gate electrode. Before the step of replacing the dummy gate electrode with the metal gate electrode, the method includes the steps of making the height of the memory cell lower than the height of the dummy gate electrode and forming a protective film for covering the memory cell.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: April 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuyoshi Mihara
  • Patent number: 10608108
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to extended drain MOSFET structures with a dual oxide thickness and methods of manufacture. The structure includes an extended drain metal oxide semiconductor transistor (EDMOS) comprising a gate structure with a dual oxide scheme.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: March 31, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Chia Ching Yeo, Khee Yong Lim, Kiok Boone Elgin Quek, Donald R. Disney
  • Patent number: 10566433
    Abstract: A semiconductor device includes a substrate having a first region and a second region, a first transistor formed in the first region and formed by a first gate line including a first lower metal-containing layer and a first upper metal-containing layer, and a second transistor formed in the second region and formed by a second gate line having an equal width to that of the first gate line and including a second lower metal-containing layer and a second upper metal-containing layer on the second upper metal-containing layer, wherein each of an uppermost end of the first upper metal-containing layer and an uppermost end of the second lower metal-containing layer has a higher level than an uppermost end of the first lower metal-containing layer.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-Hyuk Yim, Wan-Don Kim, Jong-Han Lee, Hyung-Suk Jung, Sang-Jin Hyun
  • Patent number: 10522558
    Abstract: A semiconductor device having a nonvolatile memory cell arranged in a p-type well (active region) PW1 in a memory cell region 1A in a semiconductor substrate 1 and an MISFET arranged in a p-type well PW2 (active region) or an n-type well (active region) in a peripheral circuit region 2A is constructed as follows. The surface of an element isolation region STI1 surrounding the p-type well PW1 is set lower than the surface of an element isolation region STI2 surrounding the p-type well PW2 or the n-type well (H1<H2). By making the surface of the element isolation region STI1 receded and lowered, the effective channel width of both a control transistor and a memory transistor can be increased. Since the surface of the element isolation region STI2 is not made receded, an undesired film can be prevented from being residual over a dummy gate electrode.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: December 31, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Tamotsu Ogata
  • Patent number: 10504897
    Abstract: An integrated circuit is provided, including a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and second pMOS transistors including a channel that is subjected to compressive stress and made of an SiGe alloy, and a gate of said transistors being positioned at least 250 nm from a border of an active zone of said transistors; a third pair including a third nMOS transistor having a same construction as the first nMOS transistor and a third pMOS transistor having a same construction as the second pMOS transistor and exhibiting a compressive stress that is lower by at least 250 MPa, the gate of said transistors of the third pair being positioned at most 200 nm from the border.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 10, 2019
    Assignees: Commissariat A L'Energie Atomique et aux Energies Alternatives, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Francois Andrieu, Remy Berthelon
  • Patent number: 10490674
    Abstract: A semiconductor device and its manufacturing method are presented. The manufacturing method entails: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region that are mutually exclusive from one another, with a first oxide layer on the first and the second regions; conducting a nitriding process on the semiconductor substrate to form a nitride barrier layer on the first oxide layer on the first and the second regions; removing the first oxide layer on the second region; and conducting an oxidation process to form a second oxide layer on the second region.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: November 26, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Guo Bin Yu, Xiao Ping Xu
  • Patent number: 10446548
    Abstract: An integrated circuit is provided, including: a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and the second nMOS transistors including a channel region made of silicon that is subjected to tensile stress, and their respective gates being positioned at least 250 nm from a border of their active zone; and a third pair including a third nMOS transistor having a same construction as the second nMOS transistor and a third pMOS transistor having a same construction as the first pMOS transistor and having a tensile stress that is lower by at least 250 MPa than the tensile stress of the channel region, respective gates of the transistors of the third pair being positioned at most 200 nm from a border of their active zone.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: October 15, 2019
    Assignees: Commissariat A L'Energie Atomique et aux Energies Alternatives, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Francois Andrieu, Remy Berthelon
  • Patent number: 10381476
    Abstract: A method of forming vertical transport fin field effect transistors, including, forming a bottom source/drain layer on a substrate, forming a channel layer on the bottom source/drain layer, forming a recess in the channel layer on a second region of the substrate, wherein the bottom surface of the recess is below the surface of the channel layer on a first region, forming a top source/drain layer on the channel layer, where the top source/drain layer has a greater thickness on the second region of the substrate than on the first region of the substrate, and forming a vertical fin on the first region of the substrate, and a vertical fin on the second region of the substrate, wherein a first top source/drain is formed on the vertical fin on the first region, and a second top source/drain is formed on the vertical fin on the second region.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10340272
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A barrier layer is formed in a first region and a second region of a semiconductor substrate. The barrier layer formed in the first region is thinned before a step of forming a first work function layer on the barrier layer. The first work function layer formed on the first region is then removed. The process of thinning the barrier layer in the first region and the process of removing the first work function layer in the first region are performed separately for ensuring the coverage of the first work function layer in the second region. The electrical performance of the semiconductor device and the uniformity of the electrical performance of the semiconductor device may be improved accordingly.
    Type: Grant
    Filed: April 8, 2018
    Date of Patent: July 2, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hao Lin, Shou-Wei Hsieh, Hsin-Yu Chen
  • Patent number: 10276613
    Abstract: An image sensor and a method for forming an image sensor are provided. The image sensor includes a substrate, and the substrate includes a pixel region, a peripheral region and a boundary region, and the boundary region is formed between the pixel region and the peripheral region. The image sensor also includes a first gate stack structure formed in the pixel region and a second gate stack structure formed in the peripheral region. The second gate stack structure includes a high-k dielectric layer and a first metal layer.
    Type: Grant
    Filed: March 31, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Ming-Chyi Liu
  • Patent number: 10276447
    Abstract: A method of forming a semiconductor structure may include: forming a first dielectric layer having a first thickness over a substrate; removing a first portion of the first dielectric layer to expose a second region of the substrate; forming a second dielectric layer having a second thickness over the second region of the substrate; removing a second portion of the first dielectric layer to expose a third region of the substrate; forming a third dielectric layer having a third thickness over the third region of the substrate; and forming a first plurality of gate stacks comprising the first dielectric layer in a first region of the substrate, a second plurality of gate stacks comprising the second dielectric layer in the second region of the substrate, and a third plurality of gate stacks comprising the third dielectric layer in the third region of the substrate.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacting Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Po-Nien Chen, Bao-Ru Young
  • Patent number: 10263075
    Abstract: Methods of forming integrated chips include forming a respective stack of sheets in two regions, each stack having first layers and second layers. The second layers are etched away in the first region. The second region is annealed to change the composition of the first layers in the second region by interaction with the second layers in the second region. A gate stack is formed in the first and second region.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10263110
    Abstract: A strained semiconductor layer is produced from a semiconductor layer extending on an insulating layer. A thermal oxidization is performed on the semiconductor layer across its entire thickness to form two bars extending in a direction of a transistor width. Insulating trenches are formed in a direction of a transistor length. A strain of the strained semiconductor layer is induced in one implementation before the thermal oxidation is performed. Alternatively, the strain is induced after the thermal oxidation is performed. The insulating trenches serve to release a component of the strain extending in the direction of transistor width. A component of the strain extending in the direction of transistor length is maintained. The bars and trenches delimit an active area of the transistor include source, drain and channel regions.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: April 16, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Remy Berthelon, Didier Dutartre, Pierre Morin, Francois Andrieu, Elise Baylac
  • Patent number: 10262903
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an N-P boundary spacer structure used with finFET devices and methods of manufacture. The method includes forming a plurality of first fin structures, forming a blocking layer between a first fin structure of the plurality of fin structures and a second fin structure of the plurality of fin structures, and forming an epitaxial material on the first fin structure, while blocking the epitaxial material from extending onto the second fin structure by at least the blocking layer formed between the first fin structure and the second fin structure.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: April 16, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Judson R. Holt, Yi Qi, Hsien-Ching Lo, Jianwei Peng
  • Patent number: 10211320
    Abstract: A method of forming semiconductor fins is provided. Sacrificial fins are provided on a surface of substrate. A hard mask layer, formed around the sacrificial fins and the gaps therebetween, is made coplanar with a topmost surface of the sacrificial fins. A fin cut mask then covers a portion of the sacrificial fins and partly covers a sacrificial fin. Trenches are formed in the hard mask layer by removing sacrificial fins not covered by the fin cut mask and that portion of the sacrificial fin not partly covered by the fin cut mask. Spacers are formed on the sidewalls of the trenches and a plug is formed in the trench formed by removing that portion of the sacrificial fin not partly covered by the fin cut mask. Semiconductor fins are grown epitaxially in the trenches having the spacers from the exposed surface of the substrate upward.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Alexander Reznicek, Dominic J. Schepis
  • Patent number: 10163725
    Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: December 25, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Manoj Mehrotra, Charles Frank Machala, III, Rick L. Wise, Hiroaki Niimi
  • Patent number: 10157985
    Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a channel region comprising dopants of a first type. The MOSFET device further includes a gate dielectric over the channel region, and a gate over the gate dielectric. The MOSFET device further includes a source comprising dopants of a second type, and a drain comprising dopants of the second type, wherein the channel region is between the source and the drain. The MOSFET device further includes a deactivated region underneath the gate, wherein dopants within the deactivated region are deactivated.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Dhanyakumar Mahaveer Sathaiya, Kai-Chieh Yang, Wei-Hao Wu, Ken-Ichi Goto, Zhiqiang Wu, Yuan-Chen Sun
  • Patent number: 10090303
    Abstract: Semiconductor devices are fabricated with vertical field effect transistor (FET) devices having uniform structural profiles. Semiconductor fabrication methods for vertical FET devices implement a process flow to fabricate dummy fins within isolation regions to enable the formation of vertical FET devices with uniform structural profiles within device regions. Sacrificial semiconductor fins are formed in the isolation regions concurrently with semiconductor fins in the device regions, to minimize/eliminate micro-loading effects from an etch process used for fin patterning and, thereby, form uniform profile semiconductor fins. The sacrificial semiconductor fins within the isolation regions also serve to minimize/eliminate non-uniform topography and micro-loading effects when planarizing and recessing conductive gate layers and, thereby. form conductive gate structures for vertical FET devices with uniform gate lengths in the device regions.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: October 2, 2018
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 10056298
    Abstract: A manufacturing method of a semiconductor device comprises a step of ion-implanting a P-type impurity at a first dose amount to form semiconductor regions that are low concentration semiconductor regions of a high breakdown voltage P-type transistor, and a step of ion-implanting a P-type impurity at a second dose amount to form P? semiconductor regions that are low concentration semiconductor regions of a low breakdown voltage P-type transistor and form a P-type impurity layer that is a resistance portion of a polysilicon resistor. The manufacturing method further comprises a resistance portion forming step in which a resistance portion of the polysilicon resistor is made thinner than terminal portions at both ends of the resistance portion, and the second dose amount is larger than the first dose amount.
    Type: Grant
    Filed: August 26, 2017
    Date of Patent: August 21, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Tohru Kawai
  • Patent number: 10014297
    Abstract: One aspect of the disclosure is directed to a method of forming an integrated circuit structure. The method may include: providing a set of fins over a semiconductor substrate, the set of fins including a plurality of working fins and a plurality of dummy fins, the plurality of dummy fins including a first subset of dummy fins within a pre-defined distance from any of the plurality of working fins, and a second subset of dummy fins beyond the pre-defined distance from any of the plurality of working fins; removing the first subset of dummy fins by an extreme ultraviolet (EUV) lithography technique; and removing at least a portion of the second subset of dummy fins.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: July 3, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Lei Sun, Wenhui Wang, Xunyuan Zhang, Ruilong Xie, Jia Zeng, Xuelian Zhu, Min Gyu Sung, Shao Beng Law
  • Patent number: 9985027
    Abstract: A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is formed on the fin, and an interlayer dielectric layer is formed on the epitaxial layer. Spacers on the fin define the narrow channel and the long channel. A high-k dielectric material is deposited in the narrow and long channels. A metal layer is deposited on the high-k dielectric material in the narrow and long channels. A height of the high-k dielectric material in the narrow channel is recessed. The metal layer is removed from the narrow and long channels. A work function metal is deposited in the narrow and long channels. A gate conduction metal is deposited to fill the narrow channel and long channel. A capping layer is deposited on the top surface of the structure.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su Chen Fan, Sivananda K. Kanakasabapathy, Injo Ok, Tenko Yamashita
  • Patent number: 9947651
    Abstract: A semiconductor integrated circuit device with a “PAD on I/O cell” structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor chip. When seen in a plan view of the I/O part, a resistance lies above the transistor and a first and a second diode lie above the resistance; a second transistor lies above the diodes; and a logic block lies above the second transistor with a pad lead part, for example, formed in a metal wiring layer, therebetween. This permits the pad through the second transistor to be on the same node and therefore the pad lead part can be disposed almost in the center of the I/O part.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: April 17, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Takeo Toba, Kazuo Tanaka, Hiroyasu Ishizuka
  • Patent number: 9865695
    Abstract: An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: January 9, 2018
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Chia-Hong Jan, Anisur Rahman
  • Patent number: 9837322
    Abstract: A semiconductor arrangement is provided comprising a guard region. The semiconductor arrangement comprises an active region disposed on a first side of the guard region. The active region comprises an active device. The guard region of the semiconductor arrangement comprises residue from the active region. A method of forming a semiconductor arrangement is also provided.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Chin-Yi Huang, Shih-Chang Liu
  • Patent number: 9812524
    Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: November 7, 2017
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Kelin J. Kuhn, Seiyon Kim, Anand S. Murthy, Daniel B. Aubertine
  • Patent number: 9761495
    Abstract: A method includes forming a plurality of fins above a substrate. A plurality of gate structures is formed above the plurality of fins. A first mask layer is formed above the plurality of fins and the plurality of gate structures. The first mask layer has at least one fin cut opening and at least one gate cut opening defined therein. A first portion of a first fin of the plurality of fins disposed below the fin cut opening is removed to define a fin cut cavity. A second portion of a first gate structure of the plurality of gate structures disposed below the gate cut opening is removed to define a gate cut cavity. An insulating material layer is concurrently formed in at least a portion of the fin cut cavity and the gate cut cavity.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: September 12, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Min Gyu Sung, Catherine B. Labelle, Chanro Park, Hoon Kim
  • Patent number: 9728462
    Abstract: A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is formed on the fin, and an interlayer dielectric layer is formed on the epitaxial layer. Spacers on the fin define the narrow channel and the long channel. A high-k dielectric material is deposited in the narrow and long channels. A metal layer is deposited on the high-k dielectric material in the narrow and long channels. A height of the high-k dielectric material in the narrow channel is recessed. The metal layer is removed from the narrow and long channels. A work function metal is deposited in the narrow and long channels. A gate conduction metal is deposited to fill the narrow channel and long channel. A capping layer is deposited on the top surface of the structure.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: August 8, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su Chen Fan, Sivananda K. Kanakasabapathy, Injo Ok, Tenko Yamashita
  • Patent number: 9691756
    Abstract: The nonvolatile memory device includes a memory cell having a transistor in which an insulating isolation layer is formed in a channel region. The nonvolatile memory device includes a metal-oxide-semiconductor (MOS) transistor as a basic component. An insulating isolation layer is formed in at least a channel region, and a gate insulating layer includes an insulating layer or a variable resistor and serves as a data storage. A gate includes a metal layer formed in a lower portion thereof. First source and drain regions are lightly doped with a dopant, and second source and drain regions are heavily doped with a dopant.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: June 27, 2017
    Assignee: Rangduru Inc.
    Inventor: Euipil Kwon
  • Patent number: 9673246
    Abstract: A method for fabricating a semiconductor device with improved bonding ability is disclosed. The method comprises providing a substrate having a front surface and a back surface; forming one or more sensor elements on the front surface of the substrate; forming one or more metallization layers over the front surface of the substrate, wherein forming a first metallization layer comprises forming a first conductive layer over the front surface of the substrate; removing the first conductive layer from a first region of the substrate; forming a second conductive layer over the front surface of the substrate; and removing portions of the second conductive layer from the first region and a second region of the substrate, wherein the first metallization layer in the first region comprises the second conductive layer and the first metallization layer in the second region comprises the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: June 6, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang, Jhy-Ming Hung, Pao-Tung Chen
  • Patent number: 9666690
    Abstract: An integrated circuit includes a first replacement gate structure. The first replacement gate structure includes a layer of a first barrier material that is less than 20 ? in thickness and a layer of a p-type workfunction material. The replacement gate structure is less than about 50 nm in width.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: May 30, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Hoon Kim, Kisik Choi
  • Patent number: 9659769
    Abstract: A highly tensile dielectric layer is generated on a heat sensitive substrate while not exceeding thermal budget constraints. Ultraviolet (UV) irradiation is used to produce highly tensile films to be used, for example, in strained NMOS transistor architectures. UV curing of as-deposited PECVD silicon nitride films, for example, has been shown to produce films with stresses of at least 1.65 E10 dynes/cm2. Other dielectric capping layer film materials show similar results. In transistor implementations, the stress from a source/drain region capping layer composed of such a film is uniaxially transferred to the NMOS channel through the source-drain regions to create tensile strain in the NMOS channel.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: May 23, 2017
    Assignee: Novellus Systems, Inc.
    Inventors: Bhadri Varadarajan, Sean Chang, James S. Sims, Guangquan Lu, David Mordo, Kevin Ilcisin, Mandar Pandit, Michael Carris
  • Patent number: 9653461
    Abstract: An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Tung Ying Lee
  • Patent number: 9640527
    Abstract: An electrostatic discharge (ESD) protection device includes a first trigger element and a first silicon control rectifier (SCR) element. The first trigger element has a first parasitic bipolar junction transistor (BJT) formed in a substrate. The first SCR element has a second parasitic BJT formed in the substrate. The first parasitic BJT and the second parasitic BJT has a common parasitic bipolar base, and the first parasitic BJT has a trigger voltage substantially lower than that of the second parasitic BJT.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: May 2, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Ting Lin, Yi-Chun Chen, Tien-Hao Tang
  • Patent number: 9576952
    Abstract: Integrated circuits and fabrication methods are provided. The integrated circuit includes: a varying gate structure disposed over a substrate structure, the varying gate structure including a first gate stack in a first region of the substrate structure, and a second gate stack in a second region of the substrate structure; a first field-effect transistor in the first region, the first field-effect transistor including the first gate stack and having a first threshold voltage; and a second field-effect transistor in the second region, the second field-effect transistor including the second gate stack and having a second threshold voltage, where the first threshold voltage is different from the second threshold voltage. The methods include providing the varying gate structure, the providing including: sizing layer(s) of the varying gate structure with different thickness(es) in different region(s).
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Manoj Joshi, Manfred Eller, Richard J. Carter, Srikanth Balaji Samavedam
  • Patent number: 9536791
    Abstract: A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is formed on the fin, and an interlayer dielectric layer is formed on the epitaxial layer. Spacers on the fin define the narrow channel and the long channel. A high-k dielectric material is deposited in the narrow and long channels. A metal layer is deposited on the high-k dielectric material in the narrow and long channels. A height of the high-k dielectric material in the narrow channel is recessed. The metal layer is removed from the narrow and long channels. A work function metal is deposited in the narrow and long channels. A gate conduction metal is deposited to fill the narrow channel and long channel. A capping layer is deposited on the top surface of the structure.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: January 3, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su Chen Fan, Sivananda K. Kanakasabapathy, Injo Ok, Tenko Yamashita