Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) Patents (Class 438/197)
  • Patent number: 12021082
    Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Hou-Yu Chen, Yong-Yan Lu
  • Patent number: 11955488
    Abstract: We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on th
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: April 9, 2024
    Assignee: CAMBRIDGE GAN DEVICES LIMITED
    Inventors: Florin Udrea, Loizos Efthymiou
  • Patent number: 11935947
    Abstract: An enhancement mode high electron mobility transistor (HEMT) includes a group III-V semiconductor body, a group III-V barrier layer and a gate structure. The group III-V barrier layer is disposed on the group III-V semiconductor body, and the gate structure is a stacked structure disposed on the group III-V barrier layer. The gate structure includes a gate dielectric and a group III-V gate layer disposed on the gate dielectric, and the thickness of the gate dielectric is between 15 nm to 25 nm.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: March 19, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Shin-Chuan Huang, Wen-Jung Liao, Chun-Liang Hou
  • Patent number: 11901415
    Abstract: The present disclosure is directed to methods for the fabrication of buried layers in gate-all-around (GAA) transistor structures to suppress junction leakage. In some embodiments, the method includes forming a doped epitaxial layer on a substrate, forming a stack of alternating first and second nano-sheet layers on the epitaxial layer, and patterning the stack and the epitaxial layer to form a fin structure. The method includes forming a sacrificial gate structure on the fin structure, removing portions of the fin structure not covered by the sacrificial gate structure, and etching portions of the first nano-sheet layers. Additionally, the method includes forming spacer structures on the etched portions of the first nano-sheet layers and forming source/drain (S/D) epitaxial structures on the epitaxial layer abutting the second nano-sheet layers.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ta Yu, Yen-Chieh Huang, Yi-Hsien Tu, I-Hsieh Wong
  • Patent number: 11837155
    Abstract: Provided is a display apparatus including a plurality of subpixels and configured to emit light based on each of the plurality of subpixels, the display apparatus including a substrate, a driving layer provided on the substrate and including a driving element which is configured to apply current to the display apparatus, a first electrode electrically connected to the driving layer, a first semiconductor layer provided on the first electrode, an active layer provided on the first semiconductor layer, a second semiconductor layer provided on the active layer, a second electrode provided on the second semiconductor layer, and a reflective layer provided on the second semiconductor layer, wherein light emitted from the active layer resonates between the first electrode and the reflective layer.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: December 5, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junhee Choi, Kiho Kong, Nakhyun Kim, Junghun Park, Jinjoo Park, Joohun Han
  • Patent number: 11804534
    Abstract: A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: October 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Han Lin, Shih-Chang Tsai, Wen-Shuo Hsieh, Te-Yung Liu
  • Patent number: 11756833
    Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: September 12, 2023
    Assignee: Intel Corporation
    Inventors: Sridhar Govindaraju, Matthew J. Prince
  • Patent number: 11705361
    Abstract: Gate patterns are formed on a semiconductor layer and a conductive film is formed on the semiconductor layer so as to cover the gate patterns. By performing a polishing process to the conductive film and patterning the polished conductive film, pad layers are formed between the gate patterns via sidewall spacers.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: July 18, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hitoshi Maeda, Tatsuyoshi Mihara, Hiroki Shinkawata
  • Patent number: 11688764
    Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: June 27, 2023
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Cheng Tung, Yun-Fan Chou, Te-Hao Huang, Hsien-Shih Chu, Feng-Ming Huang
  • Patent number: 11664459
    Abstract: A method for making a semiconductor device may include forming an inverted T channel on a substrate, with the inverted T channel comprising a superlattice. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming source and drain regions on opposing ends of the inverted T channel, and forming a gate overlying the inverted T channel between the source and drain.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: May 30, 2023
    Assignee: ATOMERA INCORPORATED
    Inventor: Robert John Stephenson
  • Patent number: 11595038
    Abstract: A control system includes a control unit. When turning a bidirectional switch element ON, the control unit controls the bidirectional switch element to cause a time lag between a first timing and a second timing. The first timing is a timing when a voltage equal to or higher than a threshold voltage is applied to one gate electrode selected from a first gate electrode and a second gate electrode. The one gate electrode is associated with one source electrode selected from a first source electrode and a second source electrode and having a lower potential than the other source electrode. The second timing is a timing when a voltage equal to or higher than a threshold voltage is applied to the other gate electrode associated with the other source electrode having a higher potential than the one source electrode.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: February 28, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yusuke Kinoshita, Yasuhiro Yamada, Hidekazu Umeda
  • Patent number: 11574907
    Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: February 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Hou-Yu Chen, Yong-Yan Lu
  • Patent number: 11557658
    Abstract: Transistors having a plurality of channel semiconductor structures, such as fins, over a dielectric material. A source and drain are coupled to opposite ends of the structures and a gate stack intersects the plurality of structures between the source and drain. Lateral epitaxial overgrowth (LEO) may be employed to form a super-lattice of a desired periodicity from a sidewall of a fin template structure that is within a trench and extends from the dielectric material. Following LEO, the super-lattice structure may be planarized with surrounding dielectric material to expose a top of the super-lattice layers. Alternating ones of the super-lattice layers may then be selectively etched away, with the retained layers of the super-lattice then laterally separated from each other by a distance that is a function of the super-lattice periodicity. A gate dielectric and a gate electrode may be formed over the retained super-lattice layers for a channel of a transistor.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: January 17, 2023
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Sean T. Ma, Tahir Ghani, Willy Rachmady, Cheng-Ying Huang, Anand S. Murthy, Harold W. Kennel, Nicholas G. Minutillo, Matthew V. Metz
  • Patent number: 11545554
    Abstract: A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: January 3, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doosan Back, Dongoh Kim, Gyuhyun Kil, Jung-Hoon Han
  • Patent number: 11502197
    Abstract: The present disclosure is directed to semiconductor structures with source/drain epitaxial stacks having a low-melting point top layer and a high-melting point bottom layer. For example, a semiconductor structure includes a gate structure disposed on a fin and a recess formed in a portion of the fin not covered by the gate structure. Further, the semiconductor structure includes a source/drain epitaxial stack disposed in the recess, where the source/drain epitaxial stack has bottom layer and a top layer with a higher activated dopant concentration than the bottom layer.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Hsien Tu, Chee-Wee Liu, Fang-Liang Lu
  • Patent number: 11495606
    Abstract: A semiconductor device includes a layer having a semiconductive material. The layer includes an outwardly-protruding fin structure. An isolation structure is disposed over the layer but not over the fin structure. A first spacer and a second spacer are each disposed over the isolation structure and on sidewalls of the fin structure. The first spacer is disposed on a first sidewall of the fin structure. The second spacer is disposed on a second sidewall of the fin structure opposite the first sidewall. The second spacer is substantially taller than the first spacer. An epi-layer is grown on the fin structure. The epi-layer protrudes laterally. A lateral protrusion of the epi-layer is asymmetrical with respect to the first side and the second side.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Po Chang, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Wei-Yang Lee, Tzu-Hsiang Hsu
  • Patent number: 11469210
    Abstract: A semiconductor package includes a first interposer, a second interposer, and a gap between the first interposer and the second interposer. The first interposer and the second interposer are coplanar. A first die is mounted on the first interposer and the second interposer. The first die includes first connection elements connecting the first die to the first interposer or the second interposer. A redistribution layer (RDL) structure is disposed on bottom surfaces of the first and second interposers for connecting the first interposer with the second interposer. The RDL structure includes at least one bridge trace traversing the gap to electrically connect the first interposer with the second interposer.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: October 11, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Shing-Yih Shih
  • Patent number: 11462438
    Abstract: Methods of producing a self-aligned structure are described. The methods comprise forming a metal-containing film in a substrate feature and silicidizing the metal-containing film to form a self-aligned structure comprising metal silicide. In some embodiments, the rate of formation of the self-aligned structure is controlled. In some embodiments, the amount of volumetric expansion of the metal-containing film to form the self-aligned structure is controlled. Methods of forming self-aligned vias are also described.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: October 4, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Susmit Singha Roy, Srinivas Gandikota, Abhijit Basu Mallick, Amrita B. Mullick
  • Patent number: 11462601
    Abstract: An organic light emitting diode display includes a substrate, a semiconductor layer disposed on the substrate, a first insulating layer which covers the semiconductor layer, a first conductive layer disposed on the first insulating layer, a second insulating layer which covers the first conductive layer, a second conductive layer disposed on the second insulating layer, a third insulating layer which covers the second conductive layer, a third conductive layer disposed on the third insulating layer, a first organic layer which covers the third conductive layer, and a fourth conductive layer disposed on the first organic layer, where the fourth conductive layer includes a lower layer, a middle layer, and an upper layer, and the lower layer is disposed between the first organic layer and the middle layer, and includes a transparent conductive oxidization film.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: October 4, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sang-Ho Moon, Chun Gi You, Tae Kon Kim
  • Patent number: 11430374
    Abstract: Provided is a display apparatus including a plurality of subpixels and configured to emit light based on each of the plurality of subpixels, the display apparatus including a substrate, a driving layer provided on the substrate and including a driving element which is configured to apply current to the display apparatus, a first electrode electrically connected to the driving layer, a first semiconductor layer provided on the first electrode, an active layer provided on the first semiconductor layer, a second semiconductor layer provided on the active layer, a second electrode provided on the second semiconductor layer, and a reflective layer provided on the second semiconductor layer, wherein light emitted from the active layer resonates between the first electrode and the reflective layer.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: August 30, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junhee Choi, Kiho Kong, Nakhyun Kim, Junghun Park, Jinjoo Park, Joohun Han
  • Patent number: 11417685
    Abstract: A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: August 16, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Chung-Liang Chu, Zen-Jay Tsai, Yu-Hsiang Lin
  • Patent number: 11404555
    Abstract: A semiconductor structure includes a high-k metal gate structure (HKMG) disposed over a channel region of a semiconductor layer formed over a substrate, where the HKMG includes an interfacial layer disposed over the semiconductor layer, a high-k dielectric layer disposed over the interfacial layer, and a gate electrode disposed over the high-k dielectric layer, where a length of the high-k dielectric layer is greater than a length of the gate electrode and where outer edges of the interfacial layer, the high-k dielectric layer, and the gate electrode form a step profile. The semiconductor structure further includes gate spacers having sidewall portions contacting sidewalls of the gate electrode and bottom portions contacting top portions of the high-k dielectric layer and the interfacial layer, and source/drain features disposed in the semiconductor layer adjacent to the HKMG.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jen-Hsiang Lu, Tsung-Han Tsai, Shih-Hsun Chang
  • Patent number: 11393934
    Abstract: This disclosure illustrates a FinFET based dual electronic component that may be used as a capacitor or a resistor and methods to manufacture said component. A FinFET based dual electronic component comprises a fin, source and drain regions, a gate dielectric, and a gate. The fin is heavily doped such that semiconductor material of the fin becomes degenerate.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Ayan Kar, Kinyip Phoa, Justin S. Sandford, Junjun Wan, Akm A. Ahsan, Leif R. Paulson, Bernhard Sell
  • Patent number: 11374126
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate, wherein the semiconductor fin includes a channel region and a source/drain region; a gate structure disposed over the channel region of the semiconductor fin, wherein the gate structure includes a gate spacer and a gate stack; a source/drain structure disposed over the source/drain region of the semiconductor fin; and a fin top hard mask vertically interposed between the gate spacer and the semiconductor fin, wherein the fin top hard mask includes a dielectric layer, and wherein a sidewall of the fin top hard mask directly contacts the gate stack, and another sidewall of the fin top hard mask directly contacts the source/drain structure.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Yu Yang, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 11367783
    Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure is sculpted to have a plurality of non-etched portions and a plurality of etched portions having a narrower width than the plurality of non-etched portions. The sculpted fin structure is oxidized so that a plurality of nanowires are formed in the plurality of non-etched portions, respectively, and the plurality of etched portions are oxidized to form oxides. The plurality of nanowires are released by removing the oxides.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: June 21, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Ling-Yen Yeh
  • Patent number: 11362178
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to asymmetric source and drain structures and methods of manufacture. The structure includes: at least one gate structure; a straight spacer adjacent to the at least one gate structure; and an L-shaped spacer on a side of the at least one gate structure opposing the straight spacer, the L-shaped spacer extending a first diffusion region further away from the at least one gate structure than the straight spacer extends a second diffusion region on a second side away from the at least one gate structure.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: June 14, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Jiehui Shu, Rinus Tek Po Lee, Baofu Zhu
  • Patent number: 11355442
    Abstract: An interconnect structure is provided. The interconnect structure includes first conducting lines and second conducting lines. The first conducting lines are formed of a first metallic material and include at least one individual first conducting line in contact with a first corresponding substrate conducting line. The second conducting lines are formed of a second metallic material and include at least one individual second conducting line between neighboring first conducting lines and in contact with a second corresponding substrate conducting line. The at least one individual second conducting line is separated from each of the neighboring first conducting lines by controlled distances.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: June 7, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ashim Dutta, Ekmini Anuja De Silva
  • Patent number: 11355596
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate dielectric, a gate electrode, a field plate dielectric layer, and a field plate. The gate dielectric layer is arranged over a substrate and between a source region and a drain region. The gate electrode is arranged over the gate dielectric layer. The field plate dielectric layer is arranged over the substrate and between the gate dielectric layer and the drain region. The field plate is arranged over the field plate dielectric layer and is spaced apart from the gate dielectric layer.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ming Chyi Liu
  • Patent number: 11349026
    Abstract: An electronic device includes a ferroelectric layer arranged on a channel region and a gate electrode arranged on the ferroelectric layer. The ferroelectric layer includes a plurality of first oxide monolayers and a second oxide monolayers that is arranged between the substrate and the gate electrode and include a material different from a material of the first oxide monolayers. The first oxide monolayers include oxide monolayers that are alternately formed and include materials different from one another.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: May 31, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yunseong Lee, Jinseong Heo, Sangwook Kim, Sanghyun Jo
  • Patent number: 11322702
    Abstract: Electrical device including a substrate having a surface and a radiofrequency field effect transistor (RF-FET) on the substrate surface. RF-FET includes a CNT layer on the substrate surface, the CNT layer including electrically conductive aligned carbon nanotubes, and pin-down anchor layers on the CNT layer. A first portion of the CNT layer, located in-between the pin-down anchor layers, is not covered by the pin-down anchor layers and is a channel region of the radiofrequency field effect transistor and second portions of the CNT layer are covered by the pin-down anchor layers. For cross-sections in a direction perpendicular to a common alignment direction of the aligned CNTs in the first portion of the CNT layer: the aligned CNTs have an average linear density in a range from 20 to 120 nanotubes per micron along the cross-section, and at least 40 percent of the aligned CNTs are discrete from any CNTs of the CNT layer.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: May 3, 2022
    Assignee: Carbonics Inc.
    Inventors: Alexander Allen Kane, Christopher Michael Rutherglen, Tyler Andrew Cain, Philbert Francis Marsh, Kosmas Galatsis
  • Patent number: 11322412
    Abstract: A method includes forming a dummy gate stack over a semiconductor region of a wafer, and depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack. The depositing the gate spacer layer includes performing an ALD cycle to form a dielectric atomic layer. The ALD cycle includes introducing silylated methyl to the wafer, purging the silylated methyl, introducing ammonia to the wafer, and purging the ammonia.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yi Kao, Chung-Chi Ko
  • Patent number: 11302819
    Abstract: A first transistor and a second transistor are stacked. The first transistor and the second transistor have a gate electrode in common. At least one of semiconductor films used in the first transistor and the second transistor is an oxide semiconductor film. With the use of the oxide semiconductor film as the semiconductor film in the transistor, high field-effect mobility and high-speed operation can be achieved. Since the first transistor and the second transistor are stacked and have the gate electrode in common, the area of a region where the transistors are disposed can be reduced.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: April 12, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Seiichi Yoneda
  • Patent number: 11302820
    Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes depositing a light blocking layer along sidewalls and bottom surfaces of the source/drain contact openings and a topmost surface of the at least one dielectric layer. The method further includes performing a laser annealing process to activate dopants in the source/drain contact region. The method further includes forming source/drain contact structures within source/drain contact openings.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Blandine Duriez, Marcus Johannes Henricus Van Dal, Martin Christopher Holland, Gerben Doornbos, Georgios Vellianitis
  • Patent number: 11296194
    Abstract: The present invention relates to a method for manufacturing a nonvolatile memory, including the steps of: forming a gate oxide layer on a substrate; forming a stacked capacitor of a storage cell after making a logic gate polysilicon undertake at least two deposition processes; and removing the extra logic gate polysilicon by an etching process to form a storage transistor and a peripheral logic transistor. According to the method of the present invention, the stacked capacitor of the storage transistor is formed by depositing at least twice, and the memory is manufactured in a standard logic process, which makes the manufacturing process of the memory simpler, the memory has good compatibility with the logic process and has low cost.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: April 5, 2022
    Assignee: Chengdu Analog Circuit Technology Inc
    Inventors: Dan Ning, Tengfeng Wang
  • Patent number: 11289480
    Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Shih-Hang Chiu, Chih-Chang Hung, I-Wei Yang, Shu-Yuan Ku, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 11282950
    Abstract: Provided is a technology for obtaining a drain current of a sufficient magnitude in a field effect transistor using a nitride semiconductor. A channel layer that is Alx1Iny1Ga1-x1-y1N is formed on an upper surface of a semiconductor substrate, and on an upper surface of the channel layer, a barrier layer that is Alx2Iny2Ga1-x2-y2N having a band gap larger than that of the channel layer is formed. Then, on an upper surface of the barrier layer, a gate insulating film that is an insulator or a semiconductor and has a band gap larger than that of the barrier layer is at least partially formed, and a gate electrode is formed on an upper surface of the gate insulating film. Then, heat treatment is performed while a positive voltage is applied to the gate electrode.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: March 22, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takuma Nanjo, Tetsuro Hayashida, Koji Yoshitsugu, Akihiko Furukawa
  • Patent number: 11276783
    Abstract: A semiconductor device includes: a first conductivity type semiconductor of a nanostructure; a first electrode that is in ohmic junction with an end part of the first conductivity type semiconductor; a second electrode that is coupled to the first electrode and is provided over a side surface of the first conductivity type semiconductor; and a depletion constituent that controls expansion of a depletion layer inside the nanostructure, wherein the depletion layer is expanded inside the first conductivity type semiconductor by the depletion constituent in a direction intersecting a movement direction of a carrier.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: March 15, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Tsuyoshi Takahashi, Kenichi Kawaguchi
  • Patent number: 11271080
    Abstract: A silicon carbide semiconductor device includes a gate insulating film and a gate electrode made of p+ polysilicon doped with boron at a high concentration. Among boron impurities contained in the polysilicon of the gate electrode, 11B, which is one of the isotopes of boron, is contained 90% or more, thereby reducing the amount of 10B diffusing from the polysilicon of the gate electrode into the gate insulating film. This results in a suppression of a threshold voltage shift that occurs when AC voltage is applied to the gate electrode.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: March 8, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tsuyoshi Araoka
  • Patent number: 11264501
    Abstract: Techniques and mechanisms for imposing stress on a channel region of an NMOS transistor. In an embodiment, a fin structure on a semiconductor substrate includes two source or drain regions of the transistor, wherein a channel region of the transistor is located between the source or drain regions. At least on such source or drain region includes a doped silicon germanium (SiGe) compound, wherein dislocations in the SiGe compound result in the at least one source or drain region exerting a tensile stress on the channel region. In another embodiment, source or drain regions of a transistor each include a SiGe compound which comprises at least 50 wt % germanium.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Anand Murthy, Karthik Jambunathan, Cory Bomberger
  • Patent number: 11239359
    Abstract: Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: February 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Jingyun Zhang, Choonghyun Lee, Takashi Ando, Pouya Hashemi, Alexander Reznicek
  • Patent number: 11239191
    Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.
    Type: Grant
    Filed: July 3, 2020
    Date of Patent: February 1, 2022
    Assignee: Renesas Electronics Corporation
    Inventor: Shinya Suzuki
  • Patent number: 11233111
    Abstract: An array substrate, a manufacturing method of an array substrate, and a display panel are provided. The array substrate includes: a deformable substrate, the deformable substrate including a first region and a second region, the first region being provided with a plurality of voids, the second region being a region of the deformable substrate not provided with the plurality of voids; an electronic element on the second region of the deformable substrate.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: January 25, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Pinfan Wang, Ming Che Hsieh
  • Patent number: 11227833
    Abstract: A method for forming an interconnect structure is provided. The method for forming the interconnect structure includes forming a first dielectric layer over a substrate, forming a first conductive feature through the first dielectric layer, forming a first blocking layer on the first conductive feature, forming a first etching stop layer over the first dielectric layer and exposing the first blocking layer, removing at least a portion of the first blocking layer, forming a first metal bulk layer over the first etching stop layer and the first conductive feature, and etching the first metal bulk layer to form a second conductive feature electrically connected to the first conductive feature.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Kuan Lee, Cheng-Chin Lee, Hsin-Yen Huang, Hai-Ching Chen, Shau-Lin Shue
  • Patent number: 11211380
    Abstract: A method for manufacturing a semiconductor structure includes forming a plurality of dummy semiconductor fins on a substrate. The dummy semiconductor fins are adjacent to each other and are grouped into a plurality of fin groups. The dummy semiconductor fins of the fin groups are recessed one group at a time.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Po-Chi Wu, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 11177164
    Abstract: Processing methods to form self-aligned high aspect ratio features are described. The methods comprise depositing a metal film on a structured substrate, volumetrically expanding the metal film, depositing a second film between the expanded pillars and optionally recessing the pillars and repeating the process to form the high aspect ratio features.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: November 16, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Susmit Singha Roy, Praburam Gopalraja, Abhijit Basu Mallick, Srinivas Gandikota
  • Patent number: 11171204
    Abstract: A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: November 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Sanjay C. Mehta, Xin Miao, Chun-Chen Yeh
  • Patent number: 11171179
    Abstract: A memory array includes: a plurality of first wires; at least one second wire crossing the first wires; and a plurality of memory elements provided in correspondence with respective intersections of the first wires and the at least one second wire and each having a first electrode and a second electrode arranged spaced apart from each other, a third electrode connected to one of the at least one second wire, and an insulating layer that electrically insulates the first electrode and the second electrode and the third electrode from each other, the first wires, the at least one second wire, and the first wires, the at least one second wire, and the memory elements being formed on a substrate.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: November 9, 2021
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Shota Kawai, Seiichiro Murase, Hiroji Shimizu
  • Patent number: 11169408
    Abstract: A display device panel includes a display area including pixels and a non-display area. Each pixel is connected to one of gate lines and one of data lines. The non-display area includes data pad sections. The non-display area further includes a depiction of a first information code and a depiction of a second information code. The depiction of the first information code is disposed between first two adjacent data pad sections and is apart from an outline of the non-display area by a first distance. The depiction of the second information code is disposed between second two adjacent data pad sections and is apart from the outline of the non-display area by a second distance different from the first distance.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: November 9, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kang Young Lee, Sang Hyun Kang, Dae Hyun Kim, Seung Hwan Kim, Joo Yeol Lee, Jang Bog Ju
  • Patent number: 11158727
    Abstract: The present disclosure provides a method of semiconductor fabrication that includes forming a semiconductor fin protruding from a substrate, the semiconductor fin including a plurality of first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked, the second semiconductor material being different from the first semiconductor material in composition; forming a first gate stack on the semiconductor fin; forming a recess in the semiconductor fin within a source/drain (S/D) region adjacent to the first gate stack, a sidewall of the first and second semiconductor material layers being exposed within the recess; performing an etching process to the semiconductor fin, resulting in an undercut below the first gate stack; epitaxially growing on the sidewall of the semiconductor fin to fill in the undercut with a semiconductor extended feature of the first semiconductor material; and growing an epitaxial S/D feature from the rece
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Hsun Wang, Chih-Chao Chou, Chun-Hsiung Lin, Ching-Wei Tsai, Chih-Hao Wang
  • Patent number: 11152460
    Abstract: A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Sanjay C. Mehta, Xin Miao, Chun-Chen Yeh