Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) Patents (Class 438/197)
  • Patent number: 11004748
    Abstract: This disclosure relates to a method of fabricating semiconductor devices with a gate-to-gate spacing that is wider than a minimum gate-to-gate spacing and the resulting semiconductor devices. The method includes forming gate structures over an active structure, the gate structures including a first gate structure, a second gate structure, and a third gate structure. The second gate structure is between the first and third gate structures. A plurality of epitaxial structures are formed adjacent to the gate structures, wherein the second gate structure separates two epitaxial structures and the two epitaxial structures are between the first and third gate structures. The second gate structure is removed. A conductive region is formed to connect the epitaxial structures between the first and third gate structures.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: May 11, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Sipeng Gu, Jiehui Shu, Haiting Wang
  • Patent number: 10998428
    Abstract: Examples of an integrated circuit and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a substrate that includes: a plurality of fins extending above a remainder of the substrate; a first region that includes a first fence region that contains a first subset of the plurality of fins; and a second region that includes a second fence region that contains a second subset of the plurality of fins. The first region has a first performance characteristic, and the second region has a second performance characteristic that is different from the first. Based on the first performance characteristic, the first subset of the plurality of fins is recessed to a first height, and based on the second performance characteristic, the second subset of the plurality of fins is recessed to a second height that is less than the first height.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Wei-Chiang Hung, Wei-Hao Huang
  • Patent number: 10991711
    Abstract: Semiconductor structures and methods of making the same. The semiconductor structures including at least two vertically stacked nanosheet devices. In one embodiment, an integrated circuit includes a plurality of horizontal nanosheet devices (HNS devices) that are stacked vertically, on top of each other, relative to a top surface of a substrate. The plurality of HNS devices including a first HNS device and a second HNS device that each have source and drain structures.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: April 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan, Jeng-Bang Yau
  • Patent number: 10978344
    Abstract: A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Hao Liu, Wen-Yen Chen, Tz-Shian Chen, Cheng-Jung Sung, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Syun-Ming Jang
  • Patent number: 10964696
    Abstract: A semiconductor device includes a first channel region disposed over a substrate, a first source region and a first drain region disposed over the substrate and connected to the first channel region such that the first channel region is disposed between the first source region and the first drain region, a gate dielectric layer disposed on and wrapping the first channel region, a gate electrode layer disposed on the gate dielectric layer and wrapping the first channel region, and a second source region and a second drain region disposed over the substrate and below the first source region and the first drain region, respectively. The second source region and the second drain region are in contact with the gate dielectric layer. A lattice constant of the first source region and the first drain region is different from a lattice constant of the second source region and the second drain region.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Ka-Hing Fung
  • Patent number: 10957703
    Abstract: An example embodiment comprises a method for fabrication of a non-volatile memory (NVM) device. An isolation structure is formed in a substrate between first and second locations for first and second NVM cells. A common charge trapping layer is formed as a continuous structure over the substrate, where a first portion of the charge trapping layer is disposed directly over the isolation structure and second portions of the charge trapping layer are disposed directly over the first and second substrate locations. Nitrogen doping of the first portion of the charge trapping layer is performed, where after the nitrogen doping is performed the first portion of the charge trapping layer includes a higher nitrogen concentration than the second portions. The first and second NVM cells are then formed over the first and second substrate locations, where the first and second NVM cells include the second portions of the charge trapping layer.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: March 23, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Pawan Kishore Singh, Shivananda Shetty, James Pak
  • Patent number: 10957535
    Abstract: There is provided a method of forming a semiconductor film, including: a first process of supplying a first semiconductor raw material gas onto a substrate having recesses formed therein to form a first semiconductor film in each of the recesses, each of the recesses being covered with an insulating film; a second process of supplying a halogen-containing etching gas onto the substrate to etch the first semiconductor film while exposing a surface of the insulating film in an upper portion of an inner wall of each of the recesses and leaving the first semiconductor film formed on a bottom surface of each of the recesses; and a third process of simultaneously supplying a halogen-containing semiconductor gas and a semiconductor hydride gas onto the substrate to form a second semiconductor film on the first semiconductor film formed on the bottom surface of each of the recesses.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: March 23, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yutaka Motoyama, Younggi Hong
  • Patent number: 10956622
    Abstract: The present invention provides a thermal hardware-based data security device that is capable of physically, hardware-wise, and permanently erasing data stored in a memory and of enabling a storage device to be reused, and a method thereof. The thermal hardware-based data security device includes: a memory chip capable of storing data; a heater module which supplies heat to permanently erase the data stored in a memory cell within the memory chip; and a switch module which short-circuits the heater module between a power supply unit and a ground when switched on, and thus, controls the heater module to be operated.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: March 23, 2021
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Yang-Kyu Choi, Jun-Young Park
  • Patent number: 10957602
    Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor is a grading strained stressor including multiple graded portions formed at graded depths. The first stressor is configured to create one of a graded compressive stress or a graded tensile stress.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: March 23, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Che-Wei Yang, Hao-Hsiung Lin, Samuel C. Pan
  • Patent number: 10957600
    Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Chia Tai Lin, Chao-Cheng Chen
  • Patent number: 10930495
    Abstract: Examples of an integrated circuit with a gate structure and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate having a channel region. A gate dielectric is formed on the channel region, and a layer containing a dopant is formed on the gate dielectric. The workpiece is annealed to transfer the dopant to the gate dielectric, and the layer is removed after the annealing. In some such examples, after the layer is removed, a work function layer is formed on the gate dielectric and a fill material is formed on the work function layer to form a gate structure.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang Cheng, Yen-Yu Chen
  • Patent number: 10910479
    Abstract: A semiconductor device includes a substrate; a fin structure formed on a substrate; and a gate feature formed over the fin structure, the gate feature comprising a gate dielectric layer, wherein the gate dielectric layer traverses the fin structure to overlay a central portion of the fin structure and opposite side portions of the fin structure that are located in respective undercuts formed in respective portions of a dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend beyond respective sidewalls of the gate feature and away from the central portion of the fin structure.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: February 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Guan-Jie Shen, Chia-Der Chang, Chih-Hsiung Lin
  • Patent number: 10886180
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a plurality of fins on a substrate. A fin end spacer is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. A gate electrode layer is formed on the insulating layer and wrapping around the each channel region. Sidewall spacers are formed on the gate electrode layer.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: January 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Tzu-Chung Wang, Kai-Tai Chang, Wei-Sheng Yun
  • Patent number: 10861695
    Abstract: A method of forming a low-k layer includes forming a layer by providing a silicon source, a carbon source, an oxygen source, and a nitrogen source onto a substrate. The forming of the layer includes a plurality of main cycles, and each of the main cycles includes providing the silicon source, providing the carbon source, providing the oxygen source, and providing the nitrogen source, each of which is performed at least one time. Each of the main cycles includes sub-cycles in which the providing of the carbon source and the providing of the oxygen source are alternately performed.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: December 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunyoung Lee, Minjae Kang, Se-Yeon Kim, Teawon Kim, Yong-Suk Tak, Sunjung Kim
  • Patent number: 10861856
    Abstract: A method for fabricating a semiconductor device includes: forming a first conductive layer; forming a second conductive layer over the first conductive layer; forming a conductive line by etching the second conductive layer; etching a portion of the first conductive layer to form a plug head having the same critical dimension as the conductive line; forming a first spacer that covers the conductive line and the plug head; etching the remaining first conductive layer to form a plug body that is aligned with the first spacer, wherein the plug body have a greater critical dimension than the plug head; and forming a second spacer by performing a selective oxidation onto a side wall of the plug body.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventor: Jae-Houb Chun
  • Patent number: 10861984
    Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 ?m2.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: December 8, 2020
    Assignee: STMicroelectronics, Inc.
    Inventors: Qing Liu, John H. Zhang
  • Patent number: 10861928
    Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiao-Han Liu, Hoppy Lee, Chung-Yu Chiang, Po-Nien Chen, Chih-Yung Lin
  • Patent number: 10818755
    Abstract: A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: October 27, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
  • Patent number: 10811505
    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jonghan Lee, Wandon Kim, Jaeyeol Song, Jeonghyuk Yim, HyungSuk Jung
  • Patent number: 10811426
    Abstract: The present disclosure relates to a method of forming an integrated circuit (IC). In some embodiments, a substrate is provided comprising a memory region and a logic region disposed adjacent to the memory region. The memory region comprises a non-volatile memory (NVM) device having a control gate electrode and a select gate electrode disposed between two neighboring source/drain regions over a substrate. The control gate electrode and the select gate electrode comprise polysilicon. The logic region comprises a logic device including a metal gate electrode disposed between two neighboring source/drain regions over a logic gate dielectric and having bottom and sidewall surfaces covered by a high-k gate dielectric layer.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Cheng Wu, Chien-Hung Chang
  • Patent number: 10811751
    Abstract: Embodiments of the invention include an electromagnetic waveguide and methods of forming the electromagnetic waveguide. In an embodiment the electromagnetic waveguide includes a first spacer and a second spacer. In an embodiment, the first and second spacer each have a reentrant profile. The electromagnetic waveguide may also include a conductive body formed between in the first and second spacer, and a void formed within the conductive body. In an additional embodiment, the electromagnetic waveguide may include a first spacer and a second spacer. Additionally, the electromagnetic waveguide may include a first portion of a conductive body formed along sidewalls of the first and second spacer and a second portion of the conductive body formed between an upper portion of the first portion of the conductive body. In an embodiment, the first portion of the conductive body and the second portion of the conductive body define a void through the electromagnetic waveguide.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Rahul Ramaswamy, Chia-Hong Jan, Walid Hafez, Neville Dias, Hsu-Yu Chang, Roman Olac-Vaw, Chen-Guan Lee
  • Patent number: 10804354
    Abstract: A radio frequency resistor element comprises a resistive polysilicon trace, an isolation component and a semiconductor substrate. The resistive polysilicon trace is located above the isolation component. The isolation component is laterally at least partially surrounded by a modified semiconductor region located above the semiconductor substrate and having a higher charge carrier recombination rate than the semiconductor substrate.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: October 13, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Hans Taddiken, Martin Bartels, Andrea Cattaneo, Henning Feick, Christian Kuehn, Anton Steltenpohl
  • Patent number: 10797159
    Abstract: Methods of forming an EDNMOS with polysilicon fingers between a gate and a nitride spacer and the resulting devices are provided. Embodiments include forming a polysilicon layer upon a GOX layer over a substrate; forming a gate and plurality of fingers and a gate and plurality of fingers through the polysilicon layer down the GOX layer; forming an oxide layer over the GOX layer and sidewalls of the gates and fingers; forming a nitride layer over the oxide layer; removing portions of the nitride and oxide layers down to the polysilicon and GOX layers to form nitride spacers; and forming S/D regions laterally separated in the substrate, each S/D region adjacent to a nitride spacer.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Lin Wei, Upinder Singh, Raj Verma Purakh
  • Patent number: 10797052
    Abstract: A semiconductor device includes a substrate, an isolation structure over the substrate, and a first semiconductor layer over the substrate. At least a portion of the first semiconductor layer is surrounded by the isolation structure. The semiconductor device further includes a doped material layer between the isolation structure and the first semiconductor layer.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yong-Yan Lu, Chia-Wei Soong, Hou-Yu Chen
  • Patent number: 10790359
    Abstract: An intelligent semiconductor device has a body region in which a channel is formed. The body region has a heterojunction of different semiconductor layers and a quantum well formed in a semiconductor layer in contact with a drain. The quantum well is configured to store holes generated in a depletion layer of the drain region and imitate a short-term memory, and to convert the short-term memory into a long-term memory by enabling holes to be injected into a charge storage layer when the holes stored in quantum well exceed a specific threshold value. It is possible to fabricate with a bulk semiconductor substrate and utilize the conventional CMOS technology.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: September 29, 2020
    Assignee: GACHON UNIVERSITY OF INDUSTRY-ACADEMIC COOPERATION
    Inventors: Seongjae Cho, EunSeon Yu
  • Patent number: 10790281
    Abstract: Disclosed herein are stacked channel structures for metal oxide semiconductor field effect transistors (MOSFETs) and related circuit elements, computing devices, and methods. For example, a stacked channel structure may include: a semiconductor substrate having a substrate lattice constant; a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region; a first transistor in the lower region, wherein the first transistor has a first channel, the first channel has a first lattice constant, and the first lattice constant is different from the substrate lattice constant; and a second transistor in the upper region, wherein the second transistor has a second channel, the second channel has a second lattice constant, and the second lattice constant is different from the substrate lattice constant.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Roza Kotlyar, Stephen M. Cea, Patrick H. Keys
  • Patent number: 10763341
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first fin structure and a second fin structure disposed over the substrate. The semiconductor device structure includes a first gate stack disposed over the substrate and overlapping the first fin structure. The first gate stack includes a first work function layer, a first gate electrode, and a first hard mask layer, the first gate electrode is over the first work function layer, the first hard mask layer is over the first gate electrode, the first gate electrode has a first convex top surface protruding beyond a first top surface of the first work function layer. The semiconductor device structure includes a second gate stack disposed over the substrate and overlapping the second fin structure.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Han Fang, Chang-Yin Chen, Ming-Chia Tai, Po-Chi Wu
  • Patent number: 10756085
    Abstract: An integrated circuit may include a substrate, a first three-dimensional (3D) transistor formed on a first diffusion region of the substrate, and a second 3D transistor formed on a second diffusion region of the substrate. The first 3D transistor may include a gate that extends from between a source and a drain of the first 3D transistor, across an isolation region of the substrate, to and between a source and a drain of the second 3D transistor. The gate may include a gate metal that has an isolation portion extending over the isolation region of the substrate and a diffusion portion extending over the first and second diffusion regions of the substrate. The isolation portion of the gate metal has a thickness less than a maximum thickness of the diffusion portion of the gate metal.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: August 25, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Ye Lu, Bin Yang, Lixin Ge
  • Patent number: 10741662
    Abstract: Methods and structures for forming devices, such as transistors, are discussed. A method embodiment includes forming a gate spacer along a sidewall of a gate stack on a substrate; passivating at least a portion of an exterior surface of the gate spacer; and epitaxially growing a material in the substrate proximate the gate spacer while the at least the portion of the exterior surface of the gate spacer remains passivated. The passivating can include using at least one of a thermal treatment, a plasma treatment, or a thermal treatment.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Kuo-Feng Yu
  • Patent number: 10741517
    Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: August 11, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Shinya Suzuki
  • Patent number: 10734514
    Abstract: A semiconductor device includes trench structures that extend from a first surface into a semiconductor body. The trench structures include a gate structure and a contact structure that extends through the gate structure, respectively. Transistor mesas are between the trench structures. Each transistor mesa includes a body zone forming a first pn junction with a drift structure and a second pn junction with a source zone. Diode regions directly adjoin one of the contact structures form a third pn junction with the drift structure, respectively.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: August 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Romain Esteve, Dethard Peters, Roland Rupp, Ralf Siemieniec
  • Patent number: 10727334
    Abstract: An LDMOS transistor with a dummy gate comprises an extended drift region over a substrate, a drain region in the extended drift region, a channel region in the extended drift region, a source region in the channel region, a first dielectric layer with a first thickness formed over the extended drift region, a second dielectric layer with a second thickness formed over the extended drift region and the channel region, wherein the first thickness is greater than the second thickness, and wherein the first dielectric layer and the second dielectric layer form two steps, a first gate formed over the first dielectric layer and a second gate formed above the second dielectric layer.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Ruey-Hsin Liu, Jun Cai, Hsueh-Liang Chou, Chi-Chih Chen
  • Patent number: 10727130
    Abstract: A semiconductor device and a fabrication method are provided. The fabrication method includes providing a base substrate including a core region having a first gate structure formed thereon, and an edge region having a second gate structure formed thereon; forming a source/drain doped layer, in the core region of the base substrate on both sides of the first gate structure, and in the edge region of the base substrate on both sides of the second gate structure, respectively, the source/drain doped layer including first ions; and doping the second ions in the source/drain doped layer in the edge region, the second ions having a conductivity type opposite to the first ions.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: July 28, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10714380
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: July 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ravi P. Srivastava, Sipeng Gu, Sunil K. Singh, Xinyuan Dou, Akshey Sehgal, Zhiguo Sun
  • Patent number: 10692993
    Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: June 23, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Chan Suh, Sangmoon Lee, Yihwan Kim, Woo Bin Song, Dongsuk Shin, Seung Ryul Lee
  • Patent number: 10686056
    Abstract: A semiconductor power device formed in a semiconductor substrate that includes a plurality of trenches formed at a top portion of the semiconductor substrate. The trenches extend laterally across the semiconductor substrate along a longitudinal direction and each trench has a nonlinear portion thus the nonlinear portion has a trench sidewall perpendicular to the longitudinal direction of the trench. A plurality of trench bottom dopant regions are formed below the trench bottom surface. A sidewall dopant region is formed along the perpendicular sidewall wherein the sidewall dopant region extends vertically downward along the perpendicular sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 16, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yangping Ding, Sik Lui, Madhur Bobde, Lei Zhang, Jongoh Kim, John Chen
  • Patent number: 10672886
    Abstract: A method of forming a gate dielectric material includes forming a high-K dielectric material in a first region over a substrate, where forming the high-K dielectric material includes forming a first dielectric layer comprising hafnium over the substrate, and forming a second dielectric layer comprising lanthanum over the first dielectric layer.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Cheng-Han Lee, Zheng-Yang Pan, Shih-Chieh Chang, Chun-Chieh Wang
  • Patent number: 10665686
    Abstract: A semiconductor device includes a fin structure, disposed on a substrate, that horizontally extends along a direction; and a gate feature comprising a gate dielectric layer and at least a first metal gate layer overlaying the gate dielectric layer, wherein the gate dielectric layer and the first metal gate layer traverse the fin structure to overlay a central portion of the fin structure and further extend along the direction to overlay at least a side portion of the fin structure that is located outside a vertical projection of a sidewall of the gate feature.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Guan-Jie Shen, Chia-Der Chang, Chih-Hsiung Lin
  • Patent number: 10636906
    Abstract: A semiconductor device in chip size package includes first and second metal oxide semiconductor transistors both vertical transistors formed in first and second regions obtained by dividing the semiconductor device into halves. The first metal oxide semiconductor transistor includes one or more first gate electrodes and four or more first source electrodes provided in one major surface, each of the first gate electrodes is surrounded, in top view, by the first source electrodes, and for any combination of a first gate electrode and a first source electrode, closest points between the first gate and first source electrodes are on a line inclined to a chip side. The second metal oxide semiconductor transistor includes the same structure as the first metal oxide semiconductor transistor. A conductor that connects the drains of the first and second metal oxide semiconductor transistors is provided in the other major surface of the semiconductor device.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: April 28, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tomonari Ota, Shigetoshi Sota, Eiji Yasuda, Takeshi Imamura, Toshikazu Imai, Ryosuke Okawa, Kazuma Yoshida, Masaaki Hirako, Dohwan Ahn
  • Patent number: 10636792
    Abstract: A method of fabricating a semiconductor structure having multiple defined threshold voltages includes: forming multiple field-effect transistor (FET) devices in the semiconductor structure, each of the FET devices including a channel and a gate stack formed of one of at least two different work function metals, the gate stack being formed proximate the channel; and varying a band-gap of the channel in each of at least a subset of the FET devices by controlling a percentage of one or more compositions of a material forming the channel; wherein a threshold voltage of each of the FET devices is configured as a function of a type of work function metal forming the gate stack and the percentage of one or more compositions of the material forming the channel.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: April 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Vijay Narayanan
  • Patent number: 10629593
    Abstract: A semiconductor device includes a semiconductor substrate, trench isolations, a sacrificial layer, a first resist protect oxide (RPO) layer, a second RPO layer and a silicide layer. The semiconductor substrate has first portions and second portions which are alternately disposed, and each of the second portions includes a first resist region with a first resistance, a second resist region with a second resistance and a silicide region. The second resistance is greater than the first resistance. The trench isolations are in the first portions. The sacrificial layer is on the first resist region. The first RPO layer is on the sacrificial layer. The first RPO layer together with the sacrificial layer have a first thickness. The second RPO layer is on the second resist region, in which the second RPO layer has a second thickness smaller than the first thickness. The silicide layer is on the silicide region.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: April 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Jen Chen, Ping-Pang Hsieh, Hsin-Chi Chen
  • Patent number: 10580854
    Abstract: A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Sanjay C. Mehta, Xin Miao, Chun-Chen Yeh
  • Patent number: 10580855
    Abstract: A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Sanjay C. Mehta, Xin Miao, Chun-Chen Yeh
  • Patent number: 10566285
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: February 18, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Wei-Chi Cheng, Ssu-I Fu, Jyh-Shyang Jenq
  • Patent number: 10559696
    Abstract: The disclosure provides a hybrid CMOS device and a manufacturing method thereof. The manufacturing method of the hybrid CMOS device according to the disclosure uses a low-temperature polysilicon to prepare an active layer of a PMOS transistor, and simultaneously uses a metal oxide semiconductor to prepare an active layer of an NMOS transistor. The two types of semiconductor materials are used in combination to form a hybrid CMOS device. Compared with the existing method for producing an active layer of the PMOS transistor by using a two-dimensional carbon nanotransister material or an organic semiconductor material, the hybrid CMOS device obtained according to the disclosure has superior electrical properties.
    Type: Grant
    Filed: November 25, 2017
    Date of Patent: February 11, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Liangfen Zhang, Yuanjun Hsu, Jangsoon Im, Yuanchun Wu, Poyen Lu, Boru Yang, Changdong Chen, Chuan Liu
  • Patent number: 10559503
    Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: February 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Tuhin Guha Neogi, Andy Chi-Hung Wei, Jia Zeng, Jongwook Kye, Jason Eugene Stephens, Irene Yuh-Ling Lin, Sudharshanan Raghunathan, Lei Yuan
  • Patent number: 10553707
    Abstract: Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: February 4, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yanping Shen, Hui Zang, Bingwu Liu, Manoj Joshi, Jae Gon Lee, Hsien-Ching Lo, Zhaoying Hu
  • Patent number: 10546944
    Abstract: A semiconductor device includes a substrate having a first conductive type. An epitaxial layer having a second conductive type is disposed on the substrate. A first buried layer of the second conductive type is disposed within a high side region of the substrate. A second buried layer of the second conductive type is disposed directly above the first buried layer of the second conductive type. A top surface of the first buried layer of the second conductive type and a top surface of the second buried layer of the second conductive type are apart from a top surface of the epitaxial layer by different distances. A dopant concentration of the first buried layer of the second conductive type is less than that of the second buried layer of the second conductive type.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: January 28, 2020
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Subramanya Jayasheela Rao, Vinay Suresh, Po-An Chen
  • Patent number: 10535524
    Abstract: A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Jyun Wu, Sheng-Liang Pan, Huan-Just Lin
  • Patent number: RE48304
    Abstract: A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiqiang Wu, Wen-Hsing Hsieh, Hua Feng Chen, Ting-Yun Wu, Carlos H. Diaz, Ya-Yun Cheng, Tzer-Min Shen