Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) Patents (Class 438/197)
  • Patent number: 10665686
    Abstract: A semiconductor device includes a fin structure, disposed on a substrate, that horizontally extends along a direction; and a gate feature comprising a gate dielectric layer and at least a first metal gate layer overlaying the gate dielectric layer, wherein the gate dielectric layer and the first metal gate layer traverse the fin structure to overlay a central portion of the fin structure and further extend along the direction to overlay at least a side portion of the fin structure that is located outside a vertical projection of a sidewall of the gate feature.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Guan-Jie Shen, Chia-Der Chang, Chih-Hsiung Lin
  • Patent number: 10636906
    Abstract: A semiconductor device in chip size package includes first and second metal oxide semiconductor transistors both vertical transistors formed in first and second regions obtained by dividing the semiconductor device into halves. The first metal oxide semiconductor transistor includes one or more first gate electrodes and four or more first source electrodes provided in one major surface, each of the first gate electrodes is surrounded, in top view, by the first source electrodes, and for any combination of a first gate electrode and a first source electrode, closest points between the first gate and first source electrodes are on a line inclined to a chip side. The second metal oxide semiconductor transistor includes the same structure as the first metal oxide semiconductor transistor. A conductor that connects the drains of the first and second metal oxide semiconductor transistors is provided in the other major surface of the semiconductor device.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: April 28, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tomonari Ota, Shigetoshi Sota, Eiji Yasuda, Takeshi Imamura, Toshikazu Imai, Ryosuke Okawa, Kazuma Yoshida, Masaaki Hirako, Dohwan Ahn
  • Patent number: 10636792
    Abstract: A method of fabricating a semiconductor structure having multiple defined threshold voltages includes: forming multiple field-effect transistor (FET) devices in the semiconductor structure, each of the FET devices including a channel and a gate stack formed of one of at least two different work function metals, the gate stack being formed proximate the channel; and varying a band-gap of the channel in each of at least a subset of the FET devices by controlling a percentage of one or more compositions of a material forming the channel; wherein a threshold voltage of each of the FET devices is configured as a function of a type of work function metal forming the gate stack and the percentage of one or more compositions of the material forming the channel.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: April 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Vijay Narayanan
  • Patent number: 10629593
    Abstract: A semiconductor device includes a semiconductor substrate, trench isolations, a sacrificial layer, a first resist protect oxide (RPO) layer, a second RPO layer and a silicide layer. The semiconductor substrate has first portions and second portions which are alternately disposed, and each of the second portions includes a first resist region with a first resistance, a second resist region with a second resistance and a silicide region. The second resistance is greater than the first resistance. The trench isolations are in the first portions. The sacrificial layer is on the first resist region. The first RPO layer is on the sacrificial layer. The first RPO layer together with the sacrificial layer have a first thickness. The second RPO layer is on the second resist region, in which the second RPO layer has a second thickness smaller than the first thickness. The silicide layer is on the silicide region.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: April 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Jen Chen, Ping-Pang Hsieh, Hsin-Chi Chen
  • Patent number: 10580855
    Abstract: A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Sanjay C. Mehta, Xin Miao, Chun-Chen Yeh
  • Patent number: 10580854
    Abstract: A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Sanjay C. Mehta, Xin Miao, Chun-Chen Yeh
  • Patent number: 10566285
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: February 18, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Wei-Chi Cheng, Ssu-I Fu, Jyh-Shyang Jenq
  • Patent number: 10559503
    Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: February 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Tuhin Guha Neogi, Andy Chi-Hung Wei, Jia Zeng, Jongwook Kye, Jason Eugene Stephens, Irene Yuh-Ling Lin, Sudharshanan Raghunathan, Lei Yuan
  • Patent number: 10559696
    Abstract: The disclosure provides a hybrid CMOS device and a manufacturing method thereof. The manufacturing method of the hybrid CMOS device according to the disclosure uses a low-temperature polysilicon to prepare an active layer of a PMOS transistor, and simultaneously uses a metal oxide semiconductor to prepare an active layer of an NMOS transistor. The two types of semiconductor materials are used in combination to form a hybrid CMOS device. Compared with the existing method for producing an active layer of the PMOS transistor by using a two-dimensional carbon nanotransister material or an organic semiconductor material, the hybrid CMOS device obtained according to the disclosure has superior electrical properties.
    Type: Grant
    Filed: November 25, 2017
    Date of Patent: February 11, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Liangfen Zhang, Yuanjun Hsu, Jangsoon Im, Yuanchun Wu, Poyen Lu, Boru Yang, Changdong Chen, Chuan Liu
  • Patent number: 10553707
    Abstract: Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: February 4, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yanping Shen, Hui Zang, Bingwu Liu, Manoj Joshi, Jae Gon Lee, Hsien-Ching Lo, Zhaoying Hu
  • Patent number: 10546944
    Abstract: A semiconductor device includes a substrate having a first conductive type. An epitaxial layer having a second conductive type is disposed on the substrate. A first buried layer of the second conductive type is disposed within a high side region of the substrate. A second buried layer of the second conductive type is disposed directly above the first buried layer of the second conductive type. A top surface of the first buried layer of the second conductive type and a top surface of the second buried layer of the second conductive type are apart from a top surface of the epitaxial layer by different distances. A dopant concentration of the first buried layer of the second conductive type is less than that of the second buried layer of the second conductive type.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: January 28, 2020
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Subramanya Jayasheela Rao, Vinay Suresh, Po-An Chen
  • Patent number: 10535524
    Abstract: A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Jyun Wu, Sheng-Liang Pan, Huan-Just Lin
  • Patent number: 10521541
    Abstract: A semiconductor device includes a first active fin on a substrate; a second active fin on the substrate and separate from the first active fin; a first fin stub on the substrate, wherein the first fin stub connects a bottom portion of the first active fin and a bottom portion of the second active fin; and an isolation feature over the first fin stub and between the first and second active fins. The first fin stub is lower than both the first and the second active fins in height. The isolation feature is higher than the first fin stub and lower than both the first and the second active fins in height. From a top view, the first active fin is oriented lengthwise in a first direction, and the first fin stub is oriented lengthwise in a second direction that is different from the first direction.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ming Wang, Chih-Hsiung Peng, Chi-Kang Chang, Kuei-Shun Chen, Shih-Chi Fu
  • Patent number: 10522548
    Abstract: A method for fabricating a semiconductor device includes: forming a first conductive layer; forming a second conductive layer over the first conductive layer; forming a conductive line by etching the second conductive layer; etching a portion of the first conductive layer to form a plug head having the same critical dimension as the conductive line; forming a first spacer that covers the conductive line and the plug head; etching the remaining first conductive layer to form a plug body that is aligned with the first spacer, wherein the plug body have a greater critical dimension than the plug head; and forming a second spacer by performing a selective oxidation onto a side wall of the plug body.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: December 31, 2019
    Assignee: SK hynix Inc.
    Inventor: Jae-Houb Chun
  • Patent number: 10510582
    Abstract: A substrate includes a polycrystalline ceramic core; a first adhesion layer encapsulating the polycrystalline ceramic core; a conductive layer encapsulating the first adhesion layer; a second adhesion layer encapsulating the conductive layer; a barrier layer encapsulating the second adhesion layer, and a bonding layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the bonding layer.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: December 17, 2019
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens
  • Patent number: 10453957
    Abstract: A semiconductor device includes a first semiconductor region, a second semiconductor region between a first gate electrode and a second gate electrode that is disposed apart from the first gate electrode in a first direction, third and fourth semiconductor regions provided on respective portions of the second semiconductor region, an insulating region provided between the third semiconductor region and the fourth semiconductor region, and an electrode provided on the third semiconductor region and the fourth semiconductor region and electrically connected to the third semiconductor region and the fourth semiconductor region. The fourth semiconductor region is parallel to the third semiconductor region in a direction intersecting the first direction. The fourth semiconductor region has an impurity concentration higher than that of the second semiconductor region.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: October 22, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenya Kobayashi, Kenji Maeyama, Koji Matsuo, Yusuke Kawaguchi
  • Patent number: 10453955
    Abstract: An LDMOS transistor with a dummy gate comprises an extended drift region over a substrate, a drain region in the extended drift region, a channel region in the extended drift region, a source region in the channel region, a first dielectric layer with a first thickness formed over the extended drift region, a second dielectric layer with a second thickness formed over the extended drift region and the channel region, wherein the first thickness is greater than the second thickness, and wherein the first dielectric layer and the second dielectric layer form two steps, a first gate formed over the first dielectric layer and a second gate formed above the second dielectric layer.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: October 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Ruey-Hsin Liu, Jun Cai, Hsueh-Liang Chou, Chi-Chih Chen
  • Patent number: 10438961
    Abstract: A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a laminated film of a silicon oxide film and a silicon nitride film, and the silicon oxide film is particularly formed to directly contact the sidewall of a memory gate electrode and the side end portion of a charge storage film; on the other hand, an offset spacer formed in a MISFET is formed by a silicon nitride film. Particularly in the MISFET, the silicon nitride film directly contacts both the sidewall of a gate electrode and the side end portion of a high dielectric constant film.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: October 8, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Tamotsu Ogata
  • Patent number: 10439027
    Abstract: Provided is a silicon carbide semiconductor device that is further reduced in resistance. Silicon carbide semiconductor device includes silicon carbide semiconductor layer disposed on a first main surface of substrate, electrode layer containing polysilicon disposed on the silicon carbide semiconductor layer with first insulating layer interposed between the electrode layer and the silicon carbide semiconductor layer, second insulating layer that covers the silicon carbide semiconductor layer and the electrode layer, first silicide electrode that is located in first opening part formed in the first insulating layer and the second insulating layer and forms ohmic contact with a part of the silicon carbide semiconductor layer, and second silicide electrode that is located in second opening part formed in the second insulating layer and is in contact with a part of the electrode layer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: October 8, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Chiaki Kudou
  • Patent number: 10424751
    Abstract: One embodiment provides electronic device, which can include at least two organic electrochemical transistors (OECTs). A respective OECT includes a conductive channel, a gate electrically coupled to the conductive channel via a first electrolyte, and source and drain electrodes separated from each other by the conductive channel. The electrochemical potentials of redox-couples of the at least two organic electrochemical transistors are different, thereby resulting in the at least two organic electrochemical transistors having different threshold voltages. An alternative embodiment can provide an organic electrochemical transistor (OECT). The OECT can include a conductive channel, a gate electrically coupled to the conductive channel via a first electrolyte, and source and drain electrodes separated from each other by the conductive channel. The gate can include a conductive current collector and at least one redox-couple.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: September 24, 2019
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Sean E. Doris, Adrien Pierre
  • Patent number: 10388727
    Abstract: A method of forming a nanosheet semiconductor device that includes epitaxially forming a stack of at least two repeating nanosheets, the at least two repeating nanosheets including a first nanosheet layer of a first III-V semiconductor material and a second nanosheet layer of a second III-V semiconductor material. A sacrificial gate structure is formed on the stack of the at least two repeating nanosheets. Source and drain regions are epitaxially formed on the second nanosheet layer. The sacrificial gate structure is removed to provide a gate opening. An etch process removes the first nanosheet layer selectively to the second nanosheet layer, wherein the etch process is selective to facets of the material for the first nanosheet layer to provide an inverted apex at the base of the stack. A dielectric layer is deposited filling the inverted apex. A functional gate structure is formed in the gate opening.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Pouya Hashemi, Mahmoud Khojasteh, Alexander Reznicek
  • Patent number: 10381480
    Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Albert M. Chu, Eric Eastman, Myung-Hee Na, Ravikumar Ramachandran
  • Patent number: 10381352
    Abstract: Some embodiments include an integrated assembly having semiconductor material structures which each have a transistor channel region, and which are over metal-containing structures. Carbon-doped oxide is adjacent regions of each of the semiconductor material structures and sidewalls of the metal-containing structures. Some embodiments include an integrated assembly having pillars of semiconductor material. Each of the pillars has four sidewalls. Two of the four sidewalls of each pillar are gated sidewalls. The other two of the four sidewalls are non-gated sidewalls. Carbon-doped silicon dioxide is adjacent and directly against the non-gated sidewalls. Some embodiments include a method of forming an integrated assembly. Rails of semiconductor material are formed. A layer of carbon-doped silicon dioxide is formed adjacent top surfaces and sidewall surfaces of each of the rails. Trenches are formed which slice the semiconductor material of the rails into pillars.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Silvia Borsari, Sau Ha Cheung
  • Patent number: 10366881
    Abstract: A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins. A surface of the porous fins is treated to make the surface suitable for epitaxial growth. Lattice mismatch is compensated for between an epitaxially grown monocrystalline layer grown on the surface and the monocrystalline substrate by relaxing the epitaxially grown monocrystalline layer using the porous fins to form a relaxed heteroepitaxial interface with the monocrystalline substrate.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • Patent number: 10367028
    Abstract: A CMOS image sensor may include a first semiconductor chip including image sensor pixels and readout circuitry electrically connected thereto, and a second semiconductor chip coupled to the first chip in a stack and including image processing circuitry electrically connected to the readout circuitry. The processing circuitry may include a plurality of transistors each including spaced apart source and drain regions and a superlattice channel extending between the source and drain regions. The superlattice channel may include a plurality of stacked groups of layers, each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. Each transistor may further include a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: July 30, 2019
    Assignee: ATOMERA INCORPORATED
    Inventors: Yi-Ann Chen, Abid Husain, Hideki Takeuchi
  • Patent number: 10360331
    Abstract: Aspects of the disclosed technology relate to techniques of scoped simulation-based ESD verification. ESD (electrostatic discharge) protection devices and I/O (input/output) circuitry are identified in a circuit design. Static simulation is performed on the I/O circuitry to determine voltage and current information for devices on current paths in the I/O circuitry based on point-to-point resistance values. Transient simulation is then performed on one or more of the ESD protection devices in the devices based on the voltage and current information and detailed parasitic information. The point-to-point resistance values and the detailed parasitic information are extracted based on a layout design for the circuit design and cross-reference information between circuit component identifiers and layout features. Results of the transient simulation are analyzed to identify ESD protection problems.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: July 23, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Sridhar Srinivasan, Mark E. Hofmann
  • Patent number: 10332750
    Abstract: A method for fabricating a semiconductor device. A gate is formed on a substrate. A spacer is formed on each sidewall of the gate. A hard mask layer is formed on the spacer. A recessed region is formed in the substrate and adjacent to the hard mask layer. An epitaxial layer is formed in the recessed region. The substrate is subjected to an ion implantation process to bombard particle defects on the hard mask layer with inert gas ions. An annealing process is performed to repair damages to the epitaxial layer caused by the ion implantation process. The hard mask layer is then removed.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: June 25, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuang-Hsiu Chen, Hsu Ting, Chung-Fu Chang, Shi-You Liu, Chun-Wei Yu, Yu-Ren Wang
  • Patent number: 10319591
    Abstract: Processing methods comprising selectively replacing a first pillar material with a second pillar material in a self-aligned process are described. The first pillar material may be grown orthogonally to the substrate surface and replaced with a second pillar material to leave a substantially similar shape and alignment as the first pillar material.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: June 11, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Ziqing Duan, Abhijit Basu Mallick
  • Patent number: 10312261
    Abstract: A transistor includes an active region supported by a substrate and having a source region, a channel region and a drain region. A gate stack extends over the channel region and a first sidewall surrounds the gate stack. A raised source region and a raised drain region are provided over the source and drain regions, respectively, of the active region adjacent the first sidewall. A second sidewall peripherally surrounds each of the raised source region and raised drain region. The second sidewall extends above a top surface of the raised source region and raised drain region to define regions laterally delimited by the first and second sidewalls. A conductive material fills the regions to form a source contact and a drain contact to the raised source region and raised drain region, respectively.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: June 4, 2019
    Assignee: STMicroelectronics, Inc.
    Inventor: John Hongguang Zhang
  • Patent number: 10312348
    Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chang Huang, Fu-Peng Lu, Chun-Chang Liu, Chen-Chiu Huang
  • Patent number: 10312132
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins over a substrate, forming one or more shallow isolation trench (STI) structures defining a first region and a second region, forming a liner dielectric and forming spacers adjacent sidewalls of the plurality of fins and adjacent the one or more STI structures. The method further includes filling the one or more STI structures with an oxide layer, and incrementally recessing the oxide layer and the spacers adjacent the plurality of fins in an alternate manner until a proximal end of the second region is detected.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Sebastian Naczas, Peng Xu
  • Patent number: 10297492
    Abstract: The embodiments of mechanisms for doping wells of finFET devices described in this disclosure utilize depositing doped films to dope well regions. The mechanisms enable maintaining low dopant concentration in the channel regions next to the doped well regions. As a result, transistor performance can be greatly improved. The mechanisms involve depositing doped films prior to forming isolation structures for transistors. The dopants in the doped films are used to dope the well regions near fins. The isolation structures are filled with a flowable dielectric material, which is converted to silicon oxide with the usage of microwave anneal. The microwave anneal enables conversion of the flowable dielectric material to silicon oxide without causing dopant diffusion. Additional well implants may be performed to form deep wells. Microwave anneal(s) may be used to anneal defects in the substrate and fins.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chun Hsiung Tsai, Yan-Ting Lin, Clement Hsingjen Wann
  • Patent number: 10293377
    Abstract: A piezoelectric micromachined ultrasonic transducer (PMUT) device includes a substrate having an opening therethrough and a membrane attached to the substrate over the opening. A portion of the membrane that overlies the opening is divided into a plurality of cantilevers that are mechanically coupled so that the cantilevers resonate at a common frequency.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: May 21, 2019
    Assignee: CHIRP MICROSYSTEMS
    Inventors: Andre Guedes, David Horsley, Meng-Hsiung Kiang, Richard Przybyla, Stefon Shelton
  • Patent number: 10283634
    Abstract: A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: May 7, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Joachim Krumrey, Franz Hirler, Walter Rieger
  • Patent number: 10283624
    Abstract: A semiconductor device and a method for forming the same are provided. The method includes forming a gate structure over a fin structure. The method further includes forming first gate spacers on opposite sidewalls of the gate structure. The method further includes forming source/drain features in the fin structure and adjacent to the first gate spacers. The method further includes performing a surface treatment process on top surfaces of the source/drain features and outer sidewalls of the first gate spacers. The method further includes depositing a contact etch stop layer (CESL) over the source/drain features and the first gate spacers. A first portion of the CESL is deposited over the top surfaces of the source/drain features at a first deposition rate. A second portion of the CESL is deposited over the outer sidewalls of the first gate spacers at a second deposition rate.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Hsuan Lee, Bo-Yu Lai, Chi-On Chui, Cheng-Yu Yang, Yen-Ting Chen, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 10276572
    Abstract: A semiconductor device includes a first channel region disposed over a substrate, a first source region and a first drain region disposed over the substrate and connected to the first channel region such that the first channel region is disposed between the first source region and the first drain region, a gate dielectric layer disposed on and wrapping the first channel region, a gate electrode layer disposed on the gate dielectric layer and wrapping the first channel region, and a second source region and a second drain region disposed over the substrate and below the first source region and the first drain region, respectively. The second source region and the second drain region are in contact with the gate dielectric layer. A lattice constant of the first source region and the first drain region is different from a lattice constant of the second source region and the second drain region.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Ka-Hing Fung
  • Patent number: 10269647
    Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. In one embodiment, a method for forming a FinFET device includes removing a portion of each fin of a plurality of fins, and a remaining portion of each fin is recessed from a dielectric surface. The method further includes forming a feature on the remaining portion of each fin, filling gaps formed between adjacent features with a dielectric material, removing the features, and forming a fill material on the remaining portion of each fin. Because the shape of the features is controlled, the shape of the fill material can be controlled.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: April 23, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ying Zhang, Schubert S. Chu, Xinyu Bao, Regina Germanie Freed, Hua Chung
  • Patent number: 10263004
    Abstract: The present disclosure relates to a method of forming sidewall spacers configured to improve dielectric fill between adjacent gate structures. In some embodiments, the method may be performed by depositing a sidewall spacer material over a first gate structure and a second gate structure. A first etching process is performed on the sidewall spacer material to form a first intermediate sidewall spacer surrounding the first gate structure and a second sidewall spacer surrounding the second gate structure. A masking material is formed over the substrate. Parts of the first intermediate sidewall spacer protrude outward from the masking material, while the second sidewall spacer is completely covered by the masking material. A second etching process is then performed on the parts of the first intermediate sidewall spacer protruding outward from the masking material to form a first sidewall spacer recessed below an uppermost surface of the first gate structure.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Josh Lin, Chia-Ta Hsieh, Chen-Ming Huang, Chi-Wei Ho
  • Patent number: 10256092
    Abstract: The invention relates to a method for fabricating a semiconductor circuit comprising providing a semiconductor substrate; fabricating a first semiconductor device comprising a first semiconductor material on the substrate and forming an insulating layer comprising a cavity structure on the first semiconductor device. The cavity structure comprises at least one growth channel and the growth channel connects a crystalline seed surface of the first semiconductor device with an opening. Further steps include growing via the opening from the seed surface a semiconductor filling structure comprising a second semiconductor material different from the first semiconductor material in the growth channel; forming a semiconductor starting structure for a second semiconductor device from the filling structure; and fabricating a second semiconductor device comprising the starting structure. The invention is notably also directed to corresponding semiconductor circuits.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniele Caimi, Lukas Czornomaz, Veeresh Deshpande, Vladimir Djara, Jean Fompeyrine
  • Patent number: 10256089
    Abstract: Interconnect structures and methods of forming an interconnect structure. A sacrificial contact is arranged between a first gate structure and a second gate structure. The sacrificial contact extends vertically to a source/drain region. A section of the sacrificial contact is removed to form a cut opening extending vertically to the source/drain region. A first dielectric layer is deposited in the cut opening, and is then partially removed to open a space in the cut opening that is arranged vertically above the first dielectric layer. A second dielectric layer is deposited that fills the space in the cut opening and forms a cap on the first dielectric layer. The first dielectric layer has a first dielectric constant, and the second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: April 9, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Huy Cao, Haigou Huang, Jinsheng Gao, Tai Fong Chao
  • Patent number: 10256240
    Abstract: A semiconductor device includes a substrate having a first region and a second region, a fin-shaped structure and a bump on the first region of the substrate, and a shallow trench isolation (STI) around the fin-shaped structure and on the bump. Preferably, the fin-shaped structure and the bump comprise different material, the fin-shaped structure comprises a top portion and a bottom portion, the top portion and the bottom portion comprise different semiconductor material, and a top surface of the bottom portion is lower than a top surface of all of the STI on both the first region and the second region and higher than a top surface of the bump and the top surface of the bump contacts the STI directly.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 9, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Yu-Cheng Tung
  • Patent number: 10249533
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of gate structures spaced apart from each other on a fin, forming an inorganic plug portion on the fin between at least two gate structures of the plurality of gate structures, forming a dielectric layer on the fin and between remaining gate structures of the plurality of gate structures, forming an organic planarizing layer (OPL) on the plurality of gate structures and on the inorganic plug portion, removing a portion of the OPL to expose the inorganic plug portion, selectively removing the inorganic plug portion, and forming a contact on the fin in place of the removed inorganic plug portion.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Shearer, John R. Sporre, Nicole A. Saulnier, Hyung Joo Shin
  • Patent number: 10229836
    Abstract: A method for manufacturing a silicon carbide epitaxial substrate includes epitaxially growing a first layer on a silicon carbide single crystal substrate, and forming a second layer at an outermost surface of the first layer. The second layer has a chemical composition or density different from that of the first layer. A ratio of a thickness of the second layer to a thickness of the first layer is more than 0% and less than or equal to 10%.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: March 12, 2019
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Taro Nishiguchi, Toru Hiyoshi
  • Patent number: 10204952
    Abstract: A semiconductor device includes a first semiconductor chip comprising a first metallic structure and a second semiconductor chip comprising a second metallic structure. The second semiconductor chip is bonded with the first semiconductor chip by a conductive material filled in a through via. The through via connects the first metallic structure and the second metallic structure, wherein a portion of the through via is inside the first semiconductor chip and the second semiconductor chip.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Yin-Chieh Huang
  • Patent number: 10199480
    Abstract: A semiconductor structure includes a semiconductor substrate, a bottom source/drain layer for a first vertical transistor over the semiconductor substrate, a vertical channel over the source/drain layer, and a metal gate wrapped around the vertical channel, the vertical channel having a fixed height relative to the metal gate at an interface therebetween. The semiconductor structure further includes a top source/drain layer over the vertical channel, and a self-aligned contact to each of the top and bottom source/drain layer and the gate. The semiconductor structure can be realized by providing a semiconductor substrate with a bottom source/drain layer thereover, forming a vertical channel over the bottom source/drain layer, forming a dummy gate wrapped around the vertical channel, and forming a bottom spacer layer and a top spacer layer around a top portion and a bottom portion, respectively, of the vertical channel, a remaining center portion of the vertical channel defining a fixed vertical channel height.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Tenko Yamashita, Kangguo Cheng, Chun-Chen Yeh
  • Patent number: 10170595
    Abstract: A method of forming an arrangement of active and inactive fins on a substrate, including forming at least three vertical fins on the substrate, forming a protective liner on at least three of the at least three vertical fins, removing at least a portion of the protective liner on the one of the at least three of the at least three of vertical fins, and converting the one of the at least three of the at least three vertical fins to an inactive vertical fin.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 10170467
    Abstract: A 3D semiconductor memory device includes a semiconductor substrate, a source line, a gate line and a plurality of memory cells connected in series. The semiconductor substrate has a protruding portion. The source line is disposed in the semiconductor substrate and partially extending below the protruding portion. The gate line is configured to surround and cover the protruding portion and electrically separated from the source line and the protruding portion. The memory cells are disposed on the semiconductor substrate and connected in series to the protruding portion at a top surface thereof.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: January 1, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Kuang-Hao Chiang, Dai-Ying Lee
  • Patent number: 10164065
    Abstract: In a method for manufacturing a semiconductor device, a first raised structure is formed on a surface of a substrate. The first raised structure includes a top surface and a side surface adjoining the top surface. The side surface includes an upper portion, a middle portion, and a lower portion. A deposition operation is performed with a precursor to form a first film on the top surface, the upper portion and the lower portion of the side surface, and the surface of the substrate. Performing the deposition operation includes controlling a saturated vapor pressure of the precursor. A re-deposition operation is performed on the first film and the first raised structure, so as to form a film structure. A thickness of the film structure on the middle portion of the side surface is smaller than a thickness of the film structure on the top surface.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Shu-Hui Wang, Chih-Yang Yeh, Jeng-Ya David Yeh
  • Patent number: 10163935
    Abstract: The present invention provides a thin film transistor, an array substrate and a display device. The thin film transistor comprises an active layer, a source electrode and a drain electrode. The active layer comprises a source electrode contact region and a drain electrode contact region, and a semiconductor channel region arranged between the source electrode contact region and the drain electrode contact region. A conductive layer is provided on the semiconductor channel region and is spaced apart from the source electrode and the drain electrode.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: December 25, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongfei Cheng, Yong Qiao, Jianbo Xian, Wenbo Li, Pan Li
  • Patent number: 10157769
    Abstract: Semiconductor devices including at least one diode over a conductive strap. The semiconductor device may include at least one conductive strap over an insulator material, at least one diode comprising a single crystalline silicon material over a conductive material, and a memory cell on the at least one diode. The at least one diode may be formed from a single crystalline silicon material. Methods of forming such semiconductor devices are also disclosed.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: December 18, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Ming Zhang