Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.) Patents (Class 438/197)
  • Patent number: 11322412
    Abstract: A method includes forming a dummy gate stack over a semiconductor region of a wafer, and depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack. The depositing the gate spacer layer includes performing an ALD cycle to form a dielectric atomic layer. The ALD cycle includes introducing silylated methyl to the wafer, purging the silylated methyl, introducing ammonia to the wafer, and purging the ammonia.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yi Kao, Chung-Chi Ko
  • Patent number: 11322702
    Abstract: Electrical device including a substrate having a surface and a radiofrequency field effect transistor (RF-FET) on the substrate surface. RF-FET includes a CNT layer on the substrate surface, the CNT layer including electrically conductive aligned carbon nanotubes, and pin-down anchor layers on the CNT layer. A first portion of the CNT layer, located in-between the pin-down anchor layers, is not covered by the pin-down anchor layers and is a channel region of the radiofrequency field effect transistor and second portions of the CNT layer are covered by the pin-down anchor layers. For cross-sections in a direction perpendicular to a common alignment direction of the aligned CNTs in the first portion of the CNT layer: the aligned CNTs have an average linear density in a range from 20 to 120 nanotubes per micron along the cross-section, and at least 40 percent of the aligned CNTs are discrete from any CNTs of the CNT layer.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: May 3, 2022
    Assignee: Carbonics Inc.
    Inventors: Alexander Allen Kane, Christopher Michael Rutherglen, Tyler Andrew Cain, Philbert Francis Marsh, Kosmas Galatsis
  • Patent number: 11302819
    Abstract: A first transistor and a second transistor are stacked. The first transistor and the second transistor have a gate electrode in common. At least one of semiconductor films used in the first transistor and the second transistor is an oxide semiconductor film. With the use of the oxide semiconductor film as the semiconductor film in the transistor, high field-effect mobility and high-speed operation can be achieved. Since the first transistor and the second transistor are stacked and have the gate electrode in common, the area of a region where the transistors are disposed can be reduced.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: April 12, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Seiichi Yoneda
  • Patent number: 11302820
    Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes depositing a light blocking layer along sidewalls and bottom surfaces of the source/drain contact openings and a topmost surface of the at least one dielectric layer. The method further includes performing a laser annealing process to activate dopants in the source/drain contact region. The method further includes forming source/drain contact structures within source/drain contact openings.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Blandine Duriez, Marcus Johannes Henricus Van Dal, Martin Christopher Holland, Gerben Doornbos, Georgios Vellianitis
  • Patent number: 11296194
    Abstract: The present invention relates to a method for manufacturing a nonvolatile memory, including the steps of: forming a gate oxide layer on a substrate; forming a stacked capacitor of a storage cell after making a logic gate polysilicon undertake at least two deposition processes; and removing the extra logic gate polysilicon by an etching process to form a storage transistor and a peripheral logic transistor. According to the method of the present invention, the stacked capacitor of the storage transistor is formed by depositing at least twice, and the memory is manufactured in a standard logic process, which makes the manufacturing process of the memory simpler, the memory has good compatibility with the logic process and has low cost.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: April 5, 2022
    Assignee: Chengdu Analog Circuit Technology Inc
    Inventors: Dan Ning, Tengfeng Wang
  • Patent number: 11289480
    Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Shih-Hang Chiu, Chih-Chang Hung, I-Wei Yang, Shu-Yuan Ku, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 11282950
    Abstract: Provided is a technology for obtaining a drain current of a sufficient magnitude in a field effect transistor using a nitride semiconductor. A channel layer that is Alx1Iny1Ga1-x1-y1N is formed on an upper surface of a semiconductor substrate, and on an upper surface of the channel layer, a barrier layer that is Alx2Iny2Ga1-x2-y2N having a band gap larger than that of the channel layer is formed. Then, on an upper surface of the barrier layer, a gate insulating film that is an insulator or a semiconductor and has a band gap larger than that of the barrier layer is at least partially formed, and a gate electrode is formed on an upper surface of the gate insulating film. Then, heat treatment is performed while a positive voltage is applied to the gate electrode.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: March 22, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takuma Nanjo, Tetsuro Hayashida, Koji Yoshitsugu, Akihiko Furukawa
  • Patent number: 11276783
    Abstract: A semiconductor device includes: a first conductivity type semiconductor of a nanostructure; a first electrode that is in ohmic junction with an end part of the first conductivity type semiconductor; a second electrode that is coupled to the first electrode and is provided over a side surface of the first conductivity type semiconductor; and a depletion constituent that controls expansion of a depletion layer inside the nanostructure, wherein the depletion layer is expanded inside the first conductivity type semiconductor by the depletion constituent in a direction intersecting a movement direction of a carrier.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: March 15, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Tsuyoshi Takahashi, Kenichi Kawaguchi
  • Patent number: 11271080
    Abstract: A silicon carbide semiconductor device includes a gate insulating film and a gate electrode made of p+ polysilicon doped with boron at a high concentration. Among boron impurities contained in the polysilicon of the gate electrode, 11B, which is one of the isotopes of boron, is contained 90% or more, thereby reducing the amount of 10B diffusing from the polysilicon of the gate electrode into the gate insulating film. This results in a suppression of a threshold voltage shift that occurs when AC voltage is applied to the gate electrode.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: March 8, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tsuyoshi Araoka
  • Patent number: 11264501
    Abstract: Techniques and mechanisms for imposing stress on a channel region of an NMOS transistor. In an embodiment, a fin structure on a semiconductor substrate includes two source or drain regions of the transistor, wherein a channel region of the transistor is located between the source or drain regions. At least on such source or drain region includes a doped silicon germanium (SiGe) compound, wherein dislocations in the SiGe compound result in the at least one source or drain region exerting a tensile stress on the channel region. In another embodiment, source or drain regions of a transistor each include a SiGe compound which comprises at least 50 wt % germanium.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Anand Murthy, Karthik Jambunathan, Cory Bomberger
  • Patent number: 11239359
    Abstract: Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: February 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Jingyun Zhang, Choonghyun Lee, Takashi Ando, Pouya Hashemi, Alexander Reznicek
  • Patent number: 11239191
    Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.
    Type: Grant
    Filed: July 3, 2020
    Date of Patent: February 1, 2022
    Assignee: Renesas Electronics Corporation
    Inventor: Shinya Suzuki
  • Patent number: 11233111
    Abstract: An array substrate, a manufacturing method of an array substrate, and a display panel are provided. The array substrate includes: a deformable substrate, the deformable substrate including a first region and a second region, the first region being provided with a plurality of voids, the second region being a region of the deformable substrate not provided with the plurality of voids; an electronic element on the second region of the deformable substrate.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: January 25, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Pinfan Wang, Ming Che Hsieh
  • Patent number: 11227833
    Abstract: A method for forming an interconnect structure is provided. The method for forming the interconnect structure includes forming a first dielectric layer over a substrate, forming a first conductive feature through the first dielectric layer, forming a first blocking layer on the first conductive feature, forming a first etching stop layer over the first dielectric layer and exposing the first blocking layer, removing at least a portion of the first blocking layer, forming a first metal bulk layer over the first etching stop layer and the first conductive feature, and etching the first metal bulk layer to form a second conductive feature electrically connected to the first conductive feature.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Kuan Lee, Cheng-Chin Lee, Hsin-Yen Huang, Hai-Ching Chen, Shau-Lin Shue
  • Patent number: 11211380
    Abstract: A method for manufacturing a semiconductor structure includes forming a plurality of dummy semiconductor fins on a substrate. The dummy semiconductor fins are adjacent to each other and are grouped into a plurality of fin groups. The dummy semiconductor fins of the fin groups are recessed one group at a time.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Po-Chi Wu, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 11177164
    Abstract: Processing methods to form self-aligned high aspect ratio features are described. The methods comprise depositing a metal film on a structured substrate, volumetrically expanding the metal film, depositing a second film between the expanded pillars and optionally recessing the pillars and repeating the process to form the high aspect ratio features.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: November 16, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Susmit Singha Roy, Praburam Gopalraja, Abhijit Basu Mallick, Srinivas Gandikota
  • Patent number: 11171204
    Abstract: A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: November 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Sanjay C. Mehta, Xin Miao, Chun-Chen Yeh
  • Patent number: 11169408
    Abstract: A display device panel includes a display area including pixels and a non-display area. Each pixel is connected to one of gate lines and one of data lines. The non-display area includes data pad sections. The non-display area further includes a depiction of a first information code and a depiction of a second information code. The depiction of the first information code is disposed between first two adjacent data pad sections and is apart from an outline of the non-display area by a first distance. The depiction of the second information code is disposed between second two adjacent data pad sections and is apart from the outline of the non-display area by a second distance different from the first distance.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: November 9, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kang Young Lee, Sang Hyun Kang, Dae Hyun Kim, Seung Hwan Kim, Joo Yeol Lee, Jang Bog Ju
  • Patent number: 11171179
    Abstract: A memory array includes: a plurality of first wires; at least one second wire crossing the first wires; and a plurality of memory elements provided in correspondence with respective intersections of the first wires and the at least one second wire and each having a first electrode and a second electrode arranged spaced apart from each other, a third electrode connected to one of the at least one second wire, and an insulating layer that electrically insulates the first electrode and the second electrode and the third electrode from each other, the first wires, the at least one second wire, and the first wires, the at least one second wire, and the memory elements being formed on a substrate.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: November 9, 2021
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Shota Kawai, Seiichiro Murase, Hiroji Shimizu
  • Patent number: 11158727
    Abstract: The present disclosure provides a method of semiconductor fabrication that includes forming a semiconductor fin protruding from a substrate, the semiconductor fin including a plurality of first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked, the second semiconductor material being different from the first semiconductor material in composition; forming a first gate stack on the semiconductor fin; forming a recess in the semiconductor fin within a source/drain (S/D) region adjacent to the first gate stack, a sidewall of the first and second semiconductor material layers being exposed within the recess; performing an etching process to the semiconductor fin, resulting in an undercut below the first gate stack; epitaxially growing on the sidewall of the semiconductor fin to fill in the undercut with a semiconductor extended feature of the first semiconductor material; and growing an epitaxial S/D feature from the rece
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Hsun Wang, Chih-Chao Chou, Chun-Hsiung Lin, Ching-Wei Tsai, Chih-Hao Wang
  • Patent number: 11152460
    Abstract: A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Sanjay C. Mehta, Xin Miao, Chun-Chen Yeh
  • Patent number: 11139289
    Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device, as well as apparatus having such circuit-protection devices.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michael A. Smith, Kenneth W. Marr
  • Patent number: 11139294
    Abstract: Semiconductor structure and method for fabricating a semiconductor structure are provided. A substrate including device regions and an isolation region located adjacent to and between the device regions is provided. A fin on the substrate, gate structures across the fin at the device regions, source/drain doped regions in the fin at two sides of each of the gate structures, and a sacrificial gate across the fin at the isolation region are provided. The sacrificial gate and a portion of the fin near a bottom of the sacrificial gate are removed, thus forming a first opening in the fin. An insulation structure in the first opening is formed. Two sides of the sacrificial gate are in contact with the source/drain doped regions at adjacent device regions. A top surface of the insulation structure is flush with or higher than top surfaces of the source/drain doped regions.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: October 5, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Wu Feng Deng, De Biao He, Chang Yong Xiao
  • Patent number: 11133227
    Abstract: The instant disclosure discloses a method comprises receiving a substrate having a first region and a second region defined thereon and an insulating structure formed there-between; forming, extending across the first region and the second region, a gate stack including a dielectric layer and a gate poly layer formed thereon; forming a first well mask covering the second region while defining a first opening that projectively overlaps the first region to partially exposes the gate poly layer; performing a first doping process, through the first opening and the gate stack, to form a first well in the substrate beneath the first opening; and performing a second doping process through the first opening to form a first gate conductor in the gate poly layer.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: September 28, 2021
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Deok-Yong Kim, Yongchul Oh
  • Patent number: 11091726
    Abstract: To provide a composition for removing photoresist residue and/or polymer residue formed in a process for producing a semiconductor circuit element, and a removal method employing same. A composition for removing photoresist residue and/or polymer residue, the composition containing saccharin and water, and the pH being no greater than 9.7.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: August 17, 2021
    Assignee: Kanto Kagaku Kabushiki Kaisha
    Inventor: Yasuyuki Seino
  • Patent number: 11081592
    Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. The core region has an approximately square-shape cross section and a first shell of the one or more shells forms a first shell region of an approximately rhombus-shape cross section around the core region and is connected to an adjacent first shell region corresponding to a neighboring semiconductor wire.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Sheng Chen, Szu-Wei Huang, Hung-Li Chiang, Cheng-Hsien Wu, Chih Chieh Yeh
  • Patent number: 11075120
    Abstract: A device includes a fin over a substrate, the fin including a first end and a second end, wherein the first end of the fin has a convex profile, an isolation region adjacent the fin, a gate structure along sidewalls of the fin and over the top surface of the fin, a gate spacer laterally adjacent the gate structure, and an epitaxial region adjacent the first end of the fin.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kun-Mu Li, Heng-Wen Ting, Hsueh-Chang Sung, Yen-Ru Lee, Chien-Wei Lee
  • Patent number: 11063126
    Abstract: A method of forming a semiconductor structure includes the following steps. At least a first source/drain region and a second source/drain region are formed in a substrate. At least a first sacrificial layer and a second sacrificial layer are respectively formed over the first source/drain region and the second source/drain region. A spacer layer is formed on at least a top surface of the substrate and around sides of the first sacrificial layer and the second sacrificial layer. The spacer layer includes an electrical-isolating material. The first sacrificial layer and a second sacrificial layer are removed to form a first open trench and a second open trench. The first open trench and the second open trench are filled with metal contact material to form a first metal contact and a second metal contact electrically isolated from each other by the spacer layer.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Su Chen Fan, Yann Mignot, Hsueh-Chung Chen, James J. Kelly
  • Patent number: 11063137
    Abstract: An embodiment includes an apparatus comprising: a transistor including a source, a drain, and a gate that has first and second sidewalls; a first spacer on the first sidewall between the drain and the gate; a second spacer on the second sidewall between the source and the gate; and a third spacer on the first spacer. Other embodiments are described herein.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Jui-Yen Lin, Chen-Guan Lee, Joodong Park, Walid M. Hafez, Kun-Huan Shih
  • Patent number: 11043421
    Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of cutting the wafer by using a cutting apparatus to thereby divide the wafer into individual device chips, and a pickup step of cooling the polyester sheet, pushing up each device chip through the polyester sheet, and then picking up each device chip from the polyester sheet.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: June 22, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11038092
    Abstract: Structures that include semiconductor fins and methods for forming a structure that includes semiconductor fins. A first fin comprised of n-type semiconductor material and a second fin comprised of p-type semiconductor material are formed. A conductive strap is formed that couples an end of the first fin with an end of the second fin.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: June 15, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Philipp Steinmann, Puneet H. Suvarna
  • Patent number: 11024553
    Abstract: A method includes forming a transistor over a substrate; forming a conductive structure over the substrate, such that a first end of the conductive structure is electrically coupled to a gate of the transistor, and a second end of the conductive structure is electrically coupled to the substrate; applying biases to the gate of the transistor and source/drain structures of the transistor; determining whether the first end and the second end of the conductive structure are electrically connected; generating, based on the determination, a first result indicating that the first end and the second end of the conductive structure are electrically connected; and qualifiying the conductive structure as an antenna in response to the first result.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: June 1, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Tsang-Po Yang, Jui-Hsiu Jao, Chun-Shun Huang
  • Patent number: 11010526
    Abstract: A semiconductor device includes a first active fin on a substrate; a second active fin on the substrate and separate from the first active fin; and a first fin stub on the substrate, wherein the first fin stub connects a first end of the first active fin and a first end of the second active fin, wherein the fin stub is lower than both the first and the second active fins in height, wherein from a top view the first active fin is oriented lengthwise in a first direction, and the first fin stub is oriented lengthwise in a second direction that is different from the first direction.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ming Wang, Chih-Hsiung Peng, Chi-Kang Chang, Kuei-Shun Chen, Shih-Chi Fu
  • Patent number: 11011426
    Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor fin over a substrate. A fin spacer is formed on a sidewall of the semiconductor fin. An e-beam treatment is performed on the fin spacer. An epitaxial structure is formed over the semiconductor fin. The epitaxial structure is in contact with the e-beam treated fin spacer.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Han-Wen Liao
  • Patent number: 11004748
    Abstract: This disclosure relates to a method of fabricating semiconductor devices with a gate-to-gate spacing that is wider than a minimum gate-to-gate spacing and the resulting semiconductor devices. The method includes forming gate structures over an active structure, the gate structures including a first gate structure, a second gate structure, and a third gate structure. The second gate structure is between the first and third gate structures. A plurality of epitaxial structures are formed adjacent to the gate structures, wherein the second gate structure separates two epitaxial structures and the two epitaxial structures are between the first and third gate structures. The second gate structure is removed. A conductive region is formed to connect the epitaxial structures between the first and third gate structures.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: May 11, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Sipeng Gu, Jiehui Shu, Haiting Wang
  • Patent number: 10998428
    Abstract: Examples of an integrated circuit and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a substrate that includes: a plurality of fins extending above a remainder of the substrate; a first region that includes a first fence region that contains a first subset of the plurality of fins; and a second region that includes a second fence region that contains a second subset of the plurality of fins. The first region has a first performance characteristic, and the second region has a second performance characteristic that is different from the first. Based on the first performance characteristic, the first subset of the plurality of fins is recessed to a first height, and based on the second performance characteristic, the second subset of the plurality of fins is recessed to a second height that is less than the first height.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Wei-Chiang Hung, Wei-Hao Huang
  • Patent number: 10991711
    Abstract: Semiconductor structures and methods of making the same. The semiconductor structures including at least two vertically stacked nanosheet devices. In one embodiment, an integrated circuit includes a plurality of horizontal nanosheet devices (HNS devices) that are stacked vertically, on top of each other, relative to a top surface of a substrate. The plurality of HNS devices including a first HNS device and a second HNS device that each have source and drain structures.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: April 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan, Jeng-Bang Yau
  • Patent number: 10978344
    Abstract: A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Hao Liu, Wen-Yen Chen, Tz-Shian Chen, Cheng-Jung Sung, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Syun-Ming Jang
  • Patent number: 10964696
    Abstract: A semiconductor device includes a first channel region disposed over a substrate, a first source region and a first drain region disposed over the substrate and connected to the first channel region such that the first channel region is disposed between the first source region and the first drain region, a gate dielectric layer disposed on and wrapping the first channel region, a gate electrode layer disposed on the gate dielectric layer and wrapping the first channel region, and a second source region and a second drain region disposed over the substrate and below the first source region and the first drain region, respectively. The second source region and the second drain region are in contact with the gate dielectric layer. A lattice constant of the first source region and the first drain region is different from a lattice constant of the second source region and the second drain region.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Ka-Hing Fung
  • Patent number: 10956622
    Abstract: The present invention provides a thermal hardware-based data security device that is capable of physically, hardware-wise, and permanently erasing data stored in a memory and of enabling a storage device to be reused, and a method thereof. The thermal hardware-based data security device includes: a memory chip capable of storing data; a heater module which supplies heat to permanently erase the data stored in a memory cell within the memory chip; and a switch module which short-circuits the heater module between a power supply unit and a ground when switched on, and thus, controls the heater module to be operated.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: March 23, 2021
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Yang-Kyu Choi, Jun-Young Park
  • Patent number: 10957535
    Abstract: There is provided a method of forming a semiconductor film, including: a first process of supplying a first semiconductor raw material gas onto a substrate having recesses formed therein to form a first semiconductor film in each of the recesses, each of the recesses being covered with an insulating film; a second process of supplying a halogen-containing etching gas onto the substrate to etch the first semiconductor film while exposing a surface of the insulating film in an upper portion of an inner wall of each of the recesses and leaving the first semiconductor film formed on a bottom surface of each of the recesses; and a third process of simultaneously supplying a halogen-containing semiconductor gas and a semiconductor hydride gas onto the substrate to form a second semiconductor film on the first semiconductor film formed on the bottom surface of each of the recesses.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: March 23, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yutaka Motoyama, Younggi Hong
  • Patent number: 10957703
    Abstract: An example embodiment comprises a method for fabrication of a non-volatile memory (NVM) device. An isolation structure is formed in a substrate between first and second locations for first and second NVM cells. A common charge trapping layer is formed as a continuous structure over the substrate, where a first portion of the charge trapping layer is disposed directly over the isolation structure and second portions of the charge trapping layer are disposed directly over the first and second substrate locations. Nitrogen doping of the first portion of the charge trapping layer is performed, where after the nitrogen doping is performed the first portion of the charge trapping layer includes a higher nitrogen concentration than the second portions. The first and second NVM cells are then formed over the first and second substrate locations, where the first and second NVM cells include the second portions of the charge trapping layer.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: March 23, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Pawan Kishore Singh, Shivananda Shetty, James Pak
  • Patent number: 10957602
    Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor is a grading strained stressor including multiple graded portions formed at graded depths. The first stressor is configured to create one of a graded compressive stress or a graded tensile stress.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: March 23, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Che-Wei Yang, Hao-Hsiung Lin, Samuel C. Pan
  • Patent number: 10957600
    Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Chia Tai Lin, Chao-Cheng Chen
  • Patent number: 10930495
    Abstract: Examples of an integrated circuit with a gate structure and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate having a channel region. A gate dielectric is formed on the channel region, and a layer containing a dopant is formed on the gate dielectric. The workpiece is annealed to transfer the dopant to the gate dielectric, and the layer is removed after the annealing. In some such examples, after the layer is removed, a work function layer is formed on the gate dielectric and a fill material is formed on the work function layer to form a gate structure.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang Cheng, Yen-Yu Chen
  • Patent number: 10910479
    Abstract: A semiconductor device includes a substrate; a fin structure formed on a substrate; and a gate feature formed over the fin structure, the gate feature comprising a gate dielectric layer, wherein the gate dielectric layer traverses the fin structure to overlay a central portion of the fin structure and opposite side portions of the fin structure that are located in respective undercuts formed in respective portions of a dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend beyond respective sidewalls of the gate feature and away from the central portion of the fin structure.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: February 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Guan-Jie Shen, Chia-Der Chang, Chih-Hsiung Lin
  • Patent number: 10886180
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a plurality of fins on a substrate. A fin end spacer is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. A gate electrode layer is formed on the insulating layer and wrapping around the each channel region. Sidewall spacers are formed on the gate electrode layer.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: January 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Tzu-Chung Wang, Kai-Tai Chang, Wei-Sheng Yun
  • Patent number: 10861928
    Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiao-Han Liu, Hoppy Lee, Chung-Yu Chiang, Po-Nien Chen, Chih-Yung Lin
  • Patent number: 10861856
    Abstract: A method for fabricating a semiconductor device includes: forming a first conductive layer; forming a second conductive layer over the first conductive layer; forming a conductive line by etching the second conductive layer; etching a portion of the first conductive layer to form a plug head having the same critical dimension as the conductive line; forming a first spacer that covers the conductive line and the plug head; etching the remaining first conductive layer to form a plug body that is aligned with the first spacer, wherein the plug body have a greater critical dimension than the plug head; and forming a second spacer by performing a selective oxidation onto a side wall of the plug body.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventor: Jae-Houb Chun
  • Patent number: 10861695
    Abstract: A method of forming a low-k layer includes forming a layer by providing a silicon source, a carbon source, an oxygen source, and a nitrogen source onto a substrate. The forming of the layer includes a plurality of main cycles, and each of the main cycles includes providing the silicon source, providing the carbon source, providing the oxygen source, and providing the nitrogen source, each of which is performed at least one time. Each of the main cycles includes sub-cycles in which the providing of the carbon source and the providing of the oxygen source are alternately performed.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: December 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunyoung Lee, Minjae Kang, Se-Yeon Kim, Teawon Kim, Yong-Suk Tak, Sunjung Kim