Abstract: Low-power, dual sensitivity thin oxide FG-MOSFET sensors in RF-CMOS technology for a wireless X-ray dosimeter chip, methods for radiation measurement and for charging and discharging the sensors are described. The FG-MOSFET sensor from a 0.13 ?m (RF-CMOS process, includes a thin oxide layer having a device region, a source and a drain associated with the device well region, separated by a channel region, a floating gate extending over the channel region, and a floating gate extension extending over the thin oxide layer adjacent to the device well region. In a matched sensor pair for dual sensitivity radiation measurement, the floating gate and the floating gate extension of a FG-MOSFET higher sensitivity sensor are without a salicide layer or a silicide layer formed thereon and the floating gate and the floating gate extension of a FG-MOSFET lower sensitivity sensor have a salicide layer or a silicide layer formed thereon.

Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.

Abstract: An integrated circuit (IC) includes a first field-plated field effect transistor (FET), and a second field-plated FET, and functional circuitry configured together with the field-plated FETs for realizing at least one circuit function in a semiconductor surface layer on a substrate. The field-plated FETs include a gate structure including a gate electrode partially over a LOCOS field relief oxide and partially over a gate dielectric layer. The LOCOS field relief oxide thickness for the first field-plated FET is thicker than the LOCOS field relief oxide thickness for the second field-plated FET. There are sources and drains on respective sides of the gate structures in the semiconductor surface layer.

Abstract: One illustrative device disclosed herein includes a layer of insulating material having an upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein the recessed conductive interconnect structure has a recessed upper surface that is positioned at a second level that is below the first level. In this example, the device also includes a recess defined in the recessed conductive interconnect structure, a memory cell positioned above the recessed conductive interconnect structure and a conductive via plug that is conductively coupled to the recessed conductive interconnect structure and a lower conductive material of the memory cell, wherein at least a portion of the conductive via plug is positioned in the recess defined in the recessed conductive interconnect.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor device with reduced gate height budget and methods of manufacture. The method includes: forming a plurality of gate structures on a substrate; recessing material of the plurality of gate structures to below a surface of an insulator material; forming trenches in the insulator material and underlying material adjacent to sidewalls of the plurality of gate structures; and filling the recesses and trenches with a capping material.

Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.

Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.

Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices for forming conductive paths between fins for contact-to-gate shorting. One method includes, for instance: obtaining wafer with a substrate, at least one fin, at least one hard mask, and an oxide layer; etching the oxide layer to reveal at least one of a portion of the hard masks; forming sacrificial pillars over the substrate; forming sacrificial gates, wherein at least one sacrificial gate contacts at least one sacrificial pillar; growing an epitaxial layer between the at least one sacrificial gate and the at least one sacrificial pillar; starting a RMG process on the sacrificial gates; etching to remove the sacrificial pillars and form pillar openings; and completing the RMG process to fill the pillar openings and the gate openings with a metal.

Abstract: A semiconductor device includes an active region having a doped region, a first contact member on the doped region, gate structures including a first gate structure having a first gate and a second gate structure having a second gate, the first and second gate structures being adjacent to each other and on opposite sides of the first contact member, an interlayer dielectric layer on the active region and surrounding the first and second gate structures, and the first contact member, a first insulator layer on a portion of the interlayer dielectric layer, a first contact on an upper surface of the first gate and a second contact on an upper surface of the second gate, and a second insulator layer surrounding the first and second contacts each having an upper surface lower than an upper surface of the second insulator layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to variable space mandrel cut for self-aligned double patterning and methods of manufacture. The method includes: forming a plurality of mandrels on a substrate; forming spacers about the plurality of mandrels and exposed portions of the substrate; removing a portion of at least one of the plurality of mandrels to form an opening; and filling in the opening with material.

Abstract: A method includes providing a semiconductor structure including an active region having a first doped region, a first contact member on the first doped region, first and second gates on opposite sides of the first contact member, an interlayer dielectric layer surrounding the first and second gates and the first contact member. The method also includes forming a first insulator layer having first and second contact holes, forming a second insulator layer on sidewalls of the first and second contact holes, filling the first and second contact holes with a first conductive material to form first and second contacts to the first and second gates, forming a third insulator layer on the first and second contacts, selectively etching the first insulator layer to form a third contact hole, and filling the third contact hole with a second conductive material to form a third contact to the first contact member.

Abstract: A semiconductor pattern structure includes a substrate, an input/output (I/O) region defined on the substrate, a core region defined on the substrate, a dummy region defined on the substrate, and a gate electrode formed on the substrate. The dummy region is formed between the I/O region and the core region. The gate electrode crosses the I/O region and covers a portion of the dummy region.

Abstract: In a p-type field effect transistor, a pair of spacers are formed over the top surface of a substrate. A channel recess cavity includes an indentation in the substrate top surface between the pair of spacers. A gate stack has a bottom portion in the channel recess cavity and a top portion extending outside the channel recess cavity. A source/drain (S/D) recess cavity has a bottom surface and sidewalls below the substrate top surface. The S/D recess cavity has a portion extending below the gate stack. A strained material is filled the S/D recess cavity.

Abstract: Methods of fabricating semiconductor devices may include forming an isolation region that defines a plurality of fin active regions on a semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate, forming a first hard mask line that crosses first and second fin active regions and an edge bard mask line that crosses an edge fin active region, and forming a gate cut mask having a plurality of gate cut openings. The plurality of gate cut openings may include first and second gate cut openings that have a first width and are adjacent to the first and second fin active regions, respectively, and an edge gate cut opening that is adjacent to the edge fin active region and has a second width that is greater than the first width but smaller than twice a size of the first width.

Abstract: The method includes forming a first opening in a dielectric layer exposing a source drain region of an SRAM device and forming a second opening in the dielectric layer exposing a source drain region of a logic device, forming a third opening in the dielectric layer exposing a gate of the SRAM device and forming a fourth opening in the dielectric layer exposing a gate of the logic device, forming a first sidewall spacer in the third opening and forming a second sidewall spacer in the fourth opening, recessing a portion of the first sidewall spacer without recessing the second sidewall spacer, forming a strapped contact in the first and third openings, the strapped contact creates an electrical connection between the source drain region of the SRAM device and the gate of the SRAM device, the electrical connection is directly above a remaining portion of the first sidewall spacer.

Abstract: The method includes forming a first opening in a dielectric layer exposing a source drain region of an SRAM device and forming a second opening in the dielectric layer exposing a source drain region of a logic device, forming a third opening in the dielectric layer exposing a gate of the SRAM device and forming a fourth opening in the dielectric layer exposing a gate of the logic device, forming a first sidewall spacer in the third opening and forming a second sidewall spacer in the fourth opening, recessing a portion of the first sidewall spacer without recessing the second sidewall spacer, forming a strapped contact in the first and third openings, the strapped contact creates an electrical connection between the source drain region of the SRAM device and the gate of the SRAM device, the electrical connection is directly above a remaining portion of the first sidewall spacer.

Abstract: A method includes forming a plurality of fins on a substrate, conformally depositing a nitride liner above and in direct contact with the plurality of fins and the substrate, removing a top portion of the nitride liner above the plurality of fins to expose a top surface of the plurality of fins, forming a gate over a first portion of the plurality of fins, a second portion of the plurality of fins remains exposed, forming spacers on opposite sidewalls of the nitride liner on the second portion of the plurality of fins, removing the second portion of the plurality of fins to form a trench between opposing sidewalls of the nitride liner, and forming an epitaxial layer in the trench, the lateral growth of the epitaxial layer is constrained by the nitride liner to form constrained source-drain regions.

Abstract: A method of forming an integrated circuit including forming a first diffusion area and a second diffusion area on a substrate, wherein the first diffusion area is configured for a first type transistor, the second diffusion area is configured for a second type transistor. The method further includes forming first source and drain regions in the first diffusion area. The method further includes forming second source and drain regions in the second diffusion area. The method further includes forming a gate electrode extending across the first diffusion area and the second diffusion area. The method further includes forming a first metallic layer, a second metallic layer, and a third metallic layer. The first metallic layer is electrically coupled with the first source region. The second metallic layer is electrically coupled with the first and second drain regions. The third metallic layer is electrically coupled with the second source region.

Abstract: Methods of fabricating transistors having raised active region(s) with at least partially angled upper surfaces are provided. The method includes, for instance: providing a gate structure disposed over a substrate, the gate structure including a conformal spacer layer; forming a raised active region adjoining a sidewall of the conformal spacer layer; providing a protective material over the raised active region; selectively etching-back the sidewall of the conformal spacer layer, exposing a side portion of the raised active region below the protective material; and etching the exposed side portion of the raised active region to partially undercut the protective material, wherein the etching facilitates defining, at least in part, an at least partially angled upper surface of the raised active region of the transistor.

Abstract: A semiconductor device includes an active area having a source and a gate. A gate metal contact is deposited above and forms an electrical contact with the gate and a source metal contact is deposited above and forms an electrical contact with the source. The source metal contact includes a plurality of metal through contacts positioned adjacent a side of the active area, the plurality of metal through contacts being spaced at intervals from one another and arranged in two or more rows.

Abstract: One illustrative method disclosed herein includes forming a plurality of spaced-apart fin structures in a semiconductor substrate, wherein the fin structures define a portion of an alignment/overlay mark trench where at least a portion of an alignment/overlay mark will be formed, forming at least one layer of insulating material that overfills the alignment/overlay mark trench and removing excess portions of the layer of insulating material positioned above an upper surface of the plurality of fins to thereby define at least a portion of the alignment/overlay mark positioned within the alignment/overlay mark trench. A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to partially define an alignment/overlay mark trench, an alignment/overlay mark consisting only of at least one insulating material positioned within the alignment/overlay mark trench, and a plurality of FinFET semiconductor devices formed in and above the substrate.

Abstract: Disclosed are methods for forming fins. In an example embodiment, a method includes providing a substrate that includes at least two elongated structures separated by an isolation region. Each elongated structure comprises a semiconductor alloy of a first semiconductor material and a second semiconductor material, and a relaxed portion of the elongated structure includes the semiconductor alloy in a relaxed and substantially defect-free condition. The method further includes subjecting the substrate to a condensation-oxidation, such that each elongated structure forms a fin and an oxide layer. The fin includes a fin base portion formed of the semiconductor alloy and a fin top portion of the first semiconductor material in a strained condition. The fin top portion is formed by condensation of the first semiconductor material. The oxide layer includes an oxide of the second semiconductor material. The method further includes removing at least some of the oxide layer.

Abstract: A method of forming a contact hole includes providing a substrate. A nitrogen-containing dielectric layer, a first material layer, a second material layer, an oxygen-containing dielectric layer and a patterned photoresist layer cover the substrate from bottom to top. Then, the oxygen-containing dielectric layer is etched by taking the second material layer as a first etching stop layer to form a patterned oxygen-containing dielectric layer. Latter, the second material layer is etched by taking the first material layer as a second etching stop layer to form a patterned second material layer. Subsequently, the first material layer is etched by taking the nitrogen-containing dielectric layer as a third etching stop layer to form a patterned first material layer. Finally, the nitrogen-containing dielectric layer is etched until the substrate is exposed.

Abstract: The present invention is directed to a semiconductor memory device including a plurality of first level contacts arranged in an array with every third row vacant along a first direction, thereby forming multiple contact regions separated by multiple vacant regions along the first direction with each of the multiple contact regions including a first row and a second row of the first level contacts extending along a second direction; a first and second plurality of second level contacts formed on top of the first level contacts with the second plurality of second level contacts having elongated shape extending into the vacant regions adjacent thereto; and a first and second plurality of memory elements formed on top of the first and second plurality of second level contacts, respectively, thereby permitting the memory elements to have greater center-to-center distance between two closest neighbors than the first level contacts.

Abstract: Angled directional ion beams are directed to sidewalls of a gate structure that straddles at least one semiconductor fin. The directions of the angled directional ion beams are contained within a vertical plane that is parallel to the sidewalls of the at least one semiconductor. A pair of gate spacers are formed on sidewalls of the gate structure by accumulation of the deposited dielectric material from the angled directional ion beams and without use of an anisotropic etch, while the sidewalls of the semiconductor fins parallel to the directional ion beams remain physically exposed. A selective epitaxy process can be performed to form raised active regions by growing a semiconductor material from the sidewalls of the semiconductor fins.

Abstract: A method for fabricating a semiconductor device includes forming first and second gate structures overlying the semiconductor substrate, and depositing a layer of a silicide-resistant material over the first and second gate structures and over the semiconductor substrate. The method further includes forming sidewall spacers from the layer of silicide-resistant material adjacent the first gate structure and removing the silicide-resistant material adjacent the sidewall spacers to expose the silicon substrate in a source and drain region. Still further, the method includes implanting conductivity determining impurities in the source and drain region, depositing a silicide forming metal, and annealing the semiconductor device to form a silicide in the source and drain region. The silicide-resistant material is not removed from over the second gate structure so as to prevent silicide formation at the second gate structure.

Abstract: A non-volatile memory device includes a substrate including an active region and a field region, selection transistors and cell transistors on the active region, bit line contacts on the bridge portions, and shared bit lines electrically connected to the bit line contacts. The active region includes string portions and bridge portions. The string portions extend in a first direction and are arranged in a second direction substantially perpendicular to the first direction, and the bridge portions connect at least two adjacent string portions. Each bridge portion has a length in the first direction equal to or longer than about twice a width of each bit line contact in the first direction.

Abstract: An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.

Abstract: Dimensions of structures in integrated circuits are shrinking with each new fabrication technology generation. Maintaining control of profiles of structures in transistors and interconnects is becoming more important to sustaining profitable integrated circuit production facilities. Measuring profiles of structures with many elements in integrated circuits, such as MOS transistor gates with recessed regions for Si—Ge epitaxial layers, is not cost effective for the commonly used metrology techniques: SEM, TEM and AFM. Scatterometry is technically unfeasible due to the number of elements and optical constants. The instant invention is a simplified scatterometry structure which reproduces the profiles of a structure to be profiled in a simpler structure that is compatible with conventional scatterometric techniques. A method of fabricating a transistor and an integrated circuit using the inventive simplified scatterometry structure are also disclosed.

Abstract: A plurality of doped sacrificial semiconductor material portions of a first width and a plurality of doped sacrificial semiconductor material portions of a second width, which is different from the first width, are provided on a sacrificial gate dielectric material. Exposed portions of the sacrificial dielectric material are removed. A dielectric material is formed adjacent each doped sacrificial semiconductor material portion such that an upper surface of each doped sacrificial semiconductor material portion is exposed. Each doped sacrificial semiconductor material portion is removed providing a first set of gate cavities having the first width and a second set of gate cavities having the second width. Each gate cavity is filled with a gate structure. The gate structures formed in the first set of gate cavities have the first width, while the gate structure formed in the second set of gate cavities have the second width.

Abstract: Each unit pixel includes a photoelectric converter formed above a semiconductor region, an amplifier transistor formed in the semiconductor region, and including a gate electrode connected to the photoelectric converter, a reset transistor configured to reset a potential of the gate electrode, and an isolation region formed in the semiconductor region between the amplifier transistor and the reset transistor to electrically isolate the amplifier transistor from the reset transistor. The amplifier transistor includes a source/drain region. The source/drain region has a single source/drain structure.

Abstract: An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer.

Abstract: The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region, forming first and second gate stacks over the first and second regions, respectively, the first and second gate stacks each including a dummy gate electrode, removing the dummy gate electrodes from the first and second gate stacks, respectively, thereby forming trenches, forming a metal layer to partially fill the trenches, forming an oxide layer over the metal layer filling a remaining portion of the trenches, applying a first treatment to the oxide layer, forming a patterned photoresist layer on the oxide layer overlying the first region, applying a second treatment to the oxide layer overlying the second region, etching the oxide layer overlying the second region, etching the first metal layer overlying the second region, removing the patterned photoresist layer, and removing the oxide layer overlying the first region.

Abstract: Various aspects of the invention are directed to memory circuits and their implementation. According to an example embodiment, an apparatus includes a channel region between raised source and drain regions which are configured and arranged with respective bandgap offsets relative to the channel region to confine carriers in the channel region. The apparatus also includes front and back gates respectively separated from the channel region by gate dielectrics. The raised source and drain regions have respective portions laterally adjacent the front gate and adjacent the channel region. Carriers are stored in the channel region via application of voltage(s) to the front and back gates, and relative to bias(es) at the source and drain regions.

Abstract: An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.

Abstract: A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells formed on a semiconductor substrate, each memory cell including source and drain regions separately formed on a surface portion of the substrate, buried insulating films formed in portions of the substrate that lie under the source and drain regions and each having a dielectric constant smaller than that of the substrate, a tunnel insulating film formed on a channel region formed between the source and drain regions, a charge storage layer formed of a dielectric body on the tunnel insulating film, a block insulating film formed on the charge storage layer, and a control gate electrode formed on the block insulating film.

Abstract: When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.

Abstract: A nano resonator includes a substrate, a first insulating layer disposed on the substrate, a first source disposed on the first insulating layer at a first position, a first drain disposed on the first insulating layer at a second position spaced apart from the first position so that the first drain faces the first source, a first nano-wire channel having a first end connected to the first source and a second end connected to the first drain, and having a doping type and a doping concentration that are identical to a doping type and a doping concentration of the first source and the first drain, and a second nano-wire channel disposed at a predetermined distance from the first nano-wire channel in a direction perpendicular to the substrate or a direction parallel to the substrate.

Abstract: Methods are provided for manufacturing a thin film storage memory cell. The method includes forming a long select gate on a substrate, and forming thin film storage crystals overlying the long select gate and the adjacent substrate. A left and right control gate are formed on opposite sides of the long select gate, and a long select gate center portion is removed to form a left select gate and a right select gate with a gap therebetween. A drain is formed in the substrate underlying the gap, and a left and right source are formed in the substrate aligned with the left and right control gate.

Abstract: A semiconductor device includes a semiconductor substrate, a body region disposed in the semiconductor substrate and having a first conductivity type, a source region disposed in the semiconductor substrate adjacent the body region and having a second conductivity type, a drain region disposed in the semiconductor substrate, having the second conductivity type, and spaced from the source region to define a conduction path, a gate structure supported by the semiconductor substrate, configured to control formation of a channel in the conduction path during operation, and having a side adjacent the source region that comprises a notch, the notch defining a notch area, and a notch region disposed in the semiconductor substrate in the notch area and having the first conductivity type.

Abstract: An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height.

Abstract: According to a process for manufacturing an integrated power device, projections and depressions are formed in a semiconductor body that extend in a first direction and are arranged alternated in succession in a second direction, transversely to the first direction. Further provided are a first conduction region and a second conduction region. The first conduction region and the second conduction region define a current flow direction parallel to the first direction, along the projections and the depressions. To form the projections and the depressions, portions of the semiconductor body that extend in the first direction and correspond to the depressions, are selectively oxidized.

Abstract: A semiconductor package may include a package substrate, a first semiconductor chip and a second semiconductor chip. The first semiconductor chip may be arranged on the package substrate. The first semiconductor chip may have a plug electrically connected to the package substrate and at least one insulating hole arranged around the plug. The second semiconductor chip may be arranged on the first semiconductor chip. The second semiconductor chip may be electrically connected to the plug. Thus, the insulating hole and the insulating member may ensure an electrical isolation between the plug and the first semiconductor chip, and between the plugs.

Abstract: Embodiments of transistors comprise a gate stack overlying a semiconductor material. The gate stack comprises a deposited oxide layer overlying the semiconductor material, an oxygen-diffusion barrier layer overlying the deposited oxide layer, a high-k dielectric layer overlying the oxygen-diffusion barrier layer, and a conductive material (e.g., an oxygen-gettering conductive material) overlying the high-k dielectric layer. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.

Abstract: Embodiments of the invention provide dual workfunction semiconductor devices and methods for manufacturing thereof. According to one embodiment, the method includes providing a substrate containing first and second device regions, depositing a dielectric film on the substrate, and forming a first metal-containing gate electrode film on the dielectric film, wherein a thickness of the first metal-containing gate electrode film is less over the first device region than over the second device region. The method further includes depositing a second metal-containing gate electrode film on the first metal-containing gate electrode film, patterning the second metal-containing gate electrode film, the first metal-containing gate electrode film, and the dielectric film to form a first gate stack above the first device region and a second gate stack above the second device region.

Abstract: A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.

Abstract: An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.

Abstract: In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.

Abstract: A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.