Abstract: A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of moisture through the sidewall of an exposed fuse opening portion, an etch stop layer is formed over a fuse line. A guard ring opening portion is formed using the etch stop layer. The guard ring opening portion is filled with a material for forming the uppermost wiring of multi-level interconnect wirings or the material of a passivation layer, thereby forming the guard ring concurrently with the uppermost interconnect wiring or the passivation layer. Accordingly, permeation of moisture through an interlayer insulating layer or the interface between interlayer insulating layers around the fuse opening portion can be efficiently prevented by a simple process.

Abstract: In a semiconductor device and a method of fabricating the same, a fuse and a capacitor are formed at a same level on a semiconductor substrate having a fuse area and a capacitor area. The fuse is placed on the fuse area, and a lower plate is placed on the capacitor area. The lower plate is located on a same plane as the fuse. Further, an upper plate is located above the lower plate, and a capping layer is interposed between the lower plate and the upper plate. Therefore, the fuse and the capacitor can be formed at the same time, thereby minimizing photolithography and etch process steps.

Abstract: A semiconductor device includes a protection target element formed on a semiconductor substrate and includes a protection target element electrode, a substrate connecting part including a substrate connecting electrode electrically connected to the semiconductor substrate and a fuse structure provided between the protection target element electrode and the substrate connecting electrode and includes a fuse film configured to be torn by applying a predetermined current thereto. The protection target element electrode, the substrate connecting electrode and the fuse film are formed of an integral conductive film as long as the fuse film is not torn.

Abstract: A redundant fuse is provided with a redundant length, here a winding structure, at one end thereof, here at a vicinity of a second wire side to which a high voltage (Vcc) is impressed. A disconnected portion is provided between the other end side of the redundant fuse, here a second wire side which is on the ground potential (GND) and the winding structure.

Abstract: A semiconductor fuse and methods of making the same. The fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a substrate, forming a trench feature in the substrate, depositing fuse material in the trench feature, depositing compressive stress liner material over the fuse material, and patterning the compressive stress liner material.

Abstract: An anti-fuse is provided. The anti-fuse includes a substrate, a gate disposed over the substrate, a gate dielectric layer sandwiched between the substrate and the gate, and two source/drain regions in the substrate at respective sides of the gate. The gate and the substrate have the same conductive type, but the conductive type of the gate and the substrate is different from that of the two source/drain regions.

Abstract: The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the invention includes methods in which one or more processing steps associated with fabrication and patterning of bond pads and redistribution layers is conducted simultaneously over a fuse box region to form and/or remove materials that are directly over the fuse box region.

Abstract: A method for making a semiconductor device having a fuse window above a substrate is disclosed. The semiconductor device has at least one fuse protection circuit located under the fuse window. The fuse protection circuit includes a fuse having a first end connected to a first voltage and a second end. A first transistor having a drain is connected to the second end of the fuse, a gate for receiving an input signal, and a source is connected to a second voltage. A second transistor having a drain is connected to the second end of the fuse, a gate, and a source is connected to the second voltage. A first diode having an anode and a cathode, the anode of the first diode is connected to the second voltage and the cathode of the first diode is connected to the second end of the fuse. A second diode having an anode and a cathode, the anode of the second diode is connected to the second end of the fuse and the cathode of the second diode is connected to the first voltage.

Abstract: A repair fuse element and method of construction are disclosed that eliminate or substantially reduce the disadvantages and problems associated with prior fuse elements. In one embodiment, the fuse element is constructed with a rectangular-shaped contact. The contact is made long enough so that it makes contact at each end with a metal layer, but design rule spacing is still maintained between the connections with the metal layer. The overlapping areas between the rectangular contact and the metal layers are asymmetrical. Alternatively, these overlapping areas are smaller than the design rule overlap requirements. In a second embodiment, a fuse element is constructed with a plurality of rectangular-shaped contacts. As a result, a current value that is significantly lower than conventional fuse current values, can be used to melt such a contact or blow the fuse.

Abstract: A fin type field effect transistor includes a semiconductor substrate, an active fin, a first hard mask layer pattern, a gate insulation layer pattern, a first conductive layer pattern, and source/drain regions. The active fin includes a semiconductor material and is formed on the substrate and extends in a direction away from a major surface of the substrate. The first hard mask layer pattern is formed on a distal surface of the active fin from the substrate. The gate insulation layer is formed on a sidewall portion of the active fin. The first conductive layer pattern includes a metal silicide and is formed on surfaces of the substrate and the gate insulation layer pattern, and on a sidewall of the first hard mask pattern. The source/drain regions are formed in the active fin on opposite sides of the first conductive layer pattern.

Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.

Abstract: A fuse box includes a semiconductor substrate having a fuse region, and a lower line in the fuse region that has a first region and a second region. An upper line is placed on the upper part of the lower line to overlap the first region. A fuse is placed on the upper part of the upper line, and connects electrically to the second region of the lower line and the upper surface of the upper line. A lower interlayer insulating layer is interposed between the lower line and the upper line, and an upper interlayer insulating layer is interposed between the upper line and the fuse. The fuse is formed on the upper interlayer insulating layer. Both ends of the fuse connect electrically to the second region of the lower line and the upper line, respectively, through fuse holes penetrating the lower and upper interlayer insulating layers.

Abstract: A semiconductor device has a semiconductor substrate, first and second insulating layers, a fuse, a diffusion layer and a conductive pattern. The first insulating layer is selectively formed on a surface of the semiconductor substrate. The fuse is formed on the first insulating layer. The diffusion layer is formed on the surface of the semiconductor substrate. The diffusion layer is applied to a fixed potential. The second insulating layer is formed on the fuse. The conductive pattern is formed on the second insulating layer. The conductive pattern surrounds the fuse. Further, the conductive pattern is electrically connected to the diffusion layer.

Abstract: A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer includes a heat dissipating structural feature adjacent the fin, and a portion of the gate conductor contacts the heat dissipating structural feature. The heat dissipating structural feature can comprise a recess within the insulator layer or a thermal conductor extending through the insulator layer.

Abstract: A semiconductor structure including at least one e-fuse embedded within a trench that is located in a semiconductor substrate (bulk or semiconductor-on-insulator) is provided. In accordance with the present invention, the e-fuse is in electrical contact with a dopant region that is located within the semiconductor substrate. The present invention also provides a method of fabricating such a semiconductor structure in which the embedded e-fuse is formed substantially at the same time with the trench isolation regions.

Abstract: A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is preferably a material that minimizes stresses on the crystalline body, such as an oxide. The body may be doped, and may also include a silicide layer on the upper surface. This fuse structure may be successfully programmed over a wide range of programming voltages and time.

Abstract: In a fuse region of a semiconductor device, and a method of fabricating the same, the fuse region includes an interlayer insulating layer on a semiconductor substrate, a plurality of fuses on the interlayer insulating layer disposed in parallel with each other, a blocking layer on the interlayer insulating layer between each of the plurality of fuses and in parallel with the plurality of fuses, and a plurality of fuse grooves recessed into the interlayer insulating layer between each of the plurality of fuses and the blocking layer.

Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film supported by a semiconductor substrate, forming an aluminum layer supported by the first insulating film, etching the aluminum layer to form a bonding pad and fuse elements, depositing by plasma chemical vapor deposition a second insulating film covering the bonding pad and the fuse elements, the second insulating film having planar portions between the fuse elements and ridged portions opposite the fuse elements, depositing by plasma chemical vapor deposition a third insulating film covering the second insulating film, etching the third insulating film to form a first hole exposing a first region of the second insulating film, opposite the fuse elements, and a second hole exposing a second region of the second insulating film, opposite at least part of said bonding pad, and etching the second insulating film to form a third hole exposing at least part of the bonding pad.

Abstract: A semiconductor device (10) such as a FinFET transistor of small dimensions is formed in a process that permits substantially uniform ion implanting (32) of a source (14) electrode and a drain (16) electrode adjacent to an intervening gate (18) and channel (23) connected via source/drain extensions (22, 24) which form a fin. At small dimensions, ion implanting may cause irreparable crystal damage to any thin areas of silicon such as the fin area. To permit a high concentration/low resistance source/drain extension, a sacrificial doping layer (28, 30) is formed on the sides of the fin area. Dopants from the sacrificial doping layer are diffused into the source electrode and the drain electrode using heat. Subsequently a substantial portion, or all, of the sacrificial doping layer is removed from the fin.

Abstract: An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-type doping layer and the N-type doping region. The second P-type doping layer with higher doping level, which has a linear structure, is served as a bit line. An electrically conductive layer is disposed over the P-type semiconductor substrate. The electrically conductive layer also has a linear structure that crosses over the first P-type doping layer. The first N-type doping layer is disposed in the P-type semiconductor substrate between the electrically conductive layer and the first P-type doping layer. The arrangement of N-type and P-type doping layer is used to be selective diode device. An anti-fuse layer is disposed between the electrically conductive layer and the first N-type doping layer.

Abstract: A method of forming an abrupt junction device with a semiconductor substrate is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. A thickening layer is formed by selective epitaxial growth on the semiconductor substrate adjacent the sidewall spacer. Raised source/drain dopant implanted regions are formed in at least a portion of the thickening layer. Silicide layers are formed in at least a portion of the raised source/drain dopant implanted regions to form source/drain regions, beneath the silicide layers, that are enriched with dopant from the silicide layers. A dielectric layer is deposited over the silicide layers, and contacts are then formed in the dielectric layer to the silicide layers.

Abstract: A gate insulating film on a silicon substrate of includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the transition metal and aluminum in the vicinity of the interface with the SiO2 film and the vicinity of the interface with the gate electrode. Furthermore, it is preferable that the concentration of silicon is the highest at least in one of the vicinity of the interface with the SiO2 film or the vicinity of the interface with the gate electrode, gradually decreases with distance from these interfaces, and becomes the lowest in a central part of the high-k film.

Abstract: Method of manufacturing a semiconductor chip. An array region gate stack is formed on an array region of a substrate and a periphery region gate stack is formed on a periphery region of a substrate. A first dielectric material, a charge-storing material, and a second dielectric material are deposited over the substrate. Portions of the first dielectric material, the charge-storing material, and the second dielectric material are removed to form storage structures on the array region gate stack and on the periphery region gate stack. The storage structures have a generally L-shaped cross-section. A first source/drain region is formed in the array region well. A third dielectric material and a spacer material are deposited over the substrate. Portions of the third dielectric material and the spacer material are removed to form spacers. A second source/drain region is formed in the periphery region well.

Abstract: A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is preferably a material that minimizes stresses on the crystalline body, such as an oxide. The body may be doped, and may also include a silicide layer on the upper surface. This fuse structure may be successfully programmed over a wide range of programming voltages and time.

Abstract: An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal layer overlies the sense area. A plurality of polysilicon gate stripes, polysilicon openings, and body stripes are disposed on the die, and extend in a continuous and uninterrupted manner from the active area into the sense area. A first region from which source dopants and contacts have been excluded surrounds a periphery of the sense area. An etched region is disposed over the first region, thereby separating and electrically isolating the sense area metal layer from the active area metal layer.

Abstract: A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate electrode of the transistor, and simultaneously introducing a negative bias to the transistor. The threshold voltage of the p-channel NVM transistor is shifted in response to the negative bias condition and the heat generated by the programming current. The high temperature accelerates the threshold voltage shift. The threshold voltage shift is accompanied by an agglomeration of material in the gate electrode. The agglomeration of material in the gate electrode is an indication of the high temperature reached during programming. The threshold voltage shift of the p-channel NVM transistor is permanent.

Abstract: An anti-fuse is manufactured by forming an isolation region including an insulating material layer buried in a surface of a device formation region on a surface of a semiconductor substrate, and by forming diffusion regions at both sides of the isolation region, then by contacting electrodes to the respective diffusion regions. The anti-fuse is initially in a non-conductive state, and is programmed to be in a permanently conductive state by a simple writing circuit.

Abstract: An electrically programmable transistor fuse having a double-gate arrangement disposed in a single layer of polysilicon in which a first gate is disposed overlapping a portion of a source region and a second gate is insulated from the first gate and disposed overlapping a portion of a drain region. The first gate includes a terminal for receiving an externally applied control signal and the second gate is capacitively couple to the drain region in which a coupling device is included for increasing the capacitive coupling of the second gate and the drain region for enabling reduction in fuse programming voltage.

Abstract: A semiconductor device comprising a substrate, a plurality of dielectric films formed on the substrate, laid one upon another, and a fuse interconnect-wire formed above the substrate and covered with a predetermined one of the dielectric films, and including a fuse main body which is to be blown to electrically disconnect the fuse interconnect-wire, which is smaller than a bottom of a fuse-blowing recess made in the predetermined dielectric film, which has a length not less than the diameter of a fuse-blowing laser beam and which opposes the bottom of the fuse-blowing recess.

Abstract: A novel fuse structure. An optimal position of laser spot is defined above a substrate. A first conductive layer is formed on part of the substrate. A dielectric layer is formed on the substrate and the first conductive layer. A second conductive layer comprising the position of laser spot is formed on part of the dielectric layer. A third conductive layer is formed on the part of the dielectric layer placed above the first conductive layer, wherein the third conductive layer is insulated from the first and second conductive layers. At least one conductive plug penetrates the dielectric layer, to electrically connect the first conductive layer and the second conductive layer. Thus, the third conductive layer serves as a floating layer to prevent the first conductive layer from being damaged in the laser blow process.

Abstract: A method of producing an antifuse includes introducing nitrogen by ion implantation means into the substrate. An oxide dielectric layer is then formed on the nitrided substrate in a wet oxidation ambient. The conditions of the ion implantation and the oxidation are controlled to generate a dielectric with uniform thickness and a low breakdown voltage when subjected to a high electric field.

Abstract: A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate electrode of the transistor, and simultaneously introducing a negative bias to the transistor. The threshold voltage of the p-channel NVM transistor is shifted in response to the negative bias condition and the heat generated by the programming current. The high temperature accelerates the threshold voltage shift. The threshold voltage shift is accompanied by an agglomeration of material in the gate electrode. The agglomeration of material in the gate electrode is an indication of the high temperature reached during programming. The threshold voltage shift of the p-channel NVM transistor is permanent.

Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.

Abstract: A method for fabricating a fuse for a semiconductor device. The method including: providing a substrate; forming a first dielectric layer on a top surface of said substrate; forming a dielectric mandrel on a top surface of said first dielectric layer; forming a second dielectric layer on top of said mandrel and a top surface of said first dielectric layer forming contact openings down to said substrate in said first and second dielectric layers on opposite sides of said mandrel, said contacts spaced away from said mandrel and leaving portions of said second dielectric layer between said mandrel and said contacts; removing said second dielectric layer from over said mandrel between said contact openings to form a trough; and filling said trough and contact openings with a conductor.

Abstract: A semiconductor device comprises a semiconductor substrate having a bonding pad region; and a bonding pad and a fuse box formed in the bonding pad region. Thus, the chip size can be reduced and the manufacturing yield can be increased.

Abstract: A FinFET structure that prevents parasitic electrical leakages between its gate region and its fin region and between its gate region and its epitaxial region (source/drain regions). The structure is formed by first forming a fin region on top of an electrically insulating layer. Next, a gate stack having gate spacers thereon is formed on top of and electrically insulated from the fin region. Then, the final S/D (source/drain) regions are formed by epitaxially growing a semiconductor material from the two ends of the fin region not covered by the gate stack. Next, another electrically insulating layer is formed on top of the structure except the gate spacers. Next, the gate spacers and portions of the gate stack beneath them are replaced with a dielectric material.

Abstract: A programmable element including a semiconductor material doped with a dopant that alters the resistance of the element when exposed to actinic radiation. Rather than producing a mechanical deformation, the radiation rearranges the bonding configuration of the dopant in the element, allowing it to be placed on a chip in close proximity to other device structures without risking damage to those structures. After formation, the programmable element is subjected to a laser anneal process in which the dopant is electrically activated. The activation process allows the dopant to donate a charge carrier to the crystal structure. Rapid cooling following laser anneal preserves the desired bonding configuration of the dopant produced in the programmable element. Laser anneals have been shown to reduce the resistivity of a programmable element by at least a factor of two.

Abstract: Disclosed is a technique capable of enhancing the degree of freedom in the layout of a rerouting layer in a wafer level CSP in which defect repairing is performed by cutting a fuse. More specifically, after the defect repairing is performed by irradiating a laser beam to a fuse, an organic passivation layer (photo-sensitive polyimide layer) is filled in a fuse opening. Thereafter, a rerouting layer, a bump land, an uppermost wiring layer, and a solder bump are formed on the organic passivation layer. In the following steps of the defect repairing, the baking process to cure an elastomer layer and the uppermost protection layer is conducted at a temperature below 260° C. in order to prevent the variance of the refresh times of memory cells.

Abstract: Programmable fuses for integrated circuits are provided. The fuses may be based on polysilicon or crystalline silicon fuse links coated with silicide or other conductive thin films. Fuses may be formed on silicon-on-insulator (SOI) substrates. A fuse may be blown by applying a programming current to the fuse link. The silicon or polysilicon in the fuses may be provided with a p-n junction. When a fuse is programmed, the silicide or other conductive film forms an open circuit. This forces current though the underlying p-n junction. Unlike conventional silicided polysilicon fuses, fuses with p-n junctions change their qualitative behavior when programmed. Unprogrammed fuses behave like resistors, while programmed fuses behave like diodes. The presence of the p-n junction allows sensing circuitry to determine in a highly accurate qualitative fashion whether a given fuse has been programmed.

Abstract: A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

Abstract: An EEPROM memory cell and a method of forming the same are provided. A portion of a floating gate is formed on walls of a trench formed on the substrate. An inside of the trench is filled with a gate electrode layer constituting a sensing line. This leads to increases in opposite areas of a floating gate and a control gate of a sensing transistor, and a decrease in an area of the floating gate in the substrate.

Abstract: A fuse device including a transistor having a source, drain, and gate. The gate includes a first and second gate contact. A current may be run from the first gate contact to the second gate contact to heat the gate. The current through the gate indirectly heats the channel region beneath the gate, causing localized annealing of the channel region. The heated gate causes dopants to diffuse from the source and drain into the channel region, permanently changing the properties of the transistor material and programming the fuse device. The fuse device functions as a transistor in an unprogrammed state, and acts as a shunt in a programmed state, caused by the shorting of the source and drain of the transistor during programming.

Abstract: An active fuse includes an active fuse geometry (120) that is used to form both a variable resistor (106) and a select transistor (110). In one embodiment, the active fuse geometry is formed in a portion of an active region (160) of a semiconductor substrate (140), and a select gate (124) is disposed over an end portion (123) of the active fuse geometry to form an integral select transistor (110) for use in programming the active fuse. The use of a shared active fuse geometry within the active region allows for reduced area requirements and improved sensing margins.

Abstract: An increased number of fuses per area are provided in this semiconductor device while complying with the predetermined distance between the fuses. The device having a first patterned, conductive interconnect plane on a passivated substrate; a second patterned, conductive interconnect plane on the first patterned, conductive passivated interconnect plane; contact devices for selectively electrically contact-connecting the patterned, conductive interconnect planes to one another; a fuse device in a nonpassivated section of the second patterned, conductive interconnect plane with predetermined fuse regions for selectively linking interconnects; the fuse device being divided into fuse modules with fuse pairs and the fuse regions thereof at a predetermined distance from one another, which can be linked to a predetermined potential via a central interconnect.

Abstract: A double gate electrode for a field effect transistor is fabricated by forming in a substrate, a trench and a tunnel that extends from a sidewall of the trench parallel to the substrate. An insulating coating is formed inside the tunnel. A bottom gate electrode is formed within the insulating coating inside the tunnel. An insulating layer is formed on the substrate and a top gate electrode is formed on the insulating layer opposite the bottom gate electrode.

Abstract: A method of forming an integrated circuit device can include forming a plurality of fuse wires on an integrated circuit substrate, and forming an insulating layer on the integrated circuit substrate and on the plurality of fuse wires so that the fuse wires are between the integrated circuit substrate and the insulating layer. A plurality of fuse cutting holes can be formed in the insulating layer wherein each of the fuse cutting holes exposes a target spot on a respective one of the fuse wires, and a cross-sectional area of the fuse wires can be reduced at the exposed target spots. Related structures are also discussed.

Abstract: A method for programming a semiconductor element in a semiconductor structure such as an IC involves reducing the backside thickness of the substrate and directing an energy beam through the backside at an opaque component of the semiconductor element. A support structure mounted on the semiconductor structure provides support during and after the thinning operation. Alternatively, the substrate can be thinned only under the semiconductor element, leaving the rest of the substrate thick enough to maintain structural integrity. The energy beam heats the opaque component. The prior thinning operation minimizes heat dissipation away from the semiconductor element, so that dopant diffusion occurs, changing the electrical characteristics of the semiconductor element. By modifying selected elements in this manner, a semiconductor structure can be permanently programmed, even if it does not include non-volatile memory. Additionally, security is enhanced since the programming leaves no visible signs.

Abstract: In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region to form a nano-rod structure. Part of the nano-rod structure is then used as a gate channel. Preferably, a gate dielectric and a gate electrode both wrap around the nano-rod structure, with the gate dielectric being between the nano-rod structure and the gate electrode, to form a transistor device.

Abstract: A programmable interconnect structure and method of operating the same provides a programmable interconnection between electrical contacts. The interconnect includes material that has a reversibly programmable resistance. The material includes a molecular matrix with ionic complexes distributed through the molecular matrix. Application of an electrical field or electric current causes the molecular composite material to assume a desired resistivity (or conductivity) state. This state is retained by the molecular composite material to thus form a conductive or a non-conductive path between the electrical contacts.

Abstract: A method of forming a semiconductor device, such as a self-passivating fuse, includes patterning an opening in a dielectric to form a fuse. A seed-layer of a copper-alloy is deposited in the opening and the opening is filled with pure copper. The copper is planarized and a passivation layer is deposited. This passivation layer can be thinned over a fuse portion of the copper. The fuse portion can then be laser fused to form a crater in an area surrounding a blown copper fuse. Exposed portions of the pure copper can then be self-passivated by annealing the device.