Abstract: A silicon carbide semiconductor device that is able to increase the gate reliability, and to provide a method for manufacturing the silicon carbide semiconductor device, and that includes: a source electrode selectively formed on a source region; a gate insulating film formed so as to extend over the source region; and a gate electrode formed on the gate insulating film. The source region includes a first source region located below the source electrode, and a second source region surrounding the first source region. The doping concentration in a superficial layer of the second source region is lower than the doping concentration in a superficial layer of the first source region. The doping concentration in the second source region is higher in a deep portion than in a superficial portion thereof.

Abstract: The invention relates to a method for forming a semiconductor structure, comprising: providing a semiconductor substrate which comprises a dummy gate formed thereon, a spacer surrounding the dummy gate, source and drain regions formed on two sides of the dummy gate, respectively, and a channel region formed in the semiconductor substrate and below the dummy gate; removing the dummy gate to form a gate opening; forming a stressed material layer in the gate opening; performing an annealing to the semiconductor substrate, the stressed material layer having tensile stress characteristics during the annealing; removing the stressed material layer in the gate opening; and forming a gate in the gate opening. By the above steps, the stress memorization technique can be applied to the pMOSFET.

Abstract: Certain embodiments provide semiconductor device including a semiconductor layer including a channel layer, a barrier layer, and a cap layer, the semiconductor layer provided on a semiconductor substrate, a drain electrode and a source electrode, an opening of the cap layer, and a gate electrode. The drain electrode and the source electrode are provided on the barrier layer. The opening is provided in the cap layer provided between the drain electrode and the source electrode, the opening being separated from the drain electrode and the source electrode. The gate electrode is provided so as to be in contact with the barrier layer exposed in the opening of the cap layer and also insulated from a side surface of the opening of the cap layer. Inside the opening, a distance between the gate electrode and the side surface of the opening increases with a decreasing distance from the barrier layer.

Abstract: Structures and methods are presented relating to formation of finFET semiconducting devices. A finFET device is presented comprising fin(s) formed on a substrate, wherein the fin(s) has a needle-shaped profile. The needle-shaped profile, in conjunction with at least a buffer layer or a doped layer, epitaxially formed on the fin(s), facilitates strain to be induced into the fin(s) by the buffer layer or the doped layer. The fin(s) can comprise silicon aligned on a first plane, while at least one of the buffer layer or the doped layer are grown on a second plane, the alignment of the first and second planes are disparate and are selected such that formation of the buffer layer or the doped layer generates a stress in the fin(s). The generated stress results in a strain being induced into the fin(s) channel region, which can improve electron and/or hole mobility in the channel.

Abstract: This specification is directed to a semiconductor device capable of reducing a leakage current by forming a first GaN layer including a plurality of GaN layers and FexNy layers interposed between the plurality of GaN layers, in a semiconductor device having the first GaN layer, an AlGaN layer, a second GaN layer, a gate electrode, a source electrode and a drain electrode which are deposited in a sequential manner, and a fabricating method thereof. To this end, a semiconductor device according to one exemplary embodiment includes a first GaN layer, an AlGaN layer on the first GaN layer, a second GaN layer on the AlGaN layer, and a source electrode, a drain electrode and a gate electrode formed on a partial area of the second GaN layer, wherein the first GaN layer comprises a plurality of GaN layers and FexNy layers interposed between the plurality of GaN layers.

Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

Abstract: A method of manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate; etching the substrate on both sides of the gate stack to form C-shaped source/drain grooves; and wet-etching the C-shaped source/drain grooves to form ?-shaped source/drain grooves. With this method, it is possible to effectively increase stress applied to a channel region, to accurately control a depth of the source/drain grooves, and to reduce roughness of side walls and bottom portions of the grooves and thus reduce defects by etching the C-shaped source/drain grooves and then further wet-etching them to form the ?-shaped source/drain grooves.

Abstract: The present invention discloses a semiconductor device, comprising: a substrate, a gate stack structure on the substrate, source and drain regions in the substrate on both sides of the gate stack structure, and a channel region between the source and drain regions in the substrate, characterized in that at least one of the source and drain regions comprises a GeSn alloy. In accordance with the semiconductor device and method for manufacturing the same of the present invention, GeSn stressed source and drain regions with high concentration of Sn is formed by implanting precursors and performing a laser rapid annealing, thus the device carrier mobility of the channel region is effectively enhanced and the device drive capability is further improved.

Abstract: A method of forming a group III nitride semiconductor comprises: preparing a group III nitride semiconductor which contains a p-type dopant or an n-type dopant; and performing a treatment of the group III nitride semiconductor by using a reducing gas and a nitrogen source gas to form a conductive group III nitride semiconductor. The treatment includes performing a first treatment of the group III nitride semiconductor by using a first treatment gas including the reducing gas and the nitrogen source gas, which are supplied to a treatment apparatus at a first flow rate and a second flow rate, respectively, and after the first treatment is performed, performing a second treatment of the group III nitride semiconductor by using a second treatment gas including the reducing gas and the nitrogen source gas, which are supplied to the treatment apparatus at a third flow rate and a fourth flow rate, respectively.

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. In an example, the method includes providing a substrate; forming a gate structure over the substrate; removing portions of the substrate to form a first recess and a second recess in the substrate, such that the gate structure interposes the first recess and the second recess; forming a nitrogen passivation layer in the substrate, such that the first recess and the second recess are defined by nitrogen passivated surfaces of the substrate; and forming doped source and drain features over the nitrogen passivated surfaces of the first recess and the second recess, the doped source and drain features filling the first and second recesses.

Abstract: A high electron mobility field effect transistor (HEMT) includes a two dimensional electron gas (2DEG) in the drift region between the gate and the drain that has a non-uniform lateral 2DEG distribution that increases in a direction in the drift region from the gate to the drain.

Abstract: In some embodiments, a metal insulator semiconductor heterostructure field effect transistor (MISHFET) is disclosed that has a source, a drain, an insulation layer, a gate dielectric, and a gate. The source and drain are on opposing sides of a channel region of a channel layer. The channel region is an upper portion of the channel layer. The channel layer comprises gallium nitride. The insulation layer is over the channel layer and has a first portion and a second portion. The first portion is nearer the drain than the source and has a first thickness. The second portion is nearer the source than drain and has the first thickness. The insulation layer has an opening through the insulation layer. The opening is between the first portion and the second portion.

Abstract: A semiconductor device includes a semiconductor body having a compound semiconductor material on a substrate. The compound semiconductor material has a channel region. A source region extends to the compound semiconductor material. A drain region also extends to the compound semiconductor material and is spaced apart from the source region by the channel region. An insulating region is buried in the semiconductor body between the compound semiconductor material and the substrate in an active region of the semiconductor device. The active region includes the source, the drain and the channel region of the device. The insulating region is discontinuous over a length of the channel region between the source region and the drain region.

Abstract: The present invention discloses a method of making nano-MOS devices having a metal gate, thereby avoiding the poly depletion effect, and enhancing the MOS device's performance. The method forms metal gates by depositing a metal film over sidewall surfaces on two sides of a polycrystalline semiconductor layer. The metal in the metal film diffuses toward the sidewall surfaces of the polycrystalline semiconductor layer and forms, after annealing, metal-semiconductor compound nanowires (i.e., metal gates) on the sidewall surfaces of the polycrystalline semiconductor layer. Thus, high-resolution lithography is not required to form metal compound semiconductor nanowires, resulting in significant cost saving. At the same time, a nano-MOS device is also disclosed, which includes a metal gate, thereby avoiding the poly depletion effect, and resulting in enhanced MOS device performance.

Abstract: An asymetric gate MOS device is disclosed. The gate is a metal gate, and the metal gate has a different work function on the source side from that on the drain side of the MOS device, so that the overall performance parameters of the MOS device are more optimized. A method of making an asymetric gate MOS device is also disclosed. In the method, dopant ions are implanted into the gate of the MOS device, so as to cause the gate to have a different work function on the source side from that on the drain side of the MOS device. As a result, the overall performance parameters of the MOS device are more optimized. The method can be easily implemented.

Abstract: A semiconductor apparatus invention includes a substrate (1), an epitaxial layer (2) formed on the substrate (1), a gate electrode (3), a source electrode (4), and a drain electrode (5) that are formed on the epitaxial layer. The source electrode (4) and the drain electrode (5) each include at least two first divided electrodes that are formed to extend in parallel to each other in a first direction, inter-electrode distances Ps and Pd between the first divided electrodes are greater than or equal to a radius of an abnormal growth portion formed on a surface of the epitaxial layer (2), and widths of the first divided electrodes are less than or equal to the radius of the abnormal growth portion.

Abstract: A first AlGaN layer formed over a substrate, a second AlGaN layer formed over the first AlGaN layer, an electron transit layer formed over the second AlGaN layer, and an electron supply layer formed over the electron transit layer are provided. A relationship of “0?x1<x2?1” is found when a composition of the first AlGaN layer is represented by Alx1Ga1-x1N, and a composition of the second AlGaN layer is represented by Alx2Ga1-x2N. Negative charges exist at an upper surface of the AlGaN layer more than positive charges existing at a lower surface of the AlGaN layer.

Abstract: A MOS transistor structure with an in-situ doped source and/or drain and a method for forming the same are provided. The method comprises steps of: providing a substrate; forming a high Ge content layer on the substrate; forming a gate stack on the high Ge content layer and forming a side wall of one or more layers on both sides of the gate stack; etching the high Ge content layer to form a source region and/or a drain region; and forming a source and/or a drain in the source region and/or the drain region respectively by a low-temperature selective epitaxy, and introducing a doping gas during the low-temperature selective epitaxy to heavily dope the source and/or the drain and to in-situ activate a doping element.

Abstract: A field effect transistor (FET) has a channel hosted in Ge. The FET has silicon-germanium (SiGe) source and drain formed by selective epitaxy. The SiGe source and drain exert a tensile stress onto the Ge channel. During forming of the SiGe source and drain, an n-type dopant species and a compensating species are being incorporated into the SiGe source and drain. The n-type dopant species and the compensating species are so selected that the size of the SiGe atomic radius is inbetween the dopant atomic radius and the compensating species atomic radius.

Abstract: Methods are provided for fabricating a FINFET integrated circuit that includes epitaxially growing a first silicon germanium layer and a second silicon layer overlying a silicon substrate. The second silicon layer is etched to form a silicon fin using the first silicon germanium layer as an etch stop. The first silicon germanium layer underlying the fin is removed to form a void underlying the fin and the void is filled with an insulating material. A gate structure is then formed overlying the fin.

Abstract: In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first recess in the substrate. A preliminary first epitaxial layer including silicon-germanium is formed in the first recess. An upper portion of the preliminary first epitaxial layer is etched to form a second recess on the preliminary first epitaxial layer. In addition, a portion of the preliminary first epitaxial layer adjacent to the second recess is etched to thereby transform the preliminary first epitaxial layer into a first epitaxial layer. A second epitaxial layer including silicon-germanium is formed in the second recess located on the first epitaxial layer.

Abstract: A method of manufacturing a tunnel field effect transistor is disclosed. The method comprises forming a two-step profile in a silicon substrate (100) using a patterned hard mask (104) covering the higher steps of said profile; forming a gate stack (114, 116) against the side wall of the higher step; forming spacers (122) on either side of the gate stack (118); and implanting a first type impurity (124) in the higher step and an opposite type impurity in the neighboring lower step (120), wherein at least the first type impurity is implanted using an angled implanting step after removing the patterned hard mask (104). In a preferred embodiment, the method further comprises forming a sacrificial spacer (108) against a side wall of a higher step and the side wall of the hard mask (104); further etching the lower step (106, 110) next to said spacer (108) and subsequently growing a further semiconductor portion (112) on said lower step and removing the spacer (108) prior to forming the gate stack.

Abstract: A method for fabricating a transistor with uniaxial stress channels includes depositing an insulating layer onto a substrate, defining bars within the insulating layer, recessing a channel into the substrate, growing a first semiconducting material in the channel, defining a gate stack over the bars and semiconducting material, defining source and drain recesses and embedding a second semiconducting material into the source and drain recesses.

Abstract: Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate.

Abstract: The likelihood of forming silicon germanium abnormal growths, which can be undesirably formed on the gate electrode of a strained-channel PMOS transistor at the same time that silicon germanium source and drain regions are formed, is substantially reduced by using protection materials that reduce the likelihood that the gate electrode is exposed during the formation of the silicon germanium source and drain regions.

Abstract: An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.

Abstract: According to an aspect of the invention, a method is provided for manufacturing electronic components. A conducting element comprising a first portion, a second portion and a third portion between the first portion and the second portion is provided. Thermally responsive dielectric material is added at least onto the third portion of the conducting element. Electric current is supplied between the first portion and the second portion of the conducting element causing ohmic heating to affix dielectric material located on the third portion to the third portion. Non-thermally-affixed dielectric material is removed.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode.

Abstract: semiconductor device comprises a semiconductor substrate; a channel layer of at least a first III-V semiconductor compound above the semiconductor substrate; a gate stack structure above a first portion of the channel layer; a source region and a drain region comprising at least a second III-V semiconductor compound above a second portion of the channel layer; and a first metal contact structure above the S/D regions comprising a first metallic contact layer contacting the S/D regions. The first metallic contact layer comprises at least one metal-III-V semiconductor compound.

Abstract: A method for producing a SiGe stressor with high Ge concentration is provided. The method includes providing a semiconductor substrate with a source area, a drain area, and a channel in between; depositing the first SiGe film layer on the source area and/or the drain area; performing a low temperature thermal oxidation, e.g., a high water vapor pressure wet oxidation, to form an oxide layer at the top of the first SiGe layer and to form the second SiGe film layer with high Ge percentage at the bottom of the first SiGe film layer without Ge diffusion into the semiconductor substrate; performing a thermal diffusion to form the SiGe stressor from the second SiGe film layer, wherein the SiGe stressor provides uniaxial compressive strain on the channel; and removing the oxide layer. A Si cap layer can be deposited on the first SiGe film layer prior to performing oxidation.

Abstract: A semiconductor device is fabricated by providing a substrate including a silicon channel layer and a silicon-germanium channel layer, forming gate structures disposed on the silicon channel layer and on the silicon-germanium channel layer, forming a first protection layer to cover the resultant structure including the gate structures, and injecting hydrogen and/or its isotopes into the silicon-germanium channel layer. The silicon and silicon-germanium channel layers may be oriented along a <100> direction. Related devices are also described.

Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a channel region under the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the channel region, wherein at least one of the source and drain regions comprises a set of dislocations that are adjacent to the channel region and arranged in the direction perpendicular to a top surface of the semiconductor substrate, and the set of dislocations comprises at least two dislocations.

Abstract: Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes but not electrons.

Abstract: Graphene or carbon nanotube-based transistor devices and techniques for the fabrication thereof are provided. In one aspect, a transistor is provided. The transistor includes a substrate; a carbon-based material on the substrate, wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor; a patterned organic buffer layer over the portion of the carbon-based material that serves as the channel region of the transistor; a conformal high-k gate dielectric layer disposed selectively on the patterned organic buffer layer; metal source and drain contacts formed on the portions of the carbon-based material that serve as the source and drain regions of the transistor; and a metal top-gate contact formed on the high-k gate dielectric layer.

Abstract: Various embodiments provide an MOS transistor, a formation method thereof, and an SRAM memory cell circuit. An exemplary MOS transistor can include a channel region including an asymmetric stressing layer having a stress gradually varied from a compressive stress to a tensile stress or from a tensile stress to a compressive stress from a first end of the channel region adjacent to a source region to a second end of the channel region adjacent to a drain region. The MOS transistor can be used as a transfer transistor in an SRAM memory cell circuit to increase a source-drain saturation current in a write operation and to reduce a source-drain saturation current in a read operation. Read and write margins of the SRAM can be increased.

Abstract: A first layer of a first conductivity type made of silicon carbide is formed. A second layer of a second conductivity type different from the first conductivity type positioned on the first layer, and a third layer of the first conductivity type positioned on the second layer are formed. The step of forming second and third layers includes the steps of performing impurity ion implantation, and performing heat treatment for activating impurities implanted by the impurity ion implantation. After the step of performing heat treatment, a trench having a side wall penetrating the third layer and the second layer and having a bottom reaching the first layer is formed. A gate insulating film to cover the side wall of the trench is formed. As a result, a silicon carbide semiconductor device having a low ON resistance is provided.

Abstract: CMOS devices are fabricated with a channel layer having minimized dopant fluctuation and diffusion. Embodiments include forming a dummy gate, on a substrate, between a pair of spacers, forming, in the substrate, a source and drain separated by a ground plane layer, removing the dummy gate from the substrate, forming a cavity between the pair of spacers, forming, after removal of the dummy gate, a channel layer on the substrate, forming a high-k layer on the channel layer and on side surfaces of the cavity, and forming a replacement gate in the cavity.

Abstract: A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.

Abstract: A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.

Abstract: A device includes providing a silicon substrate; annealing the silicon substrate at a first temperature higher than about 900° C.; and lowering a temperature of the silicon substrate from the first temperature to a second temperature. A temperature lowering rate during the step of lowering the temperature is greater than about 1° C./second. A III-V compound semiconductor region is epitaxially grown on a surface of the silicon substrate using metal organic chemical vapor deposition (MOCVD).

Abstract: In sophisticated transistor elements, long-term threshold voltage shifts in transistors comprising a threshold adjusting semiconductor alloy may be reduced by reducing the roughness of an interface formed between the threshold adjusting semiconductor material and the gate dielectric material. To this end, a portion of the threshold adjusting semiconductor material may be oxidized and may be removed prior to forming the high-k dielectric material.

Abstract: A MOS transistor process includes the following steps. A gate structure is formed on a substrate. A source/drain is formed in the substrate beside the gate structure. After the source/drain is formed, (1) at least a recess is formed in the substrate beside the gate structure. An epitaxial structure is formed in the recess. (2) A cleaning process may be performed to clean the surface of the substrate beside the gate structure. An epitaxial structure is formed in the substrate beside the gate structure.

Abstract: The field effect device comprises a sacrificial gate electrode having side walls covered by lateral spacers formed on a semiconductor material film. The source/drain electrodes are formed in the semiconductor material film and are arranged on each side of the gate electrode. A diffusion barrier element is implanted through the void left by the sacrificial gate so as to form a modified diffusion area underneath the lateral spacers. The modified diffusion area is an area where the mobility of the doping impurities is reduced compared with the source/drain electrodes.

Abstract: A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.

Abstract: A semiconductor device includes a nitride semiconductor stacked structure including a carrier transit layer and a carrier supply layer; a p-type nitride semiconductor layer provided over the nitride semiconductor stacked structure and including an active region and an inactive region; an n-type nitride semiconductor layer provided on the inactive region in the p-type nitride semiconductor layer; and a gate electrode provided over the active region in the p-type nitride semiconductor layer.

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device may include a buffer layer disposed on a substrate, the buffer layer including gallium (Ga) and nitrogen (N), a barrier layer disposed on the buffer layer, the barrier layer including aluminum (Al) and nitrogen (N), wherein the barrier layer includes an oxidized portion of the barrier layer, a gate dielectric disposed on the oxidized portion of the barrier layer, and a gate electrode disposed on the gate dielectric, wherein the oxidized portion of the barrier layer is disposed in a gate region between the gate electrode and the buffer layer.

Abstract: A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.

Abstract: A method for manufacturing a heterojunction field effect transistor 1 comprises the steps of: epitaxially growing a drift layer 20a on a support substrate 10; epitaxially growing a current blocking layer 20b which is a p-type semiconductor layer on the drift layer 20a at a temperature equal to or higher than 1000° C. by using hydrogen gas as a carrier gas; and epitaxially growing a contact layer 20c on the current blocking layer 20b by using at least one gas selected from the group consisting of nitrogen gas, argon gas, helium gas, and neon gas as a carrier gas.

Abstract: Provided are a nitride semiconductor device having an excellent boundary between a nitride semiconductor and a gate insulating film, resulting in improved device characteristics, and a manufacturing method therefor.

Abstract: A semiconductor device comprises a substrate; a shallow trench isolation embedded in the substrate and forms at least one opening region; a channel region located in the opening region; a gate stack including a gate dielectric layer and a gate electrode layer, located above said channel region; a source/drain region located on both sides of the channel region, including a stress layer which provides strain for the channel region. A liner layer is provided between the shallow trench isolation and the stress layer, which serves as a crystal seed layer of the stress layer. A liner layer and a pad oxide layer are provided between the substrate and the shallow trench isolation. The liner layer is inserted between the STI and the stress layer of the source/drain region as a crystal seed layer or nucleating layer for epitaxial growth, thereby eliminating the STI edge effect during the source/drain strain engineering.