Abstract: A method of manufacturing a heterojunction BiCMOS IC. (100) includes forming a gate electrode (121, 131), forming a protective layer (901, 902) over the gate electrode, forming a semiconductor layer (1101) over the protective layer, depositing an electrically insulative layer (1102, 1103) over the semiconductor layer, using a mask layer (1104) to define a doped region (225) in the semiconductor layer and to define a hole (1201) in the electrically insulative layer, forming an electrically conductive layer (1301) over the electrically insulative layer, using another mask layer (1302) to define an emitter region (240) in the electrically conductive layer and to define an intrinsic base region (231) and a portion of an extrinsic base region (232) in the electrically conductive layer, and using yet another mask layer (1502) to define another portion of the extrinsic base region in the electrically conductive layer.

Abstract: Disclosed is a method for manufacturing a hetero junction bipolar transistor capable of forming a ledge by using a low-priced contact aligner and in a selective wet etching manner, without having any expensive stepper and dry etching and forming a ballasting resistor, without having an additional NiCr thin film, whereby the manufacturing processes thereof can be embodied in simple and easy manners, thereby improving productivity and an economical efficiency.

Abstract: A method of manufacturing a hetero-junction bipolar transistor including a carbon-doped base layer includes the steps of (a) growing a base layer on an underlying layer through chemical vapor deposition, (b) forming at least one semiconductor layer over the base layer, and (c) then subjecting the base layer to thermal annealing at a temperature of 520° C. to 650° C.

Abstract: In one disclosed embodiment, a collector is deposited and a base is grown on the collector, for example, by epitaxially depositing either silicon or silicon-germanium. An emitter is fabricated on the base followed by implant doping an extrinsic base region. For example, the extrinsic base region can be implant doped using boron. The extrinsic base region doping diffuses out during subsequent thermal processing steps in chip fabrication, creating an out diffusion region in the device, which can adversely affect various operating characteristics, such as parasitic capacitance and linearity. The out diffusion is controlled by counter doping the out diffusion region. For example, the counter doped region can be implant doped using arsenic or phosphorous. Also, for example, the counter doped region can be formed using tilt implanting or, alternatively, by implant doping the counter doped region and forming a spacer on the base prior to implanting the extrinsic base region.

Abstract: A semiconductor component of the heterojunction bipolar transistor type comprises, on a substrate, a collector, a base and a mesa-shaped emitter resting on the base. The bipolar transistor furthermore comprises electrically insulating elements in contact with the base and the flanks of the emitter mesa, said elements having a width of the same magnitude as the width of the mesa and providing the component with greater stability. Furthermore, a method for the manufacture of a component of this kind comprises in particular a step for the ion implantation of insulating ions through the constituent layer of the emitter mesa so as to define the electrically insulating elements.

Abstract: A solid imaging device including: a semiconductor substrate of a first conductivity types a layer of a second conductivity type formed on a surface of the semiconductor substrate, the layer at least including a photosensitive portion of the second conductivity type; and a MOS transistor of the second conductivity type coupled to the photosensitive portion, wherein the solid imaging device further includes a layer of the first conductivity type in at least a channel region of the MOS transistor of the second conductivity type, the layer of the first conductivity type having an impurity concentration which is higher than an impurity concentration of the semiconductor substrate, and wherein at least a portion of a boundary of the layer of the second conductivity type is in direct contact with the semiconductor substrate.

Abstract: According to a disclosed embodiment, a base region is grown on a transistor region. A dielectric layer is next deposited over the base region. The dielectric layer can comprise, for example, silicon dioxide, silicon nitride, or a suitable low-k dielectric. Subsequently, an opening is fabricated in the dielectric layer, and an emitter layer is formed on top of the dielectric layer and in the opening. Thereafter, an anisotropic polymerizing etch chemistry is utilized to etch the emitter layer down to a first depth, forming an emitter region in the opening. Next, a non-polymerizing etch chemistry having isotropic components is used to create a notch in the dielectric layer below the emitter region. The formation of the notch reduces the overlap area of a capacitor that forms between the emitter region and the base region, which translates to a lower level of emitter to base capacitance.

Abstract: According to a disclosed embodiment, the surface of a semiconductor wafer is covered by an etch stop layer. For example, the etch stop layer can be composed of silicon dioxide. A cap layer is then fabricated over the etch stop layer. For example, the cap layer can be a polycrystalline silicon layer fabricated over the etch stop layer. The cap layer is then selectively etched down to the etch stop layer creating an opening in the cap layer according to a pattern. The pattern can be formed, for example, by covering the cap layer with photoresist and selective etching. Selective etching can be accomplished by using a dry etch process which etches the cap layer without substantially etching the etch stop layer. The etch stop layer is then removed using, for example, a hydrogen-fluoride cleaning process. A semiconductor crystal is then grown by epitaxial deposition in the opening. For example, the semiconductor crystal can be silicon-germanium. Moreover, a single crystal semiconductor structure of high quality, i.

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

Abstract: A SiGe bipolar transistor including a semiconductor substrate having a collector and sub-collector region formed therein, wherein the collector and sub-collector are formed between isolation regions that are also present in the substrate is provided. Each isolation region includes a recessed surface and a non-recessed surface which are formed utilizing lithography and etching. A SiGe layer is formed on the substrate as well as the recessed non-recessed surfaces of each isolation region, the SiGe layer includes polycrystalline Si regions and a SiGe base region. A patterned insulator layer is formed on the SiGe base region; and an emitter is formed on the patterned insulator layer and in contact with the SiGe base region through an emitter window opening.

Abstract: A heterojunction bipolar transistor includes an emitter or collector region of doped silicon, a base region including silicon-germanium, and a spacer. The emitter or collector region form a heterojunction with the base region. The spacer is positioned to electrically insulate the emitter or collector region from an external region. The spacer includes a silicon dioxide layer physically interposed between the emitter or collector region and the remainder of the spacer.

Abstract: A method of fabricating a MOSEFT device, which is suitable for fabricating an III-V group semiconductor device. A substrate comprises a buffer layer and a channel layer, wherein silicon oxide is formed on the channel layer by a liquid phase deposition method (LPD) to control the parameters of growth solution. A silicon oxide insulating layer that is formed on the channel layer has a thickness of approximately 40 Å, wherein the silicon oxide insulating layer is used as a gate oxide layer. A source, a drain and a gate are formed on the gate oxide layer. The LPD process is performed in a temperature range from room temperature to 60° C. Thus, the low temperature of the LPD technique will not lead to a negative heat effect on other fabrications or on the wafer, therefore the low temperature will not cause thermal stress, dopant redistribution, dopant diffusion or material interaction, for example.

Abstract: In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for example, a base contact in a heterojunction bipolar transistor while the single crystal silicon-germanium region can be, for example, a base in the heterojunction bipolar transistor. The polycrystalline silicon-germanium region can be grown in a mass controlled mode at a certain temperature and a certain pressure of the precursor gas while the single crystal silicon-germanium region can be grown, concurrently, in a kinetically controlled mode at the same temperature and the same pressure of the precursor gas. The disclosed embodiments result in controlling the growth of the polycrystalline silicon-germanium independent of the growth of the single crystal silicon-germanium.

Abstract: The semiconductor device comprises a collector layer 14; a base layer 16 of a carbon-doped GaxIn1−xAsySb1−y layer having one surface connected to the collector layer 14; an emitter layer 18 connected the other surface of the base layer 16; a base contact layer 30 of a carbon-doped GaAsSb layer electrically connected to the base layer 16; and a base electrode 32 formed on the base contact layer 30. The semiconductor device of such structure can have a much reduced base resistance RB, whereby InP/GaInAsSb-based HBTs including InP/InGaAs-based HBTs can have higher maximum oscillation frequency fmax. Because of the carbon-doped semiconductor layer the semiconductor device can have higher reliability.

Abstract: A low resistance bipolar transistor extrinsic base and method of manufacture. A layer of heavily doped polysilicon is deposited over an oxide layer on an npn silicon substrate and a window is formed through to an n doped region of the substrate. Epitaxial SiGe is grown on the polysilicon layer and within the window. Dopant from the polysilicon layer diffuses into the SiGe layer thereby lowering its resistance.

Abstract: A process for forming a silicon-germanium base of a heterojunction bipolar transistor. First, a silicon substrate having a mesa surrounded by a trench is formed. Next, a silicon-germanium layer is deposited on the substrate and the portion of the silicon-germanium layer adjacent the mesa is removed to form the silicon-germanium base. In a second embodiment, the process comprises the steps of forming a silicon substrate having a mesa surrounded by a trench, forming a dielectric layer in the trench adjacent the mesa, and growing a silicon-germanium layer on the mesa top surface using selective epitaxial growth to form the silicon-germanium base.

Abstract: A microelectronic device having a self aligned metal diffusion barrier is disclosed. A microelectronic device having a substrate and a dielectric layer on the substrate. A trench having inside walls is formed through the dielectric layer. A lining of a barrier metal is on the inside walls of the trench and a fill metal is in the trench between the linings on the inside walls of the trench. The fill metal and the barrier metal have substantially different removal selectivities. A covering of the barrier metal is on the fill metal and the covering spans the linings on the inside walls of the trench and conforms to the top of the fill metal in the trench.

Abstract: Disclosed are a method for manufacturing a homojunction or heterojunction bipolar device and a structure of the bipolar device manufactured by the method.

Abstract: Devices and methods for fabricating wholly silicon carbide heterojunction bipolar transistors (HBTs) using germanium base doping to produce suitable emitter/base heterojunctions. In one variation, all device layers are are grown epitaxially and the heterojunction is created by introducing a pseudoalloying material, such as germanium, to form a graded implant. In other variations, the device epitaxial layers are 1) grown directly onto a semi-insulating substrate, 2) the semi-insulating epitaxial layer is grown onto a conducting substrate; 3) the subcollector is grown on a lightly doped p-type epitaxial layer grown on a conducting substrate; and 4) the subcollector is grown directly on a conducting substrate. Another variation comprises a multi-finger HBT with bridging conductor connections among emitter fingers. Yet another variation includes growth of layers using dopants other than nitrogent or aluminum.

Abstract: A method of manufacturing a semiconductor device comprising heterojunction bipolar transistors (HBTs), in which method a first semiconductor layer of monocrystalline silicon (5), a second semiconductor layer of monocrystalline silicon comprising 5 to 25 at. % germanium (6) and a third semiconductor layer of monocrystalline silicon (7) are successively provided on a surface (2) of a silicon wafer (1) by means of epitaxial deposition. Base zones of the transistors are formed in the second semiconductor layer. In this method, the second semiconductor layer is deposited without a base doping, said doping being formed at a later stage. Said doping can be formed by means of an ion implantation process or a VPD (Vapor Phase Doping) process. This method enables integrated circuits comprising npn-transistors as well as pnp-transistors to be manufactured.

Abstract: Devices and methods for fabricating wholly silicon carbide heterojunction bipolar transistors (HBTs) using germanium base doping to produce suitable emitter/base heterojunctions. In one variation, all device layers are are grown epitaxially and the heterojunction is created by introducing a pseudoalloying material, such as germanium, to form a graded implant. In other variations, the device epitaxial layers are 1) grown directly onto a semi-insulating substrate, 2) the semi-insulating epitaxial layer is grown onto a conducting substrate; 3) the subcollector is grown on a lightly doped p-type epitaxial layer grown on a conducting substrate; and 4) the subcollector is grown directly on a conducting substrate. Another variation comprises a multi-finger HBT with bridging conductor connections among emitter fingers. Yet another variation includes growth of layers using dopants other than nitrogent or aluminum.

Abstract: A method of fabricating an HBT transistor with extremely high speed and low operating current. The transistor has a small base area and a small emitter area with most of the emitter area contacted with metal, most of the base area, outside of the emitter, contacted with metal and a collector ohmic metal placed close to the device emitter and the base ohmic metal. To achieve this, the method includes partially undercutting the base ohmic metal along all external edges to reduce the device's parasitic base-collector capacitance. In order to provide metal step coverage, the undercut of the base ohmic metal can be covered with a sloped edge polymer. In addition, a Schottky diode can be fabricated within the process steps used to form the HBT transistor without additional process steps being needed to build the Schottky diode.

Abstract: A bipolar transistor device with a large current capacity is formed by connecting a plurality of transistor elements to each other in parallel, each transistor element having a collector layer, a base layer, and an emitter layer formed respectively in a semiconductor substrate. In the bipolar transistor device, the base layers of a plurality of the transistor elements are extended in parallel to each other and those base layers are separated from each other. In each separated base layer, a first base electrode is formed on a part of the base layer which is separated from an emitter junction with the emitter layer, and a second base electrode is formed on another portion of the base layer closer to the emitter junction than the first base electrode. To dispose the base electrodes of a plurality of the transistor elements in parallel to each other, a base wiring is connected to the first base electrodes of those elements electrically.

Abstract: Subcollector layers or emitter layers constituting a bipolar transistor having different thicknesses form a two-layered structure. A resistor layer is formed at the same as one of the subcollector layers or one of the emitter layers, from the same material as that of the subcollector layer or emitter layer. A resistor is formed by the resistor layer made of the same material as that of the subcollector layer or emitter layer. A resistor with a desired resistance can be integrally built into a semiconductor device without adversely affecting the characteristics of a bipolar transistor.

Abstract: A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentially laminated on the substrate in this order. First, the wafer is etched up to a preselected depth of the collector layer via a first photoresist, which is formed at a preselected position on the emitter layer, serving as a mask. Subsequently, the collector layer etched with at least the sidewalls of the base layer and collector layer, which are exposed by the first etching step, and a second photoresist covering part of the surface of the collector layer contiguous with the sidewalls serving as a mask.

Abstract: High electron mobility transistors (HEMTs) and methods of fabricating HEMTs are provided Devices according to embodiments of the present invention include a gallium nitride (GaN) channel layer and an aluminum gallium nitride (AlGaN) barrier layer on the channel layer. A first ohmic contact is provided on the barrier layer to provide a source electrode and a second ohmic contact is also provided on the barrier layer and is spaced apart from the source electrode to provide a drain electrode. A GaN-based cap segment is provided on the barrier layer between the source electrode and the drain electrode. The GaN-based cap segment has a first sidewall adjacent and spaced apart from the source electrode and may have a second sidewall adjacent and spaced apart from the drain electrode. A non-ohmic contact is provided on the GaN-based cap segment to provide a gate contact. The gate contact has a first sidewall which is substantially aligned with the first sidewall of the GaN-based cap segment.

Abstract: A microelectronic device having a self aligned metal diffusion barrier is disclosed. A microelectronic device having a substrate and a dielectric layer on the substrate. A trench having inside walls is formed through the dielectric layer. A lining of a barrier metal is on the inside walls of the trench and a fill metal is in the trench between the linings on the inside walls of the trench. The fill metal and the barrier metal have substantially different removal selectivities. A covering of the barrier metal is on the fill metal and the covering spans the linings on the inside walls of the trench and conforms to the top of the fill metal in the trench.

Abstract: A heterojunction bipolar transistor and its fabrication method is disclosed. The heterojunction bipolar transistor includes a substrate; a collector layer formed to have a ledge or MESA on the substrate; a collector electrode formed on the collector layer surrounding the ledge; a base layer formed on the ledge of the collector layer; an ohmic cap layer on the emitter layer; an emitter layer formed in the center of the base layer; an emitter electrode formed on the ohmic cap layer; a base electrode formed on the base layer surrounding the emitter electrode; an insulating layer formed to cover the base electrode and to overlay on the insulating layer; a metal wire formed to cover the emitter electrode; and an air bridge brought in contact with the metal wire and electrically connected to an external pad lying on an ion-implanted isolation region.

Abstract: A method of producing a bipolar transistor includes the step of providing a sacrificial mesa over a layer of SiGe in order to prevent a polysilicon covering layer from forming over a predetermined region of the SiGe layer forming the transistor base. After an etching process removes the sacrificial mesa and the SiGe layer is exposed, an oppositely doped material is applied over top of the SiGe layer to form an emitter. This makes it possible to realize a thin layer of silicon germanium to serve as the transistor base. This method prevents the base layer SiGe from being affected, as it otherwise would be using a conventional double-poly process.

Abstract: In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for example, a base contact in a heterojunction bipolar transistor while the single crystal silicon-germanium region can be, for example, a base in the heterojunction bipolar transistor. The polycrystalline silicon-germanium region can be grown in a mass controlled mode at a certain temperature and a certain pressure of the precursor gas while the single crystal silicon-germanium region can be grown, concurrently, in a kinetically controlled mode at the same temperature and the same pressure of the precursor gas. The disclosed embodiments result in controlling the growth of the polycrystalline silicon-germanium independent of the growth of the single crystal silicon-germanium.

Abstract: A bipolar transistor device with a large current capacity is formed by connecting a plurality of transistor elements to each other in parallel, each transistor element having a collector layer, a base layer, and an emitter layer formed respectively in a semiconductor substrate. In the bipolar transistor device, the base layers of a plurality of the transistor elements are extended in parallel to each other and those base layers are separated from each other. In each separated base layer, a first base electrode is formed on a part of the base layer which is separated from an emitter junction with the emitter layer, and a second base electrode is formed on another portion of the base layer closer to the emitter junction than the first base electrode. To dispose the base electrodes of a plurality of the transistor elements in parallel to each other, a base wiring is connected to the first base electrodes of those elements electrically.

Abstract: A method of manufacturing a semiconductor component and the component thereof includes forming a dielectric layer (620) over a portion of a passivation ledge (640) in an emitter layer (280) and overlapping a base contact (660) onto the dielectric layer (620).

Abstract: The semiconductor region of an intrinsic collector is surrounded with a lateral insulating region. A semi-conducting layer comprising a SiGe heterojunction is partially located between the transmitter and the intrinsic collector and extends on either side of the transmitter above the lateral insulating region. The base intrinsic region is formed in said semi-conducting layer with heterojunction between the transmitter and the intrinsic collector. The base extrinsic region and the collector extrinsic region respectively comprise first zones formed in said semi-conducting layer with heterojunction, located respectively on either side of the transmitter and above the lateral insulating region first part and mutually electrically insulated by the lateral insulating region second part.

Abstract: The invention relates to semiconductor devices having a bipolar transistor to form an isolation area within a base electrode contact area to ensure stable contact of the base electrode. The bipolar transistor formed in the transistor area is in the form of an island and is rectangular when view from above. The isolation area is formed of a dielectric material around the transistor area, and the base area is formed around the emitter area which forms the central area of the transistor area. A contact groove is formed at the inner interface of the isolation groove which faces the outer surface of the transistor area, and a part of the base electrode is buried in the contact groove and faces at least one of the upper surface of the transistor area and an inner surface of the contact groove.

Abstract: The performance of a heterojunction bipolar transistor (HBT) operating at high power is limited by the power that can be dissipated by the device. This, in turn, is limited by the thermal resistance of the device to heat dissipation. In a typical HBT, and especially InP-based HBTs, heat generated during operation is concentrated near the collector-base junction. In order to more efficiently dissipate heat downward through the device to the substrate, both the collector and the sub-collector are formed of InP, which has a substantially lower thermal resistance than other typically used semiconductor materials.

Abstract: Disclosed is a method for fabricating a self-aligned submicron gate electrode using an anisotropic etching process. The method involves the steps of laminating a dummy emitter defining a dummy emitter region over a heterojunction bipolar transistor structure including layers sequentially formed over a semiconductor substrate to define a base region, an emitter region, and an emitter cap region, respectively, defining a line having a width of about 1 micron on the dummy emitter by use of a photoresist while using a contact aligner, selectively anisotropic etching the dummy emitter at a region where the line is defined, to allow the dummy emitter to have an etched portion having a bottom surface with a width less than the width of the line defined by the photoresist, and depositing a contact metal on the etched portion of the dummy emitter, thereby forming a gate.

Abstract: A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.

Abstract: A method of manufacturing a semiconductor component and the component thereof includes forming a dielectric layer (620) over a portion of a passivation ledge (640) in an emitter layer (280) and overlapping a base contact (660) onto the dielectric layer (620).

Abstract: In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for example, a base contact in a heterojunction bipolar transistor while the single crystal silicon-germanium region can be, for example, a base in the heterojunction bipolar transistor. The polycrystalline silicon-germanium region can be grown in a mass controlled mode at a certain temperature and a certain pressure of the precursor gas while the single crystal silicon-germanium region can be grown, concurrently, in a kinetically controlled mode at the same temperature and the same pressure of the precursor gas. The disclosed embodiments result in controlling the growth of the polycrystalline silicon-germanium independent of the growth of the single crystal silicon-germanium.

Abstract: A solid state electronic device (40) comprising a substrate (30) and layers (32 and 34) is fabricated to control the formation of crystalline defects to control at least one characteristic of the device, such as current gain beta. The formation of crystalline defects preferably is controlled by controlling the temperature of the substrate, layers or both.

Abstract: A method for producing a heterobipolar transistor, arranged on a substrate of semiconductor material on which is grown a semiconductor sequence for a collector, a base and an emitter, which method includes: etching the layer sequence to form a transistor with a mesa structure, carrying out a first planarizing step to the upper limit of the base during which the surface of the base is protected by a protecting portion of the emitter layer adjacent to the base; removing this protective layer; depositing a metal contact layer for the base; carrying out a second planarizing step for the base emitter mesa; and finally depositing a connecting metallization layer for the collector, base and emitter.

Abstract: A semiconductor component of the heterojunction bipolar transistor type comprises, on a substrate, a collector, a base and a mesa-shaped emitter resting on the base. The bipolar transistor furthermore comprises electrically insulating elements in contact with the base and the flanks of the emitter mesa, said elements having a width of the same magnitude as the width of the mesa and providing the component with greater stability. Furthermore, a method for the manufacture of a component of this kind comprises in particular a step for the ion implantation of insulating ions through the constituent layer of the emitter mesa so as to define the electrically insulating elements.

Abstract: A semiconductor device comprises an n-conductive type Si substrate, a n-conductive type Si film formed on the n-conductive type Si substrate, a p-conductive type SiGe film formed on the n-conductive type Si film, a p-conductive type Si film formed on the p-conductive type SiGe film, a n-conductive type Si film formed on the p-conductive type Si film, a base electrode formed by removing a part of the n-conductive type Si film or changing the conductive type of a part of the n-conductive type Si film to a p-conductive type, and joining a metal terminal to a part of the p-conductive type Si film exposed by removing the N-type Si film or to the part of the n-conductive type Si film whose conductive type is changed to a p-conductive type, an emitter electrode formed by joining a metal terminal to the n-conductive type Si film, and a collector electrode formed by joining a metal terminal to a back surface of the n-conductive type Si substrate.

Abstract: Extremely high dopant concentrations are uniformly introduced into a semiconductor material by laser annealing aided by an anti-reflective coating (ARC). A spin-on-glass (SOG) film containing dopant is formed on top of the semiconductor material. An ARC is then formed over the doped SOG layer. Application of radiation from an excimer laser to the ARC heats and melts the doped SOG film and the underlying semiconductor material. During this melting process, dopant from the SOG film diffuses uniformly within the semiconductor material. Upon removal of the laser radiation, the semiconductor material cools and crystallizes, evenly incorporating the diffused dopant within its lattice structure. The ARC suppresses reflection of the laser by the doped material, promoting efficient transfer of energy from the laser to heat and melt the underlying doped layer and semiconductor material.

Abstract: A heterobipolar transistor includes a base layer formed of a SiGeC ternary mixed crystal having a C concentration profile such that a C concentration in the base layer increases from a first interface facing an emitter layer to a second interface facing a collector layer. Further, the process of forming such a SiGeC ternary mixed crystal layer is disclosed.

Abstract: A method of producing a bipolar transistor includes the step of providing a sacrificial mesa over a layer of SiGe in order to prevent a polysilicon covering layer from forming over a predetermined region of the SiGe layer forming the transistor base. After an etching process removes the sacrificial mesa and the SiGe layer is exposed, an oppositely doped material is applied over top of the SiGe layer to form an emitter. This makes it possible to realize a thin layer of silicon germanium to serve as the transistor base. This method prevents the base layer SiGe from being affected, as it otherwise would be using a conventional double-poly process.

Abstract: Process for the formation of epitaxial layers with controlled n-type dopant concentration depth profiles for use in NPN bipolar transistors. The process includes first providing a semiconductor substrate (e.g. a [100]-oriented silicon wafer substrate) with an n-type collector precursor region formed on its surface, followed by forming an n-type (e.g. phosphorous or arsenic) in-situ doped epitaxial layer of a thickness t1 on the n-type collector precursor region. Next, an undoped epitaxial layer of a thickness t2 is formed on the n-type in-situ doped epitaxial layer. A p-type (e.g. boron) in-situ doped epitaxial base layer is subsequently formed on the undoped epitaxial layer. The process can also include the sequential formation of an undoped Si1−xGex epitaxial layer and a p-type in-situ doped Si1−xGex epitaxial layer between the undoped epitaxial layer and the p-type in-situ doped epitaxial base layer.

Abstract: A semiconductor integrated circuit device comprises an active device and a resistance element formed monolithically on a common substrate wherein the resistance element includes a dummy pattern having a layered structure identical with a layered structure of the active device, and first and second electrodes are provided inside a mesa structure provided for the resistance element with a separation from a sidewall of the mesa structure, the first and second electrodes being formed in correspondence to openings formed in the dummy pattern.

Abstract: A heterobipolar transistor HBT and a laser diode LD are manufactured from a common epitaxial structure having a plurality of semiconducting layers. The transistor can be manufactured directly from the material as it is after finishing the epitaxial steps. For manufacturing the laser diode the structure is changed by diffusing zinc into the material, so that the topmost material layers change their dopant type from n-type to p-type. This is made on selected areas of a wafer, so that transistors and laser diodes thereby can be monolithically integrated. The active region of the laser is located in the collector of the transistor, which gives a freedom in designing the components and results in that an individual optimization of the two components can be made. The laser and the HBT can thus be given substantially the same structures, as if they had been individually optimized. The laser will for example be the type vertical injection and can therefor get the same performance as discrete lasers.

Abstract: In a hetero-junction bipolar transistor, an undoped Al0.7Ga0.3As stopper layer 5 having good etching controllability is provided on a base layer 4, thereby forming a base without etching damage, this resulting in achievement of the desired base resistance with good repeatability.