Including Diode Patents (Class 438/328)
  • Patent number: 10923570
    Abstract: A semiconductor device comprises: an n-type semiconductor substrate; a p-type anode region formed in the semiconductor substrate on its front surface side; an n-type field stop region formed in the semiconductor substrate on its rear surface side with protons as a donor; and an n-type cathode region formed in the semiconductor substrate to be closer to its rear surface than the field stop region is, wherein a concentration distribution of the donor in the field stop region in its depth direction has a first peak, and a second peak that is closer to the rear surface of the semiconductor substrate than the first peak is, and has a concentration lower than that of the first peak, and a carrier lifetime in at least a partial region between the anode region and the cathode region is longer than carrier lifetimes in the anode region.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: February 16, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroki Wakimoto, Hiroshi Takishita, Takashi Yoshimura, Takahiro Tamura, Yuichi Onozawa
  • Patent number: 9224729
    Abstract: A semiconductor device includes: a first well provided in a semiconductor substrate; a second well provided in the semiconductor substrate, so as to be isolated from the first well; a Schottky barrier diode formed in the first well; and a PN junction diode formed in the second well, with an impurity concentration of the PN junction thereof set higher than an impurity concentration of the Schottky junction of the Schottky barrier diode, and being connected antiparallel with the Schottky barrier diode.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: December 29, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Dai Kanai, Taiji Ema, Kazushi Fujita
  • Patent number: 9202886
    Abstract: A Schottky diode includes a deep well formed in a substrate, an isolation layer formed in the substrate, a first conductive type guard ring formed in the deep well along an outer sidewall of the isolation layer and located at a left side of the isolation layer, a second conductive type well formed in the deep well along the outer sidewall of the isolation layer and located at a right side of the isolation layer, an anode electrode formed over the substrate and coupled to the deep well and the guard ring, and a cathode electrode formed over the substrate and coupled to the well. A part of the guard ring overlaps the isolation layer.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: December 1, 2015
    Assignee: MAGNACHIP SEMICONDUCTOR, LTD.
    Inventor: Jin-Yeong Son
  • Patent number: 9123608
    Abstract: A backside illuminated CMOS image sensor comprises a photo active region formed over a substrate using a front side ion implantation process and an extended photo active region formed adjacent to the photo active region, wherein the extended photo active region is formed by using a backside ion implantation process. The backside illuminated CMOS image sensor may further comprise a laser annealed layer on the backside of the substrate. The extended photo active region helps to increase the number of photons converted into electrons so as to improve quantum efficiency.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Volume Chien, Szu-An Wu
  • Patent number: 9111750
    Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon carbide (SiC), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: August 18, 2015
    Assignee: General Electric Company
    Inventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, Rui Zhou
  • Patent number: 9105567
    Abstract: An integrated circuit structure includes a semiconductor doped area (NWell) having a first conductivity type, and a layer (PSD) that overlies a portion of said doped area (NWell) and has a doping of an opposite second type of conductivity that is opposite from the first conductivity type of said doped area (NWell), and said layer (PSD) having a corner in cross-section, and the doping of said doped area (NWell) forming a junction beneath said layer (PSD) with the doping of said doped area (NWell) diluted in a vicinity below the corner of said layer (PSD). Other integrated circuits, substructures, devices, processes of manufacturing, and processes of testing are also disclosed.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: August 11, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Ming-Yeh Chuang
  • Patent number: 9059705
    Abstract: A non-volatile field programmable gate array includes a logic component, a transistor device comprising a gate structure, a first impurity region, and a second impurity region, the first impurity region coupled to the reconfigurable logic component, and a resistive switching device comprising a bottom electrode coupled to the first impurity region, a top electrode spatially extending in a first direction, and a resistive switching element coupled to the top electrode and to the bottom electrode at an intersecting region between the bottom electrode and the top electrode, wherein the resistive switching device stores a resistance state from a plurality of resistance states that indicates a configuration code for the reconfigurable logic component.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: June 16, 2015
    Assignee: CROSSBAR, INC.
    Inventor: Frank Edelhaeuser
  • Patent number: 9018068
    Abstract: A nonvolatile resistive memory element includes a novel switching layer and methods of forming the same. The switching layer includes a material having bistable resistance properties and formed by bonding silicon to oxygen or nitrogen. The switching layer may include at least one of SiOx, SiOxNy, or SiNx. Advantageously, the SiOx, SiOxNy, and SiNx generally remain amorphous after thermal anneal processes are used to form the devices, such as ReRAM devices.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: April 28, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Randall J. Higuchi, Chien-Lan Hsueh, Yun Wang
  • Patent number: 9018069
    Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a diode. The diode comprises a first doped region, a second doped region and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region and the third doped region are separated from each other by the first doped region. The third doped region has a first portion and a second portion adjacent to each other. The first portion and the second portion are respectively adjacent to and away from the second doped region. A dopant concentration of the first portion is bigger than a dopant concentration of the second portion.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: April 28, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Chieh-Chih Chen, Cheng-Chi Lin, Shih-Chin Lien, Shyi-Yuan Wu
  • Patent number: 9018070
    Abstract: The present invention discloses a transient voltage suppressor (TVS) circuit, and a diode device therefor and a manufacturing method thereof. The TVS circuit is for coupling to a protected circuit to limit amplitude of a transient voltage which is inputted to the protected circuit. The TVS circuit includes a suppressor device and at least a diode device. The diode device is formed in a substrate, which includes: a well formed in the substrate; a separation region formed beneath the upper surface; a anode region and a cathode region, which are formed at two sides of the separation region beneath the upper surface respectively, wherein the anode region and the cathode region are separated by the separation region; and a buried layer, which is formed in the substrate below the well with a higher impurity density and a same conductive type as the well.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: April 28, 2015
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Tsung-Yi Huang, Jin-Lian Su
  • Publication number: 20150097269
    Abstract: The present invention discloses a transient voltage suppression (TVS) device and a manufacturing method thereof. The TVS device includes: a conductive layer; a P-type semiconductor substrate, which is formed on the conductive layer; an N-type buried layer, which is formed on the semiconductor substrate; a P-type lightly doped layer, which is formed on the buried layer; a P-type cap region, which is formed on the lightly doped layer; and an N-type reverse region, which is formed on the cap region, wherein a Zener diode includes the reverse region and the cap region, and an NPN bipolar junction transistor (BJT) includes the reverse region, the cap region, the lightly doped layer and the buried layer.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Wu-Te Weng
  • Patent number: 9000516
    Abstract: A super-junction device including a unit region is disclosed. The unit region includes a heavily doped substrate; a first epitaxial layer over the heavily doped substrate; a second epitaxial layer over the first epitaxial layer; a plurality of first trenches in the second epitaxial layer; an oxide film in each of the plurality of first trenches; and a pair of first films on both sides of each of the plurality of first trenches, thereby forming a sandwich structure between every two adjacent ones of the plurality of first trenches, the sandwich structure including two first films and a second film sandwiched therebetween, the second film being formed of a portion of the second epitaxial layer between the two first films of a sandwich structure. A method of forming a super-junction device is also disclosed.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: April 7, 2015
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventor: Shengan Xiao
  • Publication number: 20150084154
    Abstract: Methods and apparatus for ESD structures. A semiconductor device includes a first active area containing an ESD cell coupled to a first terminal and disposed in a well; a second active area in the semiconductor substrate, the second active area comprising a first diffusion of the first conductivity type for making a bulk contact to the well; and a third active area in the semiconductor substrate, separated from the first and second active areas by another isolation region, a portion of the third active area comprising an implant diffusion of the first conductivity type within a first diffusion of the second conductivity type and adjacent a boundary with the well of the first conductivity type; wherein the third active area comprises a diode coupled to the terminal and reverse biased with respect to the well of the first conductivity type.
    Type: Application
    Filed: December 3, 2014
    Publication date: March 26, 2015
    Inventors: Yu-Ying Hsu, Tzu-Heng Chang, Jen-Chou Tseng, Ming-Hsiang Song, Johannes Van Zwol, Taede Smedes
  • Publication number: 20150085407
    Abstract: Protection device structures and related fabrication methods and devices are provided. An exemplary device includes a first interface, a second interface, a first protection circuitry arrangement coupled to the first interface, and a second protection circuitry arrangement coupled between the first protection circuitry arrangement and the second interface. The second protection circuitry arrangement includes a first transistor and a diode coupled to the first transistor, wherein the first transistor and the diode are configured electrically in series between the first protection circuitry arrangement and the second interface.
    Type: Application
    Filed: September 23, 2013
    Publication date: March 26, 2015
    Inventors: WEIZE CHEN, PATRICE M. PARRIS
  • Patent number: 8963246
    Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: February 24, 2015
    Assignees: Inter-University Research Institute Corporation High Energy Accelerator Research Organization, LAPIS Semiconductor Co., Ltd.
    Inventors: Yasuo Arai, Masao Okihara, Hiroki Kasai
  • Patent number: 8946038
    Abstract: A method of forming one or more diodes in a fin field-effect transistor (FinFET) device includes forming a hardmask layer having a fin pattern, said fin pattern including an isolated fin area, a fin array area, and a FinFET area. The method further includes etching a plurality of fins into a semiconductor substrate using the fin pattern, and depositing a dielectric material over the semiconductor substrate to fill spaces between the plurality of fins. The method further includes planarizing the semiconductor substrate to expose the hardmask layer. The method further includes implanting a p-type dopant into the fin array area and portions of the FinFET area, and implanting an n-type dopant into the isolated fin area, a portion of the of fin array area surrounding the p-well and portions of the FinFET area. The method further includes annealing the semiconductor substrate.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hsin Hu, Sun-Jay Chang, Jaw-Juinn Horng, Chung-Hui Chen
  • Publication number: 20140319598
    Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device.
    Type: Application
    Filed: April 24, 2013
    Publication date: October 30, 2014
    Inventor: Madhur Bobde
  • Patent number: 8871600
    Abstract: Schottky barrier diodes, methods for fabricating Schottky barrier diodes, and design structures for a Schottky barrier diode. A guard ring for a Schottky barrier diode is formed with a selective epitaxial growth process. The guard ring for the Schottky barrier diode and an extrinsic base of a vertical bipolar junction diode on a different device region than the Schottky barrier diode may be concurrently formed using the same selective epitaxial growth process.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: David L. Harame, Qizhi Liu, Robert M. Rassel
  • Patent number: 8865541
    Abstract: An integrated circuit contains a voltage protection structure having a diode isolated DENMOS transistor with a guard element proximate to the diode and the DENMOS transistor. The guard element includes an active area coupled to ground. The diode anode is connected to an I/O pad. The diode cathode is connected to the DENMOS drain. The DENMOS source is grounded. A process of forming the integrated circuit is also disclosed.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: October 21, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Farzan Farbiz, Akram A. Salman
  • Patent number: 8846482
    Abstract: A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: September 30, 2014
    Assignee: Avogy, Inc.
    Inventors: David P. Bour, Richard J. Brown, Isik C. Kizilyalli, Thomas R. Prunty, Linda Romano, Andrew P. Edwards, Hui Nie, Mahdan Raj
  • Patent number: 8772106
    Abstract: Memory devices are described along with methods for manufacturing and methods for operating. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Memory cells in the plurality of memory cells comprise a diode and a metal-oxide memory element programmable to a plurality of resistance states including a first and a second resistance state, the diode of the memory element arranged in electrical series along a current path between a corresponding word line and a corresponding bit line. The device further includes bias circuitry to apply bias arrangements across the series arrangement of the diode and the memory element of a selected memory cell in the plurality of memory cells.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: July 8, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Ming-Daou Lee, Erh-Kun Lai, Kuang-Yeu Hsieh, Wei-Chih Chien, Chien Hung Yeh
  • Patent number: 8759880
    Abstract: An ultra-high voltage silicon-germanium (SiGe) heterojunction bipolar transistor (HBT), which includes: a P-type substrate; an N-type matching layer, a P-type matching layer and an N? collector region stacked on the P-type substrate from bottom up; two field oxide regions separately formed in the N? collector region; N+ pseudo buried layers, each under a corresponding one of the field oxide regions and in contact with each of the N-type matching layer, the P-type matching layer and the N? collector region; an N+ collector region between the two field oxide regions and through the N? collector region and the P-type matching layer and extending into the N-type matching layer; and deep hole electrodes, each in a corresponding one of the field oxide regions and in contact with a corresponding one of the N+ pseudo buried layers. A method of fabricating an ultra-high voltage SiGe HBT is also disclosed.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: June 24, 2014
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Jing Shi, Donghua Liu, Jun Hu, Wensheng Qian, Wenting Duan, Fan Chen
  • Publication number: 20140160827
    Abstract: The present invention relates to electronic memory circuits, and more particularly, to low power electronic memory circuits having low manufacturing costs. The present invention is a circuit design that utilizes two transistor types—bipolar and MOS (but, not both NMOS and PMOS) one of which can be manufactured together with the memory cell's non-linear conductive elements (such as a diode) thereby reducing the number of processing steps and masks and resulting in lower cost.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 12, 2014
    Inventor: Daniel Robert Shepard
  • Publication number: 20140124894
    Abstract: The disclosed technology relates to a semiconductor device comprising a diode junction between two semiconductor regions of different doping types. In one aspect, the diode comprises a junction formed between an upper portion of an active area and a remainder of the active area, where the active area is defined in a substrate between two field dielectric regions. The upper portion is a portion of the active area that has a width smaller than a width of the active area itself. In another aspect, the semiconductor device is an electrostatic discharge protection device (ESD) comprising such a diode. In addition, the active area has a doping profile that exhibits a maximum value at the surface of the active area, and changes to a minimum value at a first depth, where the first depth can be greater in value than half of a depth of the upper portion.
    Type: Application
    Filed: October 29, 2013
    Publication date: May 8, 2014
    Applicant: IMEC
    Inventors: Geert Hellings, Mirko Scholz, Dimitri Linten
  • Publication number: 20140126091
    Abstract: Protection device structures and related fabrication methods are provided. An exemplary protection device includes a first bipolar junction transistor, a second bipolar junction transistor, a first zener diode, and a second zener diode. The collectors of the first bipolar junction transistors are electrically coupled. A cathode of the first zener diode is coupled to the collector of the first bipolar transistor and an anode of the first zener diode is coupled to the base of the first bipolar transistor. A cathode of the second zener diode is coupled to the collector of the second bipolar transistor and an anode of the second zener diode is coupled to the base of the second bipolar transistor. In exemplary embodiments, the base and emitter of the first bipolar transistor are coupled at a first interface and the base and emitter of the second bipolar transistor are coupled at a second interface.
    Type: Application
    Filed: November 8, 2012
    Publication date: May 8, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chai Ean Gill, Changsoo Hong, Rouying Zhan, William G. Cowden
  • Patent number: 8686513
    Abstract: An IGBT die structure includes an auxiliary P well region. A terminal, that is not connected to any other IGBT terminal, is coupled to the auxiliary P well region. To accelerate IGBT turn on, a current is injected into the terminal during the turn on time. The injected current causes charge carriers to be injected into the N drift layer of the IGBT, thereby reducing turn on time. To accelerate IGBT turn off, charge carriers are removed from the N drift layer by drawing current out of the terminal. To reduce VCE(SAT), current can also be injected into the terminal during IGBT on time. An IGBT assembly involves the IGBT die structure and an associated current injection/extraction circuit. As appropriate, the circuit injects or extracts current from the terminal depending on whether the IGBT is in a turn on time or is in a turn off time.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: April 1, 2014
    Assignee: IXYS Corporation
    Inventor: Kyoung Wook Seok
  • Patent number: 8680585
    Abstract: There is provided a light emitting diode package and a method of manufacturing the same. A light emitting diode package according to an aspect of the invention may include: an LED chip; a body part having the LED chip mounted thereon; a pair of reflective parts extending from the body part to face each other while interposing the LED chip therebetween, and reflecting light emitted from the LED chip; and a molding part provided between the pair of reflective parts to encapsulate the LED chip and having a top surface whose central region is curved inwards.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: March 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Sam Park, Hun Joo Hahm
  • Patent number: 8642421
    Abstract: A light-emitting diode (LED) structure fabricated with a SixNy layer responsible for providing increased light extraction out of a surface of the LED is provided. Such LED structures fabricated with a SixNy layer may have increased luminous efficiency when compared to conventional LED structures fabricated without a SixNy layer. Methods for creating such LED structures are also provided.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: February 4, 2014
    Assignee: SemiLEDS Optoelectronics Co., Ltd.
    Inventor: Chuong Anh Tran
  • Patent number: 8617958
    Abstract: Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing sidewalls of the stack, and then an entirety of the sacrificial material may be removed to leave a gap between the first conductive material and the at least one dielectric material. In some embodiments of forming diodes, a layer may be formed over a first conductive material, with the layer containing supports interspersed in sacrificial material. At least one dielectric material may be formed over the layer, and a second conductive material may be formed over the at least one dielectric material. An entirety of the sacrificial material may then be removed.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: December 31, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu, Bhaskar Srinivasan
  • Patent number: 8610241
    Abstract: Diodes and bipolar junction transistors (BJTs) are formed in IC devices that include fin field-effect transistors (FinFETs) by utilizing various process steps in the FinFET formation process. The diode or BJT includes an isolated fin area and fin array area having n-wells having different depths and a p-well in a portion of the fin array area that surrounds the n-well in the isolated fin area. The n-wells and p-well for the diodes and BJTs are implanted together with the FinFET n-wells and p-wells.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: December 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hsin Hu, Sun-Jay Chang, Jaw-Juinn Horng, Chung-Hui Chen
  • Patent number: 8609502
    Abstract: In a method of manufacturing a semiconductor device, a semiconductor substrate of a first conductivity type having first and second surfaces is prepared. Second conductivity type impurities for forming a collector layer are implanted to the second surface using a mask that has an opening at a portion where the collector layer will be formed. An oxide layer is formed by enhanced-oxidizing the collector layer. First conductivity type impurities for forming a first conductivity type layer are implanted to the second surface using the oxide layer as a mask. A support base is attached to the second surface and a thickness of the semiconductor substrate is reduced from the first surface. An element part including a base region, an emitter region, a plurality of trenches, a gate insulating layer, a gate electrode, and a first electrode is formed on the first surface of the semiconductor substrate.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: December 17, 2013
    Assignee: DENSO CORPORATION
    Inventors: Masaki Koyama, Yutaka Fukuda
  • Patent number: 8587224
    Abstract: Provided are a variable field effect transistor (FET) designed to suppress a reduction of current between a source and a drain due to heat while decreasing a temperature of the FET, and an electrical and electronic apparatus including the variable gate FET. The variable gate FET includes a FET and a gate control device that is attached to a surface or a heat-generating portion of the FET and is connected to a gate terminal of the FET so as to vary a voltage of the gate terminal. A channel current between the source and drain is controlled by the gate control device that varies the voltage of the gate terminal when the temperature of the FET increases above a predetermined temperature.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: November 19, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyun-Tak Kim, Bongjun Kim
  • Patent number: 8575695
    Abstract: This invention discloses configurations and methods to manufacture lateral power device including a super-junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: November 5, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Anup Bhalla, Hamza Yilmaz, Wilson Ma, Lingpeng Guan, Yeeheng Lee, John Chen
  • Patent number: 8536679
    Abstract: In the case of adjacent high voltage nodes in which one node is protected by a lateral BJT clamp, the irreversible burnout due to transient latch-up between the two adjacent high voltage pins of the structure is avoided by increasing the base contact region by including a sinker connected to the base.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: September 17, 2013
    Assignee: National Semiconductor Corporation
    Inventor: Vladislav Vashchenko
  • Patent number: 8530318
    Abstract: In some aspects, a method of fabricating a memory cell is provided that includes: (1) fabricating a first conductor above a substrate; (2) selectively fabricating a carbon nano-tube (“CNT”) material above the first conductor by: (a) fabricating a CNT seeding layer on the first conductor, wherein the CNT seeding layer comprises silicon-germanium (“Si/Ge”), (b) planarizing a surface of the deposited CNT seeding layer, and (c) selectively fabricating CNT material on the CNT seeding layer; (3) fabricating a diode above the CNT material; and (4) fabricating a second conductor above the diode. Numerous other aspects are provided.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: September 10, 2013
    Assignee: SanDisk 3D LLC
    Inventor: April D. Schricker
  • Patent number: 8518799
    Abstract: A process of making semiconductor-on-glass substrates having a relatively stiff (e.g. relatively high Young's modulus of 125 or higher) stiffening layer between the silicon film and the glass in an ion implantation thin film transfer process by depositing a stiffening layer or layers on one of the donor wafer or the glass substrate in order to eliminate the canyons and pin holes that otherwise form in the surface of the transferred silicon film during the thin film transfer process. The new stiffening layer may be formed of a material, such as silicon nitride, that also serves as an efficient barrier against penetration of sodium and other harmful impurities from the glass substrate into the silicon film.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 27, 2013
    Assignees: Corning Incorporated, S.O.I TEC Silicon on Insulator Technologies
    Inventors: Nadia Ben Mohamed, Ta-Ko Chuang, Jeffrey Scott Cites, Daniel Delprat, Alex Usenko
  • Patent number: 8516693
    Abstract: The present invention discloses a printed circuit board. The printed circuit board is made by the method of providing a substrate; forming a first circuit on the substrate; depositing a thin film on the substrate; building an electronic component on the substrate by the thin film and allowing the electronic component to electrically connect the first circuit; forming a blanket dielectric layer enclosing the electronic component; and removing the substrate.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: August 27, 2013
    Assignee: Mutual-Tek Industries Co., Ltd.
    Inventor: Jung-Chien Chang
  • Patent number: 8513083
    Abstract: Disclosed herein are various methods of forming an anode and a cathode of a substrate diode by performing angled ion implantation processes. In one example, the method includes performing a first angled ion implantation process to form a first doped region in a bulk layer of an SOI substrate for one of the anode or the diode and, after performing the first angled ion implantation process, performing a second angled ion implantation process to form a second doped region in the bulk layer of the SOI substrate for the other of the anode and the diode, wherein said first and second angled ion implantation process are performed through the same masking layer.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: August 20, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Baars, Thilo Scheiper
  • Patent number: 8507352
    Abstract: In a method of manufacturing a semiconductor device, a semiconductor substrate of a first conductivity type having first and second surfaces is prepared. Second conductivity type impurities for forming a collector layer are implanted to the second surface using a mask that has an opening at a portion where the collector layer will be formed. An oxide layer is formed by enhanced-oxidizing the collector layer. First conductivity type impurities for forming a first conductivity type layer are implanted to the second surface using the oxide layer as a mask. A support base is attached to the second surface and a thickness of the semiconductor substrate is reduced from the first surface. An element part including a base region, an emitter region, a plurality of trenches, a gate insulating layer, a gate electrode, and a first electrode is formed on the first surface of the semiconductor substrate.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: August 13, 2013
    Assignee: DENSO CORPORATION
    Inventors: Masaki Koyama, Yutaka Fukuda
  • Patent number: 8502478
    Abstract: Provided are a variable field effect transistor (FET) designed to suppress a reduction of current between a source and a drain due to heat while decreasing a temperature of the FET, and an electrical and electronic apparatus including the variable gate FET. The variable gate FET includes a FET and a gate control device that is attached to a surface or a heat-generating portion of the FET and is connected to a gate terminal of the FET so as to vary a voltage of the gate terminal. A channel current between the source and drain is controlled by the gate control device that varies the voltage of the gate terminal when the temperature of the FET increases above a predetermined temperature.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: August 6, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyun Tak Kim, Bong Jun Kim
  • Patent number: 8476140
    Abstract: A diode and memory device including the diode, where the diode includes a conductive portion and another portion formed of a first material that has characteristics allowing a first decrease in a resistivity of the material upon application of a voltage to the material, thereby allowing current to flow there through, and has further characteristics allowing a second decrease in the resistivity of the first material in response to an increase in temperature of the first material.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: July 2, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu, Bhaskar Srinivasan
  • Patent number: 8455980
    Abstract: The self heating of a high-performance bipolar transistor that is formed on a fully-isolated single-crystal silicon region of a silicon-on-insulator (SOI) structure is substantially reduced by forming a Schottky structure in the same fully-isolated single-crystal silicon region as the bipolar transistor is formed.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: June 4, 2013
    Assignee: National Semiconductor Corporation
    Inventor: Jeffrey A. Babcock
  • Publication number: 20130127017
    Abstract: A Reverse Bipolar Junction Transistor (RBJT) integrated circuit comprises a bipolar transistor and a parallel-coupled distributed diode. The bipolar transistor involves many N-type collector regions. Each N-type collector region has a central hole so that P-type material from an underlying P-type region extends up into the hole. A collector metal electrode covers the central hole forming a diode contact at the top of the hole. When the distributed diode conducts, current flows from the collector electrode, down through the many central holes in the many collector regions, through corresponding PN junctions, and to an emitter electrode disposed on the bottom side of the IC. The RBJT and distributed diode integrated circuit has emitter-to-collector and emitter-to-base reverse breakdown voltages exceeding twenty volts. The collector metal electrode is structured to contact the collector regions, and to bridge over the base electrode, resulting in a low collector-to-emitter voltage when the RBJT is on.
    Type: Application
    Filed: November 17, 2011
    Publication date: May 23, 2013
    Applicant: IXYS Corporation
    Inventor: Kyoung Wook Seok
  • Publication number: 20130119505
    Abstract: Schottky barrier diodes, methods for fabricating Schottky barrier diodes, and design structures for a Schottky barrier diode. A guard ring for a Schottky barrier diode is formed with a selective epitaxial growth process. The guard ring for the Schottky barrier diode and an extrinsic base of a vertical bipolar junction diode on a different device region than the Schottky barrier diode may be concurrently formed using the same selective epitaxial growth process.
    Type: Application
    Filed: November 11, 2011
    Publication date: May 16, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David L. Harame, Qizhi Liu, Robert M. Rassel
  • Patent number: 8390090
    Abstract: Provided is a semiconductor device with a high breakdown voltage yield of a bipolar transistor and a high bandwidth and quantum efficiency of a light receiving element. An optical semiconductor device includes monolithically integrated transistor and light receiving element. The light receiving element includes a p-type semiconductor layer, an n-type epitaxial layer formed on the p-type semiconductor layer, and an n-type diffusion layer formed on the n-type epitaxial layer. An n-type impurity concentration of the n-type diffusion layer is 3×1018 cm?3 or less at a depth of 0.12 ?m or more below a surface of the n-type diffusion layer, 1×1016 cm?3 or more at a depth of 0.4 ?m or less below the surface, and 1×1016 cm?3 or less at a depth of 0.8 ?m or more below the surface, and an interface between the p-type semiconductor layer and the n-type epitaxial layer is located at a depth of 0.9 ?m to 1.5 ?m below the surface.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: March 5, 2013
    Assignee: NEC Corporation
    Inventor: Takao Morimoto
  • Patent number: 8390092
    Abstract: An area-efficient, high voltage, single polarity ESD protection device (300) is provided which includes an p-type substrate (303); a first p-well (308-1) formed in the substrate and sized to contain n+ and p+ contact regions (310, 312) that are connected to a cathode terminal; a second, separate p-well (308-2) formed in the substrate and sized to contain only a p+ contact region (311) that is connected to an anode terminal; and an electrically floating n-type isolation structure (304, 306, 307-2) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: March 5, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Amaury Gendron, Chai Ean Gill, Vadim A. Kushner, Rouying Zhan
  • Patent number: 8378392
    Abstract: A trench Metal Oxide Semiconductor Field Effect Transistor with improved body region structures is disclosed. By forming the inventive body region structures with concave-arc shape with respect to epitaxial layer, a wider interfaced area between the body region and the epitaxial layer is achieved, thus increasing capacitance between drain and source Cds. Moreover, the invention further comprises a Cds enhancement doped region interfaced with said body region having higher doping concentration than the epitaxial layer to further enhancing Cds without significantly impact breakdown voltage.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: February 19, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8354316
    Abstract: A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: January 15, 2013
    Inventors: Anup Bhalla, Xiaobin Wang, Wei Wang, Yi Su, Daniel Ng
  • Patent number: 8350301
    Abstract: A semiconductor photodiode includes a semiconductor substrate; a first conduction type first semiconductor layer formed above the semiconductor substrate; a high resistance second semiconductor layer formed above the first semiconductor layer; a first conduction type third semiconductor layer formed above the second semiconductor layer; and a second conduction type fourth semiconductor layer buried in the second semiconductor layer, in which the fourth semiconductor layer is separated at a predetermined distance in a direction horizontal to the surface of the semiconductor substrate.
    Type: Grant
    Filed: July 17, 2010
    Date of Patent: January 8, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Miura, Shinichi Saito, Youngkun Lee, Katsuya Oda
  • Patent number: 8343828
    Abstract: Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing sidewalls of the stack, and then an entirety of the sacrificial material may be removed to leave a gap between the first conductive material and the at least one dielectric material. In some embodiments of forming diodes, a layer may be formed over a first conductive material, with the layer containing supports interspersed in sacrificial material. At least one dielectric material may be formed over the layer, and a second conductive material may be formed over the at least one dielectric material. An entirety of the sacrificial material may then be removed.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: January 1, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu, Bhaskar Srinivasan