Including Diode Patents (Class 438/328)
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Publication number: 20040207046Abstract: High-voltage bipolar transistors (30, 60) in silicon-on-insulator (SOI) integrated circuits are disclosed. In one disclosed embodiment, an collector region (28) is formed in epitaxial silicon (24, 25) disposed over a buried insulator layer (22). A base region (32) and emitter (36) are disposed over the collector region (28). Buried collector region (31) are disposed in the epitaxial silicon (24) away from the base region (32). The transistor may be arranged in a rectangular fashion, as conventional, or alternatively by forming an annular buried collector region (31). According to another disclosed embodiment, a high voltage transistor (60) includes a central isolation structure (62), so that the base region (65) and emitter region (66) are ring-shaped to provide improved performance. A process for fabricating the high voltage transistor (30, 60) simultaneously with a high performance transistor (40) is also disclosed.Type: ApplicationFiled: May 12, 2004Publication date: October 21, 2004Inventors: Jeffrey A. Babcock, Gregory E. Howard, Angelo Pinto, Phillipp Steinmann, Scott G. Balster
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Patent number: 6803249Abstract: A photodetector is integrated on a single semiconductor chip with bipolar transistors including a high speed poly-emitter vertical NPN transistor. The photodetector includes a silicon nitride layer serving as an anti-reflective film. The silicon nitride layer and oxide layers on opposite sides thereof insulate edges of a polysilicon emitter from the underlying transistor regions, minimizing the parasitic capacitance between the NPN transistor's emitter and achieving a high frequency response. The method of manufacture is compatible with existing BiCMOS process technology, the silicon nitride layer of the anti-reflective film being formed over the photodetector as well as regions of the chip that include the vertical NPN transistor and other circuit elements.Type: GrantFiled: February 4, 2003Date of Patent: October 12, 2004Assignee: STMicroelectronics, Inc.Inventors: Danielle A. Thomas, Gilles E. Thomas
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Patent number: 6784046Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: GrantFiled: March 22, 2002Date of Patent: August 31, 2004Assignee: Micron Techology, Inc.Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Patent number: 6774003Abstract: A method for manufacturing a pair of electrodes comprises fabricating a first electrode with a substantially flat surface and placing a sacrificial layer over a surface of the first electrode, wherein the sacrificial layer comprises a first material. A second material is placed over the sacrificial layer, wherein the second material comprises a material that is suitable for use as a second electrode. The sacrificial layer is removed with an etchant, wherein the etchant chemically reacts with the first material, and further wherein a region between the first electrode and the second electrode comprises a gap that is a distance of 50 nanometers or less, preferably 5 nanometers or less. Alternatively, the sacrificial layer is removed by cooling the sandwich with liquid nitrogen, or alternatively still, the sacrificial layer is removed by heating the sacrificial layer, thereby evaporating the sacrificial layer.Type: GrantFiled: July 9, 2002Date of Patent: August 10, 2004Assignee: Borealis Technical LimitedInventors: Avto Tavkhelidze, Larisa Koptonashvili, Zauri Berishvili, Givi Skhiladze
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Patent number: 6767785Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filed with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.Type: GrantFiled: April 19, 2002Date of Patent: July 27, 2004Assignee: Micron Technology, Inc.Inventors: J. Brett Rolfson, Monte Manning
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Patent number: 6756280Abstract: In a semiconductor device having a junction type diode using a bipolar transistor and a process for producing the same, a ratio of a diode electric current to a leakage electric current is improved, and latch up resistance is improved without increasing the process. A p type semiconductor substrate, a collector buried region and an n type epitaxial layer are formed, a p type first impurity region is formed in the n type epitaxial layer, an n type second impurity region is formed in the first impurity region, an N+ sinker is formed, and a collector electrode is formed, with a common electrode being formed on the first and second impurity regions.Type: GrantFiled: May 21, 2003Date of Patent: June 29, 2004Assignee: Sony CoporationInventors: Tomotaka Fujisawa, Chihiro Arai
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Patent number: 6740552Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: GrantFiled: March 22, 2002Date of Patent: May 25, 2004Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Patent number: 6734497Abstract: An insulated gate bipolar transistor, a semiconductor device using such a transistor, and manufacturing methods of these. The transistor, device, and method eliminate the necessity of connection to a freewheel diode used for bypassing a circulating current. In the transistor, device, and method the concentration of impurities of an N+ buffer layer that forms a junction with a P+ collector layer is increased so that it is possible to reduce an avalanche breakdown voltage of a parasitic diode formed by an N base layer and the P+ collector layer. Thus, the reverse voltage resistance of an IGBT is lowered to not more than 5 times the collector-emitter saturated voltage.Type: GrantFiled: September 27, 2002Date of Patent: May 11, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideki Takahashi, Yoshifumi Tomomatsu, Mitsuharu Tabata
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Patent number: 6734031Abstract: A solid-state imaging device, comprises: a semi-conductor substrate demarcating a two-dimensional surface; a multiplicity of photoelectric conversion units formed being arranged in a plurality of rows and columns on the semiconductor substrate; a planarizing insulating film formed above the semiconductor substrate; and a plurality of gap-less microlenses having spectral characters, each gap-less microlens being formed above each of the photoelectric conversion units with the planarizing insulating film placed in-between.Type: GrantFiled: May 9, 2003Date of Patent: May 11, 2004Assignee: Fuji Photo Film Co., Ltd.Inventor: Makoto Shizukuishi
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Patent number: 6706606Abstract: A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation. The buried Zener diode has its N++/P+ junction removed from the silicon surface.Type: GrantFiled: June 19, 2003Date of Patent: March 16, 2004Assignee: Texas Instruments IncorporatedInventors: Gregory G. Romas, Jr., Darrel C. Oglesby, Jr.
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Patent number: 6703284Abstract: The invention relates to the protection of devices in a monolithic chip fabricated from an epitaxial wafer, such as a wafer for a Group III-V compound semiconductor or a wafer for a Group IV compound semiconductor. Devices fabricated from Group III-V compound semiconductors offer higher speed and better isolation than comparable devices from silicon semiconductors. Semiconductor devices can be permanently damaged when exposed to an undesired voltage transient such as electrostatic discharge (ESD). However, conventional techniques developed for silicon devices are not compatible with processing techniques for Group III-V compound semiconductors, such as gallium arsenide (GaAs). Embodiments of the invention advantageously include transient voltage protection circuits that are relatively efficiently and reliably manufactured to protect sensitive devices from undesired voltage transients.Type: GrantFiled: September 30, 2002Date of Patent: March 9, 2004Assignee: Microsemi CorporationInventor: Vrej Barkhordarian
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Patent number: 6689667Abstract: The present invention relates to a photoreceiver and method of manufacturing the same. For the purpose of a selective detection of a specific wavelength, if a waveguide type photodetector using a multiple quantum-well layer having a quantum confined stark effect as an optical absorption layer, the wavelength that is absorbed by the stark effect by which the transition energy edge of the optical absorption band is varied depending on the intensity of an electric field applied to the multiple quantum-well layer is varied. Thus, a wavelength selective detection characteristic can be varied simply implemented. The waveguide type photodetector of this structure is integrated on a semi-insulating InP substrate with a heterogeneous bipolar transistor having an n+InP/p+InGaAs/n−InGaAs/n+InGaAsP high-gain amplification characteristic.Type: GrantFiled: July 30, 2002Date of Patent: February 10, 2004Assignee: Electronics and Telecommunications Research InstituteInventors: Eun soo Nam, Heacheon Kim
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Patent number: 6686249Abstract: The present invention pertains to a transparent conductive layered structure having a transparent substrate and a transparent 2-layer film consisting of a transparent conductive layer and a transparent coating layer formed in succession on this substrate, that is used for instance, in the front panel of displays, such as CRTs, etc. The above-mentioned transparent conductive layer has as its main components noble metal microparticles with a mean particle diameter of 1 to 100 nm composed of gold and/or platinum and silver and containing 5 to 95 wt % gold and/or platinum, colored pigment microparticles with a mean particle diameter of 5 to 200 nm, and binder matrix. The noble metal microparticles are mixed at a ratio of 1 to 40 parts by weight per 1 part by weight colored pigment microparticles. Moreover, it is characterized in that the transparent 2-layer film has a surface resistance of 10 to 5000 &OHgr;/□, reflectance of 0 to 2.Type: GrantFiled: November 14, 2000Date of Patent: February 3, 2004Assignee: Sumitomo Metal Mining Co., Ltd.Inventors: Masaya Yukinobu, Yoshihiro Ohtsuka, Kenji Kato, Yukiko Suekane, Midori Fujisaki
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Publication number: 20030232479Abstract: Provided is a method of manufacturing a ferroelectric capacitor capable of manufacturing a ferroelectric capacitor with lower unevenness on a ferroelectric film surface, and thereby with excellent electric characteristics. By sputtering method, a PZT film is formed on a first conductive film, which constitutes a lower electrode of the ferroelectric capacitor. Thereafter, the PZT film is subjected to crystallization treatment (annealing). Next, a silicate solution is coated on the PZT film as a sintering assistance and then dried. Subsequently, sintering treatment is performed at the temperature of about 700C.°. In this way, crystals constituting the PZT film are sintered, unevenness on the surface of PZT film is reduced, and tiny pores in grain boundaries are also reduced.Type: ApplicationFiled: June 10, 2003Publication date: December 18, 2003Applicant: FUJITSU LIMITEDInventors: Kazuaki Kondo, Hideyuki Noshiro
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Patent number: 6645802Abstract: An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate.Type: GrantFiled: June 8, 2001Date of Patent: November 11, 2003Assignee: Xilinx, Inc.Inventors: Sheau-Suey Li, Shahin Toutounchi, Michael J. Hart, Xin X. Wu, Daniel Gitlin
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Patent number: 6638781Abstract: There is provided a high quality liquid crystal panel having a thickness with high accuracy, which is designed, without using a particulate spacer, within a free range in accordance with characteristics of a used liquid crystal and a driving method, and is also provided a method of fabricating the same. The shape of a spacer for keeping a substrate interval constant is made such that it is a columnar shape, a radius R of curvature is 2 &mgr;m or less, a height H is 0.5 &mgr;m to 10 &mgr;m, a diameter is 20 &mgr;m or less, and an angle &agr; is 65° to 115°. By doing so, it is possible to prevent the lowering of an opening rate and the lowering of light leakage due to orientation disturbance.Type: GrantFiled: June 29, 2000Date of Patent: October 28, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshiharu Hirakata, Yuugo Goto, Yuko Kobayashi, Shunpei Yamazaki
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Patent number: 6603189Abstract: A technique of improving a reverse recovery characteristic of a semiconductor device which solves a technical problem of breakdown voltage reduction which has conventionally caused in enhancing soft recover. To solve the technical problem, in a PN junction between a P type layer and an N type layer, a heavy metal such as platinum is firstly diffused into an—layer and N+ layer of the N type layer. Subsequently, helium ion is implanted into the inside of the—layer from the interface between the P type layer and the N+ layer to a predetermined depth, so that the N− layer in the vicinity of the junction is damaged to form, in the—layer, a low lifetime region having a carrier lifetime smaller than that of the N type layer and a resistibility that decreases monotonically. Such a technique may be applied to diodes, and particularly, free-wheel diodes in power modules.Type: GrantFiled: February 14, 2000Date of Patent: August 5, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Hideki Takahashi
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Patent number: 6579772Abstract: A semiconductor device is provided, which prevents the development of localized breakdowns at the semiconductor sidewall, having a stabilized, desired breakdown voltage. It embraces a p-type third semiconductor region formed on a first main surface of an n-type semiconductor body; an n-type second semiconductor region selectively formed at the center of a second main surface; an n-type first semiconductor region formed between the third and the second semiconductor regions; and, n-type fourth semiconductor region surrounding the first and the second semiconductor regions. The impurity concentration of the first semiconductor region is set higher than that of the fourth semiconductor region.Type: GrantFiled: December 7, 2001Date of Patent: June 17, 2003Assignee: Sanken Electric Co., Ltd.Inventor: Hideyuki Andoh
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Patent number: 6563194Abstract: A semiconductor device having: a base area of the first conduction type formed on a semiconductor substrate; an emitter area of the second conduction type formed in the base area; and a collector area of the second conduction type formed as joined to the base area. In the collector area, an impurity area of the first conduction type is formed as separated from the base area. A surface resistor is connected to a base electrode connected to the base area. The surface resistor is connected, at other position thereof, to the impurity area.Type: GrantFiled: September 21, 2000Date of Patent: May 13, 2003Assignee: Rohm Co., Ltd.Inventor: Kazuhisa Sakamoto
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Patent number: 6555440Abstract: A method of fabricating a diode device, such as a PIN diode, includes forming top and bottom regions of opposite conductivity types and includes anisotropically etching into the top surface to form a pit having side walls that converge with approach to the bottom surface. However, the pit does not extend to the bottom surface. In the PIN diode embodiment, the pit terminates within an intrinsic region that separates a bottom surface diffusion region from a diffusion region along the walls of the anisotropically etched pit. The anisotropic etching approach provides a degree of self regulation with regard to the geometries of the pit. A process flow of steps is described, which allows thicker and larger diameter wafers to be used in the formation of an array of such diode device.Type: GrantFiled: June 5, 2000Date of Patent: April 29, 2003Assignee: Agilent Technologies, Inc.Inventor: Frank Sigming Geefay
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Patent number: 6524900Abstract: A method for controlling the temperature dependence of a junction barrier Schottky diode of a semiconductor material having an energy gap between the valence band and the conduction band exceeding 2 eV provides for doing this when producing the diode by adjusting the on-state resistance of the grid portion of the diode during the production for obtaining a temperature dependence of the operation of the diode adapted to the intended use thereof.Type: GrantFiled: July 25, 2001Date of Patent: February 25, 2003Assignee: ABB Research, LTDInventors: Fanny Dahlqvist, Heinz Lendenmann, Willy Hermansson
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Publication number: 20030036238Abstract: A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition.Type: ApplicationFiled: September 27, 2002Publication date: February 20, 2003Applicant: The Regents of the University of CaliforniaInventors: Daniel Toet, Thomas W. Sigmon
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Patent number: 6507089Abstract: A semiconductor device is provided with a plurality of hetero junction bipolar transistors arranged in a specified direction. Also, the semiconductor device comprises emitter wiring connected to each emitter of the plural hetero junction bipolar transistors, collector wiring connected to each collector of said plural hetero junction bipolar transistors, and base wiring connected to at least one base of said plural hetero junction bipolar transistors. Bases that are not connected to the base wiring among the bases of the plural hetero junction bipolar transistors are connected to the emitter wiring.Type: GrantFiled: June 7, 2000Date of Patent: January 14, 2003Assignee: NEC CorporationInventors: Kouji Azuma, Nobuyuki Hayama, Norio Goto
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Publication number: 20020119591Abstract: A tunnel diode has a quantum well having at least one layer of semiconductor material. The tunnel diode also has a pair of injection layers on either side of the quantum well. The injection layers comprise a collector layer and an emitter layer. A barrier layer is positioned between each of the injection layers and the quantum well. The quantum well has an epitaxial relationship with the emitter layer. An amount of one element of the well layer is increased to increase the lattice constant a predetermined amount. The lattice constant may have a reduction in the conduction band energy. A second element is added to the well layer to increase the conduction band energy but not to change the lattice constant. By controlling the composition in this matter, the negative resistance, and thus the effective mass, may be controlled for various diode constructions.Type: ApplicationFiled: February 15, 2002Publication date: August 29, 2002Inventor: Joel N. Schulman
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Patent number: 6432788Abstract: The present invention comprises methods for producing semiconductor devices useful in high temperature applications. The invention is based on using silicon ion implantation to convert a portion of the p-type base layer of magnesium-doped GaN into n-type GaN. The boundary of the n-type GaN within the p-type layer then becomes an n-p diode junction which can function as the emitter-base junction. The present methods utilize ion implantation to convert a portion of the p-type layer to n-type thereby forming an n-p junction having desirable diode characteristics. The invention also includes BJT and HBT devices incorporating the present implanted n-p diode junctions.Type: GrantFiled: July 24, 2000Date of Patent: August 13, 2002Assignee: Implant Sciences CorporationInventors: H. Paul Maruska, Stephen N. Bunker
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Patent number: 6432764Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.Type: GrantFiled: November 30, 1999Date of Patent: August 13, 2002Assignee: Micron Technology, Inc.Inventors: J. Brett Rolfson, Monte Manning
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Publication number: 20020102804Abstract: The package size of a diode is made smaller. On the element forming face of a semiconductor substrate having a p−-type conductive type, after a hyper-abrupt p+n+ junction of a p+-type diffusion layer, an n+-type hyper-abrupt layer, an n−-epitaxial layer, an n-type low resistance layer and an n+-type diffusion layer is formed, an anode electrode is formed on the top of the p+-type diffusion layer and a cathode electrode is formed on the top of the n+-type diffusion layer. Thereafter, electrode bumps are formed on the top of the anode electrode and the cathode electrode to thereby manufacture a small diode that can be facedown bonded onto a mounting board.Type: ApplicationFiled: January 17, 2002Publication date: August 1, 2002Applicant: Hitachi, Ltd.Inventors: Hiroyuki Nagase, Shuichi Suzuki, Masaki Otoguro, Yasuharu Ichinose, Teruhiro Mitsuyasu
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Patent number: 6423598Abstract: A Schottky diode which provides a structure having no P-N junction while improving voltage resistance against a reverse bias when employed in combination with an insulated gate semiconductor device in particular. In order to attain the aforementioned object, a P-type impurity region having a surface exposed on a surface of an N-type semiconductor substrate functioning as a drain for functioning as a channel region and a gate insulator film covering it are provided. A gate electrode is extended from above the gate insulator film over a first taper of an oxide film. In a Schottky diode rendering the semiconductor substrate a cathode and having a boundary layer as a Schottky region, on the other hand, an anode electrode is extended from above the boundary layer over a second taper of the oxide film existing above an end portion of the boundary layer.Type: GrantFiled: June 8, 2000Date of Patent: July 23, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideki Takahashi, Shuuichi Tominaga
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Publication number: 20020081800Abstract: In a semiconductor device such as GaN semiconductor laser having an electrode formed on a nitride III-V compound semiconductor layer containing at least Ga, such as GaN layer, at least a part of the electrode in contact with the nitride III-V compound semiconductor layer is made of a &ggr;-GaNi alloy or a &ggr;′-GaNi alloy. The electrode is made by first stacking the &ggr;-GaNi alloy layer or &ggr;′-GaNi alloy layer, or its component elements, on the nitride III-V compound semiconductor layer, and then annealing it at a temperature not lower than 680° C., or by stacking any of them on the nitride-compound III-V compound semiconductor layer heated to a temperature not lower than 680° C. At least a part of the electrode in contact with the nitride III-V compound smiconductor layer may be made of an alloy of Ga and at least one kind of element selected from the group consisting of Pt, Ag, Pd, Mg, Hf, Al, Cr, Ti, Mo, W, Zr, Si and Ge.Type: ApplicationFiled: July 26, 1999Publication date: June 27, 2002Inventor: ETSUO MORITA
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Patent number: 6392285Abstract: The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so that the thickness of the dielectric layer of the capacitor device decreased relative to a specific ion concentration. Accordingly, the capacitor device formed therein has a high capacitance and good performance.Type: GrantFiled: December 14, 1999Date of Patent: May 21, 2002Assignee: Winbond Electronics CorporationInventors: Chih-Mu Huang, Chuan-Jane Chao, Chi-Hung Kao
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Publication number: 20020055218Abstract: A light emitting diode (LED) is disclosed. An emitted light can be prevented from being absorbed by a substrate by using a bragg reflector layer with high reflectivity. The present invention provides a bragg reflector layer comprising a plurality of high aluminum-contained AlGaAs/AlGaInP layers or high aluminumcontained AlGaAs/low aluminum-contained AlGaInP layers formed on the substrate before the epitaxial structure of the light emitting diode being formed. Since the high aluminum-contained AlGaAs is oxidized and formed an oxide of a lower refraction index, the reflectivity and high reflection zones of the oxidized bragg reflector layer are much larger. According to the electrical insulation characteristic of the oxide, the bragg reflector layer can limit the current within the oxidized regions of high aluminum-contained AlGaAs layer. Therefore, the aforementioned light emitting diode structure has a higher brightness than the conventional light emitting diode.Type: ApplicationFiled: October 31, 2001Publication date: May 9, 2002Inventors: Shu-Woei Chiou, Holin Chang, Tzer-Perng Chen, Chih-Sung Chang
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Patent number: 6384433Abstract: A voltage variable resistor formed on heterojunction bipolar transistor epitaxial material includes a current channel made on emitter material. Emitter mesas separated by a recess provide the contacts for the voltage variable resistor. Each mesa is topped with emitter metal forming the resistor contacts. The emitter mesas are layered on top of the current channel that is layered atop of a base layer. The voltage variable resistor's control contact is provided by a base contact located on the base layer and separated from the current channel.Type: GrantFiled: March 23, 2000Date of Patent: May 7, 2002Assignee: RF Micro Devices, Inc.Inventors: Curtis A. Barratt, Arthur E. Geissberger, Larry W. Kapitan, Michael T. Fresina, Ramond Jeffrey Vass
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Publication number: 20020048859Abstract: A method of fabricating a stripe photodiode element, for an image sensor cell, has been developed. The stripe photodiode element is comprised of a narrow width, serpentine shaped, lightly doped N type region, in a P well region. The use of the serpentine shaped region results in increased photon collection area, when compared to counterparts fabricated using non-serpentine shaped patterns. In addition the use of the serpentine shaped N type regions allow both vertical, as well as horizontal depletion regions, to result, thus increasing the quantum efficiency of the photodiode element. The combination of narrow width, and a reduced dopant level, for the N type serpentine shaped region, result in a fully depleted photodiode element.Type: ApplicationFiled: September 20, 2001Publication date: April 25, 2002Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Dun-Nian Yaung, Shou-Gwo Wuu, Chien-Hsien Tseng
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Patent number: 6344368Abstract: The present invention is related to a method for forming a CMOS image sensor device. A CMOS image device has a first MOS device acting as a source follower of an active pixel, a second MOS device acting as a row select of the active pixel. An amorphous silicon layer acts as a photo-diode area for collecting incident light over the first MOS device and the second MOS device. The amorphous silicon layer has both N-type and P-type dopants.Type: GrantFiled: June 26, 2000Date of Patent: February 5, 2002Assignee: United Microelectronics Corp.Inventor: Jui-Hsiang Pan
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Publication number: 20020003287Abstract: In a method for producing a high-speed power diode with soft recovery, in which method the carrier life within the associated semiconductor substrate (10) is governed by first, unmasked bombardment (14) with an axial profile and by subsequent, second, masked bombardment (15) with a lateral profile, improved reverse characteristics are achieved in that the first, unmasked bombardment is ion bombardment (14) which governs the switching response of the power diode and in that the second, masked bombardment is electron bombardment (15), which reduces the active area of the power diode.Type: ApplicationFiled: July 3, 2001Publication date: January 10, 2002Inventor: Norbert Galster
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Publication number: 20010042867Abstract: A monolithically integrated semiconductor device comprises: a hetero-junction bipolar transistor having at least an electrode contact layer which contacts directly with at least one of collector, base and emitter electrodes; and at least a passive device having at least a passive device electrode and at least a resistive layer, wherein the electrode contact layer and the resistive layer comprise the same compound semiconductor layer.Type: ApplicationFiled: May 4, 2001Publication date: November 22, 2001Applicant: NEC CORPORATIONInventor: Naoki Furuhata
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Publication number: 20010041410Abstract: A method for the production and formation of microscopic semiconductor light emitting diodes is set out. The method comprises the steps of: producing a semiconductor light emitting device (100) including a pn-junction (2-4) and metallization layers (6, 7); applying an etching mask (9-11) with a preset structure on one side of the semiconductor device (100), whereby the masked areas of the arrangement form and correspond to the diodes to be formed (30); applying a carrier (8, 12) on the other side of the semiconductor device (100); vertically etching the semiconductor material in the openings of the etching mask (9-11) to the carrier (8, 12) and thereby producing a diode arrangement containing a multiple number of diodes (30) below the masked areas.Type: ApplicationFiled: December 29, 2000Publication date: November 15, 2001Inventor: Gerhard Franz
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Publication number: 20010039096Abstract: A method for adjusting Vt while minimizing parasitic capacitance for low voltage high speed semiconductor devices. The method uses shadow effects and an angled punch through prevention implant between vertical structures to provide a graded implant. The implant angle is greater than or equal to arc tangent of S/H where S is the horizontal distance between, and H is the height of, such vertical structures.Type: ApplicationFiled: July 13, 2001Publication date: November 8, 2001Inventor: Luan C. Tran
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Publication number: 20010035564Abstract: A semiconductor device for an integrated injection logic cell having a pnp bipolar transistor structure formed on a semiconductor substrate, wherein at least one layer of insulating films formed on a base region of the pnp bipolar transistor structure is comprised of a silicon nitride film. The semiconductor device of the present invention is advantageous in that the silicon nitride film constituting at least one layer of the insulating films formed on the base region of the pnp bipolar transistor prevents an occurrence of contamination on the surface of the base region, so that both the properties of the pnp bipolar transistor and the operation of the IIL cell can be stabilized. Further, by the process of the present invention, the above-mentioned excellent semiconductor device can be produced.Type: ApplicationFiled: February 7, 2001Publication date: November 1, 2001Inventor: Hirokazu Ejiri
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Publication number: 20010024768Abstract: A pattern forming material includes a binary copolymer represented by the following general formula or a ternary or higher copolymer obtained by further polymerizing the binary copolymer with another group: 1Type: ApplicationFiled: April 16, 2001Publication date: September 27, 2001Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Takahiro Matsuo, Masayuki Endo, Masamitsu Shirai, Masahiro Tsunooka
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Patent number: 6291304Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device)d a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.Type: GrantFiled: September 15, 1999Date of Patent: September 18, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jun-Lin Tsaz, Ruey-Hsin Liu, Jyh-Min Jiang, Jei-Feng Hwang
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Patent number: 6284614Abstract: A method of manufacturing a semiconductor device includes (a) providing a semiconductor substrate of a first conductive type, (b) forming a field insulating film on the semiconductor substrate, and (c) providing a first region and a second region in which the field insulating film is not formed on the semiconductor substrate. Also, the method includes (d) forming a gate insulating film on both the first region and the second region at a same time, (e) removing the gate insulating film formed on the second region to expose a surface portion of the semiconductor substrate, and (f) forming a diffusion layer of the first conductive type in the second region from which the gate insulating film is removed.Type: GrantFiled: August 9, 1999Date of Patent: September 4, 2001Assignee: NEC CorporationInventor: Ko Noguchi
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Patent number: 6261874Abstract: A soft recovery diode is made by first implanting helium into the die to a location below the P/N junction and the implant annealed. An E-beam radiation process then is applied to the entire wafer and is also annealed. The diode then has very soft recovery characteristics without requiring heavy metal doping.Type: GrantFiled: June 14, 2000Date of Patent: July 17, 2001Assignee: International Rectifier Corp.Inventors: Richard Francis, Chiu Ng
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Patent number: 6245610Abstract: A method of protecting a well at a floating stage. In a first conductive type substrate, a second conductive type well is formed. A first conductive type heavily doped region and a second conductive type heavily doped region are respectively formed in the first conductive type substrate and the second conductive type well. These two heavily doped regions are electrically connected with each at an early stage of fabrication process to provide a protection from being damaged during subsequent plasma process or other processes. While forming a top metal layer of a multi-level interconnect, these two heavily doped regions are disconnected, that is, open to each other, to obtain a better electrical characteristic of the device or the integrated circuit formed on the substrate.Type: GrantFiled: September 28, 1999Date of Patent: June 12, 2001Assignee: United Microelectronics Corp.Inventors: Mu-Chun Wang, Tzung-Han Lee, Shiang Huang-Lu
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Patent number: 6184100Abstract: In a light receiving element and a semiconductor device manufacturing method, the low density PN junction is formed by constructing the internal composition of the photodiode with N+ type diffusion layer, N− type epitaxial layer, P− type epitaxial layer, P+ type deposit layer, and P type Si from the light receiving surface, the vacant layer to be occurred when the photodiode is reverse biased will be widened and the light receiving sensitivity and the frequency characteristic will be improved. Furthermore, since the separation of bipolar elements will be conducted by P− epitaxial layer, the efficiency in density control at the time of P− type epitaxial growth can be improved.Type: GrantFiled: June 13, 1997Date of Patent: February 6, 2001Assignee: Sony CorporationInventor: Chihiro Arai
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Patent number: 6180444Abstract: A semiconductor device such as a P-N or P-I-N junction diode, includes a first semiconductor layer having a first conductivity-type and being mounted over a metal address line, and a second semiconductor layer having a second conductivity-type and being mounted over the first semiconductor material. The diode preferably has a thickness of substantially no more than about 1 micron, and the diode includes a P-N junction confined to a thickness of less than about 0.1 micron. In the preferred embodiment the method comprises depositing a first semiconductor layer having a first conductivity type, depositing a second intrinsic layer, annealing to convert both layers to a polycrystalline layer, implanting ions of a second conductivity type into the second layer, and annealing to convert the second layer to a polycrystalline. The result is a diode having an ultra-sharp p-n junction.Type: GrantFiled: February 18, 1998Date of Patent: January 30, 2001Assignee: International Business Machines CorporationInventors: Stephen McConnell Gates, Roy Edwin Scheuerlein
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Patent number: 6146957Abstract: Since the PN junction of a photodiode is formed of a silicon substrate having a low impurity concentration and an epitaxial layer, the width of the depletion layer in the PN junction is formed wider, the parasitic capacitance by the junction capacitance is lowered, and the diffusion length of the silicon substrate is formed longer. Besides, a buried layer containing a high impurity concentration is formed by a high energy ion implantation method in such a depth that the buried layer cannot be depleted by a reverse voltage applied to the PN junction, which is served as a region to lead out the anode, which accordingly results in a low parasitic resistance at the anode. Thereby, the invention provides a semiconductor device including a photodetector and a method of manufacturing the same that achieves a high photoelectric conversion sensitivity and an excellent frequency characteristic at the same time.Type: GrantFiled: March 31, 1998Date of Patent: November 14, 2000Assignee: Sony CorporationInventor: Youichi Yamasaki
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Patent number: 6140188Abstract: A small-area, high-resistance load device is fabricated in the same area used for the shallow trench isolation region. In an example embodiment, the load device comprises a series resistor coupled to a poly-silicon diode. In one example application, the load device acts as a pull-up device replacing standard PMOS pull-up loads used in connection with static memory cells, thereby increasing the cell density of a static memory array.Type: GrantFiled: May 20, 1998Date of Patent: October 31, 2000Assignee: Philips Semiconductors, Inc.Inventors: Harlan Sur, Subhas Bothra
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Patent number: 6103564Abstract: A diode is formed by forming a PN junction region 6 with a p region 5 formed on a buried oxide film 19 side and an n region 7 formed on the surface side in a surface silicon layer 3 which is isolated by the buried oxide film 19 of an SOI substrate 1, providing a lightly doped p region 33 on one end side of the PN junction region 6 and a lightly doped n region 31 on an other end side, forming a heavily doped p region 13 and a heavily doped n region 9 at the respective surface portions of the lightly doped p region 33 and the lightly doped n region 31 in such a manner as not to contact the PN junction region 6, and providing two metal plates which respectively connect to the heavily doped p region 13 and the heavily doped n region 9.Type: GrantFiled: December 13, 1999Date of Patent: August 15, 2000Assignee: Citizen Watch Co., Ltd.Inventor: Takashi Masuda
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Patent number: 6096618Abstract: The invention is a method of fabricating a self-aligned, sub-minimum guard ring for a Schottky diode device wherein the sub-minimum guard ring is positioned at the inside edges of adjacent isolation structures and is self-aligned to the intrinsic base implanted regions. In this particular invention, illustrating the guard ring fabrication technique, an improved Schottky diode is fabricated at minimum groundrules which utilizes a frequency-doubling resist and an appropriate mask to provide the implant mask for a p- or n-type guard ring. This shallow implant near the surface prepares a guard ring that minimizes the electric field at the interface where the deposited metal or silicide joins the STI structure. Additional ion implants with energies greater than and less than the guard ring implantation energy may be deposited to tailor the substrate surface and reduce the parasitic capacitance of the diode.Type: GrantFiled: January 20, 1998Date of Patent: August 1, 2000Assignee: International Business Machines CorporationInventors: James S. Dunn, Stephen A. St. Onge