Forming Lateral Transistor Structure Patents (Class 438/335)
  • Patent number: 9018072
    Abstract: An electrostatic discharge (ESD) protection clamp (21, 21?, 70, 700) for protecting associated devices or circuits (24), comprises a bipolar transistors (21, 21?, 70, 700) in which doping of facing base (75) and collector (86) regions is arranged so that avalanche breakdown occurs preferentially within a portion (84, 85) of the base region (74, 75) of the device (70, 700) away from the overlying dielectric-semiconductor interface (791). Maximum variations (?Vt1)MAX of ESD triggering voltage Vt1 as a function of base-collector spacing dimensions D due, for example, to different azimuthal orientations of transistors (21, 21?, 70, 700) on a semiconductor die or wafer is much reduced. Triggering voltage consistency and manufacturing yield are improved.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: April 28, 2015
    Assignee: Freescale Semiconductor Inc.
    Inventors: Amaury Gendron, Chai Ean Gill, Changsoo Hong
  • Publication number: 20150097265
    Abstract: A device includes a semiconductor substrate, emitter and collector regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite base region disposed in the semiconductor substrate, having a second conductivity type, and including a base contact region, a buried region through which a buried conduction path between the emitter and collector regions is formed during operation, and a base link region electrically connecting the base contact region and the buried region. The base link region has a dopant concentration level higher than the buried region and is disposed laterally between the emitter and collector regions.
    Type: Application
    Filed: October 7, 2013
    Publication date: April 9, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 8962436
    Abstract: A bipolar junction transistor (BJT) and method for fabricating such. The transistor includes an emitter region, a collector region, and an intrinsic-base region. The intrinsic-base region is positioned between the emitter region and the collector region. Furthermore, the physical separation between the emitter region and the collector region is less than the sum of a base-emitter space-charge region width and a base-collector space-charge region width at the transistor's standby mode.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Tak H. Ning, Ghavam G. Shahidi, Jeng-Bang Yau
  • Patent number: 8946040
    Abstract: A Bipolar Junction Transistor with an intrinsic base, wherein the intrinsic base includes a top surface and two side walls orthogonal to the top surface, and a base contact electrically coupled to the side walls of the intrinsic base. In one embodiment an apparatus can include a plurality of Bipolar Junction Transistors, and a base contact electrically coupled to the side walls of the intrinsic bases of each BJT.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Tak H. Ning
  • Patent number: 8946862
    Abstract: Methods are provided for forming a device that includes merged vertical and lateral transistors with collector regions of a first conductivity type between upper and lower base regions of opposite conductivity type that are Ohmically coupled via intermediate regions of the same conductivity type and to the base contact. The emitter is provided in the upper base region and the collector contact is provided in outlying sinker regions extending to the thin collector regions and an underlying buried layer. As the collector voltage increases part of the thin collector regions become depleted of carriers from the top by the upper and from the bottom by the lower base regions. This clamps the collector regions' voltage well below the breakdown voltage of the PN junction formed between the buried layer and the lower base region. The gain and Early Voltage are increased and decoupled and a higher breakdown voltage is obtained.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: February 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 8946860
    Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a collector region of semiconductor material having a first conductivity type, a base region of semiconductor material within the collector region, the base region having a second conductivity type opposite the first conductivity type, and a doped region of semiconductor material having the second conductivity type, wherein the doped region is electrically connected to the base region and the collector region resides between the base region and the doped region. In exemplary embodiments, the dopant concentration of the doped region is greater than a dopant concentration of the collector region to deplete the collector region as the electrical potential of the base region exceeds that of the collector region.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: February 3, 2015
    Assignee: Freescale Semiconductor Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Publication number: 20140266407
    Abstract: A bipolar junction transistor and an operating method and a manufacturing method for the same are provided. The bipolar junction transistor comprises a first doped region, a second doped region and a third doped region. The first doped region has a first type conductivity. The second doped region comprises well regions formed in the first doped region, having a second type conductivity opposite to the first type conductivity, and separated from each other by the first doped region. The third doped region has the first type conductivity. The third doped region is formed in the well regions or in the first doped region between the well regions.
    Type: Application
    Filed: April 23, 2013
    Publication date: September 18, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD
    Inventors: Li-Fan Chen, Wing-Chor Chan, Jeng Gong
  • Patent number: 8829640
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: September 9, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Hamza Yilmaz
  • Publication number: 20140231962
    Abstract: A bipolar junction transistor (BJT) is provided. The BJT can include a semiconductor substrate, a first well disposed in the substrate and implanted with a first impurity, a second well disposed at one side of the first well and implanted with a second impurity, a first device isolation layer disposed in the first well and defining an emitter area, and a second device isolation layer disposed in the second well and defining a collector area, The BJT can also include an emitter having a second impurity, a base having a first impurity, a collector having a second impurity, and a high concentration doping area having a second impurity at high concentration. The high concentration doping area can be provided at one side of the collector in the second well.
    Type: Application
    Filed: March 15, 2013
    Publication date: August 21, 2014
    Applicant: DONGBU HITEK CO., LTD.
    Inventors: Jae Hyun YOO, Jong Min KIM
  • Patent number: 8796088
    Abstract: A semiconductor device and a method of fabricating the semiconductor device is provided. In the method, a semiconductor substrate defining a device region and an outer region at a periphery of the device region is provided, an align trench is formed in the outer region, a dummy trench is formed in the device region, an epi layer is formed over a top surface of the semiconductor substrate and within the dummy trench, a current path changing part is formed over the epi layer, and a gate electrode is formed over the current path changing part. When the epi layer is formed, a current path changing trench corresponding to the dummy trench is formed over the epi layer, and the current path changing part is formed within the current path changing trench.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: August 5, 2014
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Chul Jin Yoon
  • Patent number: 8796100
    Abstract: The present invention discloses a method of manufacturing an N-type LDMOS device. The method comprises forming a gate above the semiconductor substrate; forming a body, comprising forming a Pwell apart from the gate and forming a Pbase partly in the Pwell, wherein the Pbase is wider and shallower than the Pwell; and forming an N-type source and a drain contact region. Wherein the body curvature of the LDMOS device is controlled by adjusting the layout width of the Pwell.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: August 5, 2014
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Jeesung Jung
  • Publication number: 20140110825
    Abstract: Compound semiconductor lateral PNP bipolar transistors are fabricated based on processes traditionally used for formation of compound semiconductor NPN heterojunction bipolar transistors and hence such PNP bipolar transistors can be fabricated inexpensively using existing fabrication technologies. In particular, GaAs-based lateral PNP bipolar transistors are fabricated using GaAs-based NPN heterojunction bipolar transistor fabrication processes.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 24, 2014
    Applicant: ANALOG DEVICES, INC.
    Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo, Shuyun Zhang
  • Publication number: 20140103299
    Abstract: Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on semiconductor wafers, the CNT-based devices can be combined with the conventional semiconductor circuit elements, thus producing hybrid devices and circuits.
    Type: Application
    Filed: December 16, 2013
    Publication date: April 17, 2014
    Inventor: ALEXANDER KASTALSKY
  • Patent number: 8686505
    Abstract: A method produces a semiconductor device including a semiconductor body, an electrode thereon, and an insulating structure insulating the electrode from the semiconductor body. The semiconductor body includes a first contact region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, and a second contact region having a higher maximum doping concentration than the drift region. The insulating structure includes a gate dielectric portion forming a first horizontal interface. with the drift region and has a first maximum vertical extension A field dielectric portion forms with the drift region second and third horizontal interfaces arranged below the main surface. A second maximum vertical extension of the field dielectric portion is larger than the first maximum vertical extension. A third maximum vertical extension of the field dielectric portion is larger than the second maximum vertical extension.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: April 1, 2014
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Marc Strasser, Karl-Heinz Gebhardt, Ralf Rudolf, Lincoln O'Riain
  • Patent number: 8669640
    Abstract: An improved device (20) is provided, comprising, merged vertical (251) and lateral transistors (252), comprising thin collector regions (34) of a first conductivity type sandwiched between upper (362) and lower (30) base regions of opposite conductivity type that are Ohmically coupled via intermediate regions (32, 361) of the same conductivity type and to the base contact (38). The emitter (40) is provided in the upper base region (362) and the collector contact (42) is provided in outlying sinker regions (28) extending to the thin collector regions (34) and an underlying buried layer (28). As the collector voltage increases part of the thin collector regions (34) become depleted of carriers from the top by the upper (362) and from the bottom by the lower (30) base regions. This clamps the thin collector regions' (34) voltage well below the breakdown voltage of the PN junction formed between the buried layer (28) and the lower base region (30).
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: March 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 8659117
    Abstract: A schottky diode includes a drift region of a first conductivity type and a lightly doped silicon region of the first conductivity type in the drift region. A conductor layer is over and in contact with the lightly doped silicon region to form a schottky contact with the lightly doped silicon region. A highly doped silicon region of the first conductivity type is in the drift region and is laterally spaced from the lightly doped silicon region such that upon biasing the schottky diode in a conducting state, a current flows laterally between the lightly doped silicon region and the highly doped silicon region through the drift region. A plurality of trenches extend into the drift region perpendicular to the current flow. Each trench has a dielectric layer lining at least a portion of the trench sidewalls and at least one conductive electrode.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: February 25, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Christopher Boguslaw Kocon
  • Patent number: 8546229
    Abstract: Insufficient gain in bipolar transistors (20) is improved by providing an alloyed (e.g., silicided) emitter contact (452) smaller than the overall emitter (42) area. The improved emitter (42) has a first emitter (FE) portion (42-1) of a first dopant concentration CFE, and a second emitter (SE) portion (42-2) of a second dopant concentration CSE. Preferably CSE?CFE. The SE portion (42-2) desirably comprises multiple sub-regions (45i, 45j, 45k) mixed with multiple sub-regions (47m, 47n, 47p) of the FE portion (42-1). A semiconductor-metal alloy or compound (e.g., a silicide) is desirably used for Ohmic contact (452) to the SE portion (42-2) but substantially not to the FE portion (42-1). Including the FE portion (42-1) electrically coupled to the SE portion (42-2) but not substantially contacting the emitter contact (452) on the SE portion (42-2) provides gain increases of as much as ˜278.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: October 1, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 8460976
    Abstract: The present invention relates to a manufacturing method of SOI devices, and in particular, to a manufacturing method of SOI high-voltage power devices.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: June 11, 2013
    Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
    Inventors: Xinhong Cheng, Zhongjian Wang, Yuehui Yu, Dawei He, Dawei Xu, Chao Xia
  • Patent number: 8431450
    Abstract: An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: April 30, 2013
    Assignee: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Budong You, Yang Lu
  • Publication number: 20130075741
    Abstract: A lateral bipolar transistor with deep emitter and deep collector regions is formed using multiple epitaxial layers of the same conductivity type. Deep emitter and deep collector regions are formed without the use of trenches. Vertically aligned diffusion regions are formed in each epitaxial layer so that the diffusion regions merged into a contiguous diffusion region after annealing to function as emitter or collector or isolation structures. In another embodiment, a lateral trench PNP bipolar transistor is formed using trench emitter and trench collector regions. In yet another embodiment, a lateral PNP bipolar transistor with a merged LDMOS transistor is formed to achieve high performance.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 28, 2013
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INC.
    Inventors: Shekar Mallikarjunaswamy, François Hébert
  • Patent number: 8404552
    Abstract: A microscopic spectrum apparatus for connecting to an image capturing module which is used for converting external image light into electrical signal is disclosed. The microscopic spectrum apparatus includes a microscopic lens module, a spectrum analyzing module and a light beam splitter. The microscopic lens module is used for collecting the external image light to the image capturing module and magnifying the external image. The spectrum analyzing module is arranged at a side of the microscopic lens module. The light beam splitter is arranged between the microscopic lens module and the image capturing module, and is used for directing part of the external image light from the microscopic lens module to the spectrum analyzing module. In addition, a microscopic spectrum apparatus with image capturing capability is also disclosed.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: March 26, 2013
    Assignee: Lumos Technology Co., Ltd.
    Inventor: Chih-Yi Yang
  • Patent number: 8377788
    Abstract: A SiGe heterojunction bipolar transistor is fabricated by etching an epitaxially-formed structure to form a mesa that has a collector region, a cap region, and a notched SiGe base region that lies in between. A protective plug is formed in the notch of the SiGe base region so that thick non-conductive regions can be formed on the sides of the collector region and the cap region. Once the non-conductive regions have been formed, the protective plug is removed. An extrinsic base is then formed to lie in the notch and touch the base region, followed by the formation of isolation regions and an emitter region.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: February 19, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Wibo Van Noort, Jamal Ramdani, Andre Labonte, Donald Robertson Getchell
  • Patent number: 8377755
    Abstract: A method of manufacturing a SOI high voltage power chip with trenches is disclosed. The method comprises: forming a cave and trenches at a SOI substrate; filling oxide in the cave; oxidizing the trenches, forming oxide isolation regions for separating low voltage devices at the same time; filling oxide in the oxidized trenches; and then forming drain regions, source regions and gate regions for a high voltage power device and low voltage devices. The process involves depositing an oxide layer overlapping the cave of the SOI substrate. A SOI high voltage power chip thus made will withstand at least above 700V voltage.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: February 19, 2013
    Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
    Inventors: Xinhong Cheng, Zhongjian Wang, Yuehui Yu, Dawei He, Dawei Xu, Chao Xia
  • Publication number: 20120264270
    Abstract: Embodiments for forming improved bipolar transistors are provided, manufacturable by a CMOS IC process. The improved transistor comprises an emitter having first and second portions of different depths, a base underlying the emitter having a central portion of a first base width underlying the first portion of the emitter, a peripheral portion having a second base width larger than the first base width partly underlying the second portion of the emitter, and a transition zone of a third base width and lateral extent lying laterally between the first and second portions of the base, and a collector underlying the base. The gain of the transistor is larger than a conventional bipolar transistor made using the same CMOS process. By adjusting the lateral extent of the transition zone, the properties of the improved transistor can be tailored to suit different applications without modifying the underlying CMOS IC process.
    Type: Application
    Filed: June 27, 2012
    Publication date: October 18, 2012
    Applicant: Freescale Semiconductor, Inc.
    Inventors: XIN LIN, Daniel J. Blomberg, Jiang-Kai Zou
  • Patent number: 8236642
    Abstract: A semiconductor structure includes a semiconductor substrate; an n-type tub extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the n-type tub comprises a bottom buried in the semiconductor substrate; a p-type buried layer (PBL) on a bottom of the tub, wherein the p-type buried layer is buried in the semiconductor substrate; and a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL and within a region encircled by sides of the n-type tub.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: August 7, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-San Wei, Kuo-Ming Wu, Yi-Chun Lin
  • Patent number: 8173510
    Abstract: An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of the surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: May 8, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Marie Denison, Taylor Rice Efland
  • Publication number: 20120098095
    Abstract: Instability and drift sometimes observed in bipolar transistors, having a portion of the base extending to the transistor surface between the emitter and base contact, can be reduced or eliminated by providing a further doped region of the same conductivity type as the emitter at the transistor surface between the emitter and the base contact. The further region is desirably more heavily doped than the base region at the surface and less heavily doped than the adjacent emitter. In another embodiment, a still or yet further region of the same conductivity type as the emitter is provided either between the further region and the emitter or laterally within the emitter. The still or yet further region is desirably more heavily doped than the further region. Such further regions shield the near surface base region from trapped charge that may be present in dielectric layers or interfaces overlying the transistor surface.
    Type: Application
    Filed: October 20, 2010
    Publication date: April 26, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xin Lin, Daniel J. Blomberg, Hongning Yang, Jiang-Kai Zuo
  • Patent number: 8164096
    Abstract: A flat panel display device, more particularly, an Organic Light Emitting Diode (OLED) display device having uniform electrical characteristics and a method of fabricating the same include: a thin film transistor of which a semiconductor layer including a source, a drain, and a channel region formed in a super grain silicon (SGS) crystallization growth region; a capacitor formed in an SGS crystallization seed region; and an OLED electrically connected to the thin film transistor. Further, a length of the channel region of the silicon layer is parallel with the growth direction in the SGS growth region to improve the electrical properties thereof.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: April 24, 2012
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Jong-Hyun Choi, Woo-Sik Jun
  • Patent number: 8153515
    Abstract: A nitride based heterojunction transistor includes a substrate and a first Group III nitride layer, such as an AlGaN based layer, on the substrate. The first Group III-nitride based layer has an associated first strain. A second Group III-nitride based layer, such as a GaN based layer, is on the first Group III-nitride based layer. The second Group III-nitride based layer has a bandgap that is less than a bandgap of the first Group III-nitride based layer and has an associated second strain. The second strain has a magnitude that is greater than a magnitude of the first strain. A third Group III-nitride based layer, such as an AlGaN or AlN layer, is on the GaN layer. The third Group III-nitride based layer has a bandgap that is greater than the bandgap of the second Group III-nitride based layer and has an associated third strain. The third strain is of opposite strain type to the second strain. A source contact, a drain contact and a gate contact may be provided on the third Group III-nitride based layer.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: April 10, 2012
    Assignee: Cree, Inc.
    Inventor: Adam William Saxler
  • Patent number: 8129249
    Abstract: Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: March 6, 2012
    Assignee: Infineon Technologies AG
    Inventors: Karlheinz Mueller, Klaus Roeschlau
  • Publication number: 20120043643
    Abstract: An electrostatic discharge (EDS) device includes a substrate, an external well of a first conductivity type in the substrate, and an internal well of a second conductivity type in the external well, the first conductivity type opposite the second conductivity type. The EDS device further includes a first heavily doped region of the first conductivity type located at a surface of the internal well, a second heavily doped region of the second conductivity type located at a surface of the internal well, and a third heavily doped region of the first conductivity type located at a surface of the external well. The second heavily doped region is interposed between and spaced from each of the first and third heavily doped regions, and at least one of a space between the first and second heavily doped regions and a space between the second and third heavily doped regions is devoid of a device isolation structure of electrical isolation material.
    Type: Application
    Filed: March 7, 2011
    Publication date: February 23, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-ryul Chang, Oh-kyunm Kwon
  • Patent number: 8030167
    Abstract: Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: October 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, Louis D. Lanzerotti, Bradley A. Orner, Jay S. Rascoe, David C. Sheridan, Stephen A. St. Onge
  • Patent number: 8021952
    Abstract: Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: September 20, 2011
    Assignee: Infineon Technologies AG
    Inventors: Karlheinz Mueller, Klaus Roeschlau
  • Patent number: 7998779
    Abstract: A solid-state imaging device includes: a solid-state imaging element having a light-receiving area; a transparent member disposed so as to oppose the light-receiving area; a supporting member configured to support the transparent member; a first mark disposed at either an upper surface of the transparent member or an upper surface of the supporting member; and a second mark disposed at an outer side of the light-receiving area, at an upper surface of the solid-state imaging element.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: August 16, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Naoyuki Watanabe, Takao Ohno, Susumu Moriya, Izumi Kobayashi
  • Patent number: 7989301
    Abstract: Disclosed is a semiconductor device with a bipolar transistor and method of fabricating the same. The device may include a collector region in a semiconductor substrate. A base pattern may be disposed on the collector region. A hard mask pattern may be disposed on the base pattern. The hard mask pattern may include a buffering insulation pattern and a flatness stopping pattern stacked in sequence. An emitter electrode may be disposed in a hole that locally exposes the base pattern, penetrating the hard mask pattern. A base electrode may contact an outer sidewall of the hard mask pattern and may be disposed on the base pattern. The flatness stopping pattern may contain an insulative material with etching selectivity to the buffering insulation pattern, the emitter electrode, and the base electrode.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: August 2, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Bong-Gil Yang
  • Patent number: 7888732
    Abstract: An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of said surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: February 15, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Marie Denison, Taylor Rice Efland
  • Publication number: 20110012232
    Abstract: An improved device (20) is provided, comprising, merged vertical (251) and lateral transistors (252), comprising thin collector regions (34) of a first conductivity type sandwiched between upper (362) and lower (30) base regions of opposite conductivity type that are Ohmically coupled via intermediate regions (32, 361) of the same conductivity type and to the base contact (38). The emitter (40) is provided in the upper base region (362) and the collector contact (42) is provided in outlying sinker regions (28) extending to the thin collector regions (34) and an underlying buried layer (28). As the collector voltage increases part of the thin collector regions (34) become depleted of carriers from the top by the upper (362) and from the bottom by the lower (30) base regions. This clamps the thin collector regions' (34) voltage well below the breakdown voltage of the PN junction formed between the buried layer (28) and the lower base region (30).
    Type: Application
    Filed: July 14, 2009
    Publication date: January 20, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 7868378
    Abstract: An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.
    Type: Grant
    Filed: July 17, 2006
    Date of Patent: January 11, 2011
    Assignee: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Budong You, Yang Lu
  • Patent number: 7851320
    Abstract: A mesostructured aluminosilicate material is described, constituted by at least two spherical elementary particles, each of said spherical particles being constituted by a matrix based on silicon oxide and aluminum oxide, having a pore size in the range 1.5 to 30 nm, a Si/Al molar ratio of at least 1, having amorphous walls with a thickness in the range 1 to 20 nm, said spherical elementary particles having a maximum diameter of 10 ?m. A process for preparing said material and its application in the fields of refining and petrochemistry are also described.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: December 14, 2010
    Assignee: IFP Energies Nouvelles
    Inventors: Alexandra Chaumonnot, Aurélie Coupe, Clément Sanchez, Patrick Euzen, Cédric Boissiere, David Grosso
  • Patent number: 7816763
    Abstract: According to one embodiment, a collector electrode including metal is used for a sink region for connecting an n+ type buried layer, so that the sink region can be narrowly formed. Further, an interval between a base region and the collector electrode can be reduced, thereby considerably decreasing the size of the transistor. Furthermore, collector resistance is reduced, so that the performance of the transistor can be improved.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: October 19, 2010
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Nam Joo Kim
  • Publication number: 20100187657
    Abstract: The disclosed invention provides a method for the fabrication of a bipolar transistor having a collector region comprised within a semiconductor body separated from an overlying base region by one or more isolation cavities (e.g., air gaps) filled with low permittivity gas. In particular, a multilayer base-collector dielectric film is deposited over the collector region. A base region is formed onto the multilayer dielectric film and is patterned to form one or more base connection regions. The multilayer dielectric film is selectively etched during a plurality of isotropic etch processes to allow for the formation of one or more isolation region between the base connection regions and the collector region, wherein the one or more isolation regions comprise cavities filled with a gas having a low dielectric constant (e.g., air). The resultant bipolar transistor has a reduced base-collector capacitance, thereby allowing for improved frequency properties (e.g., higher maximum frequency operation).
    Type: Application
    Filed: December 18, 2009
    Publication date: July 29, 2010
    Applicant: Infineon Technologies AG
    Inventors: Josef Boeck, Wolfgang Liebl, Thomas Meister, Herbert Schaefer
  • Patent number: 7663166
    Abstract: Provided are relatively higher-performance wire-type semiconductor devices and relatively economical methods of fabricating the same. A wire-type semiconductor device may include at least one pair of support pillars protruding above a semiconductor substrate, at least one fin protruding above the semiconductor substrate and having ends connected to the at least one pair of support pillars, at least one semiconductor wire having ends connected to the at least one pair of support pillars and being separated from the at least one fin, a common gate electrode surrounding the surface of the at least one semiconductor wire, and a gate insulating layer between the at least one semiconductor wire and the common gate electrode.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: February 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-Pil Kim, Yoon-Dong Park, Won-Joo Kim
  • Patent number: 7642169
    Abstract: Embodiments relate to a bipolar junction transistor and a method for manufacturing the same. An oxide pattern may be formed on a P type semiconductor substrate. A low-density N type collector area may be formed in the semiconductor substrate. First spacers may be formed at sidewalls of the oxide pattern, and a low-density P type base area may be formed in the semiconductor substrate. Second spacers may be formed on sidewalls of the first spacers. A high-density N type emitter area may be formed in the low-density P type base area between the second spacers, and a high-density N type collector area may be formed in the semiconductor substrate at an outside of the first spacers. The bipolar junction transistor may be realized through a self-aligned scheme using dual nitride spacers. A base width between the emitter area and the low-density collector area may be narrowed by the width of the second spacer.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: January 5, 2010
    Assignee: Dongbu HiTek, Ltd.
    Inventor: Kwang Young Ko
  • Patent number: 7579245
    Abstract: An MOS device includes first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A non-uniformly doped channel region of the first conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on the upper surface of the semiconductor layer. A first gate is formed on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region, and at least a second gate formed on the insulating layer above at least a portion of the channel region and between the first gate and the second source/drain region.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: August 25, 2009
    Assignee: Agere Systems Inc.
    Inventors: Muhammed Ayman Shibib, Shuming Xu
  • Patent number: 7572707
    Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a floor for a semiconductor device by utilizing a CMOS process. The method further includes providing a BiCMOS-like process on top of the floor to further fabricate the semiconductor device, wherein the BiCMOS-like process and the CMOS process provides the semiconductor device.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: August 11, 2009
    Assignee: Micrel, Inc.
    Inventor: Schyi-yi Wu
  • Publication number: 20090026542
    Abstract: An integrated circuit including a semiconductor assembly in thin-film SOI technology is disclosed. One embodiment provides a semiconductor assembly in thin-film SOI technology including a first semiconductor substrate structure of a second conductivity type inverse to a first conductivity type in a semiconductor substrate below a first semiconductor layer, a second semiconductor substrate structure of a second conductivity type in a semiconductor substrate below a second semiconductor layer structure, and a third semiconductor substrate structure of the first conductivity type below the first semiconductor layer structure in the semiconductor substrate and otherwise surrounded by the first semiconductor substrate structure.
    Type: Application
    Filed: July 27, 2007
    Publication date: January 29, 2009
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Uwe Wahl
  • Patent number: 7482238
    Abstract: A method for manufacturing a semiconductor device includes steps of injecting a hole current into an N drift region while a constant voltage is applied to a P+ anode of a lateral insulated gate bipolar transistor, such that a majority of the hole current passes through a P+ cathode of the lateral insulated gate bipolar transistor via a P+ buried layer. Therefore, a hole-current path located under an N+ cathode area of a LIGBT structure is eliminated, thus securing sufficient latch-up current density.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: January 27, 2009
    Assignee: Dongbu Electronics, Co., Ltd.
    Inventor: Woong Je Sung
  • Patent number: 7462547
    Abstract: A method is provided for fabricating a bipolar transistor that includes growing an epitaxial layer onto an underlaying region having a low dopant concentration and a trench isolation region defining the edges of an active region layer, implanting a portion of the epitaxial layer through a mask to define a collector region having a relatively high dopant concentration, the collector region laterally adjoining a second region of the epitaxial layer having the low dopant concentration; forming an intrinsic base layer overlying the collector region and the second region, the intrinsic base layer including an epitaxial region in conductive communication with the collector region; forming a low-capacitance region laterally separated from the collector region by the second region, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer; and forming an emitter layer overlying the intrinsic base layer.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: December 9, 2008
    Assignee: International Business Machines Corporation
    Inventors: Hiroyuki Akatsu, Rama Divakaruni, Marwan Khater, Christopher M. Schnabel, William Tonti
  • Patent number: 7446012
    Abstract: The present invention relates to a lateral PNP transistor and the method of manufacturing the same. The medium doping N-type base area and the light doping P? collector area were first introduced in the structure before the formation of P+ doping emitter area and the collector area. The emitter-base-collector doping profile in the lateral and the base width of LPNP were similar to NPN. The designer can optimize the doping profile and area size of each area according to the request of the current gain (Hfe), collector-base breakdown voltage (BVceo), and early voltage (VA) of LPNP transistor. These advantages may cause to reduce the area and enhance performance of the LPNP transistor.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: November 4, 2008
    Assignee: BCD Semiconductor Manufacturing Limited
    Inventors: Chong Ren, Xian-Feng Liu, Bin Qiu
  • Patent number: 7422952
    Abstract: A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting during an electrostatic discharge (ESD) pulse.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: September 9, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper, Yuri Mirgorodski