Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.

Abstract: A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a non-uniform cathode region (104) and peripheral anode regions (106, 107) which define vertical and horizontal p-n junctions under the anode contact regions (130, 132), including a horizontal cathode/anode junction that is shielded by the heavily doped anode contact region (132).

Abstract: A semiconductor device manufacturing method includes (a) forming a buried diffusion layer of a first conductivity type in a semiconductor substrate of a second conductivity type, (b) forming a first impurity region by implanting an impurity of the first conductivity type, (c) diffusing the buried diffusion layer and the first impurity region to an extent that the buried diffusion layer and the first impurity region are not connected by performing a first thermal process on the semiconductor substrate, (d) forming a second impurity region by implanting an impurity of the first conductivity type at a concentration higher than that of in step (b), and (e) diffusing the buried diffusion layer, the first impurity region, and the second impurity region by performing a second thermal process on the semiconductor substrate.

Abstract: A thin film diode (100A) includes a semiconductor layer (130) having first, second, and third semiconductor regions, a first insulating layer (122) formed on the semiconductor layer (130), and a second insulating layer (123) formed on the first insulating layer (122). The first semiconductor region (134A) contains an impurity of a first-conductivity type at a first concentration; the second semiconductor region (135A) contains an impurity of a second-conductivity type different from the first conductivity type at a second concentration; and the third semiconductor region (133A) contains the first-conductivity type impurity at a third concentration lower than the first concentration, or contains the second-conductivity type impurity at a third concentration lower than the second concentration. The first semiconductor region (134A) conforms to an aperture pattern in the second insulating layer (123), or the second semiconductor region (135A) conforms to an aperture pattern in the second insulating layer (123).

Abstract: A method for producing a protective structure may include: providing a semiconductor base substrate with a doping of a first conductivity type; producing a first epitaxial layer on the substrate; implanting a dopant of a second conductivity type in a delimited implantation region of the first epitaxial layer; applying a second epitaxial layer with a doping of the second conductivity type on the first epitaxial layer; forming an insulation zone in the second epitaxial layer, such that the second epitaxial layer is subdivided into first and second regions; producing a first dopant zone with a doping of the first conductivity type in the first region above the implantation region; producing a second dopant zone with a doping of the second conductivity type in the second region; outdiffusing the dopant from the implantation region to form a buried layer at the junction between the first epitaxial layer and the first region.

Abstract: Aspects of the present invention relate to an approach for implanting and forming a polysilicon resistor with a single implant dose. Specifically, a mask having a set of openings is formed over a resistor surface. The set of openings are typically formed in a column-row arrangement according to a predetermined pattern. Forming the mask in this manner allows the resistor surface to have multiple regions/zones. A first region is defined by the set of openings in the mask, and a second region is defined by the remaining portions of the mask. The resistor is then subjected to a single implant dose via the openings. Implanting the resistor in this manner allows the resistor to have multiple resistance values (i.e., a first resistance value in the first region, and a second resistance value in the second region).

Abstract: The present invention provides a method for manufacturing a deep-trench super PN junction. The method includes: a deposition step for forming an epitaxial layer on a substrate; forming a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer; forming deep trenches in the epitaxial layer; completely filling the deep trenches with an epitaxial material and the epitaxial material is beyond the second dielectric layer; filling the entire surface of the second dielectric layer and the epitaxial layer such as Si using a third dielectric to from a surface filling layer with a predetermined height; etching back on the surface filling layer to the interface of the first dielectric layer and the epitaxial layer; and a removing step for removing the first dielectric layer, the second dielectric layer and the surface filling layer to planarize Si epitaxial material.

Abstract: An integrated circuit having a substrate with a first conductivity type of semiconductor material. A buried layer is formed in the substrate. The buried layer has a second conductivity type of semiconductor material. A first semiconductor layer is formed over the buried layer. The first semiconductor layer has the second conductivity type of semiconductor material. A trench is formed through the first semiconductor layer and buried layer and extends into the substrate. The trench is lined with an insulating layer and filled with an insulating material. A second semiconductor layer is formed in the first semiconductor layer. The second semiconductor layer has the first conductivity type of semiconductor material. A third semiconductor layer is formed in the second semiconductor layer. The third semiconductor layer has the second conductivity type of semiconductor material. The first, second, and third semiconductor layers form the collector, base, and emitter of a bipolar transistor.

Abstract: A power semiconductor device includes: a first semiconductor layer; second and third semiconductor layers above and alternatively arranged along a direction parallel to an upper surface of the first semiconductor layer; and plural fourth semiconductor layers provided on some of immediately upper regions of the third semiconductor layer. An array period of the fourth semiconductor layers is larger than that of the second semiconductor layer. A thickness of part of the gate insulating film in an immediate upper region of a central portion between the fourth semiconductor layers is thicker than a thickness of part of the gate insulating film in an immediate upper region of the fourth semiconductor layers. Sheet impurity concentrations of the second and third semiconductor layers in the central portion are higher than a sheet impurity concentration of the third semiconductor layer in an immediately lower region of the fourth semiconductor layers.

Abstract: A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation.

Abstract: A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation.

Abstract: Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer.

Abstract: To provide a semiconductor device in which an interval between first wells can be shortened by improving a separation breakdown voltage between the first wells and a method for manufacturing the same.

Abstract: An n-type isolation structure is disclosed which includes an n-type BISO layer in combination with a shallow n-well, in an IC. The n-type BISO layer is formed by implanting n-type dopants into a p-type IC substrate in addition to a conventional n-type buried layer (NBL), prior to growth of a p-type epitaxial layer. The n-type dopants in the BISO implanted layer diffuse upward from the p-type substrate to between one-third and two-thirds of the thickness of the p-type epitaxial layer. The shallow n-type well extends from a top surface of the p-type epitaxial layer to the n-type BISO layer, forming a continuous n-type isolation structure from the top surface of the p-type epitaxial layer to the p-type substrate. The width of the n-type BISO layer may be less than the thickness of the epitaxial layer, and may be used alone or with the NBL to isolate components in the IC.

Abstract: A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation.

Abstract: Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer.

Abstract: A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

Abstract: A semiconductor having a an n-type material and a p-type material, wherein the n-type material and p-type material are joined to form a space-charge-free p-n junction. The energy of the Fermi-level of the n-type material is equal to the energy of the Fermi-level of the p-type material. This allows for the pre-alignment of the Fermi-levels of the n-type and the p-type materials. The semiconductor has minimal or no g-r noise. The semiconductor can be operated at TBLIP in the range of about 220° to about 240° K.

Abstract: A semiconductor device is provided. The semiconductor device in which a field effect transistor utilizing a heterojunction is formed in a device formation region sectioned by a device separation region of a substrate comprising a semiconductor layer laminated while including a semiconductor layer having a heterojunction on a semiconductor substrate. The device separation region is composed of a layer in which a conductive impurity is introduced, and an electrode to which a positive voltage is to be applied is formed on the device separation region, specifically on the surface of at least a part of the device separation region in the periphery of the field effect transistor.

Abstract: Embodiments relate to a Complementary Metal Oxide Semiconductor (CMOS) image sensor, and to a method for manufacturing the same, that improves the low-light level characteristics of the CMOS image sensor. The CMOS image sensor has a photosensor unit and a signal processing unit, and may include a semiconductor substrate having a device isolating implant area provided with a first ion implant area and a complementary second ion implant area within the first ion implant area; a device isolating layer in the signal processing unit; a photodiode in the photosensor unit; and transistors in the signal processing unit. A crystal defect zone neighboring the photodiode may be minimized using the device isolating implant area between adjacent photodiodes so that a source of dark current can be reduced and the occurrence of interface traps can be prevented, making it possible to improve the low-light level characteristics of the image sensor.

Abstract: An n-type isolation structure is disclosed which includes an n-type BISO layer in combination with a shallow n-well, in an IC. The n-type BISO layer is formed by implanting n-type dopants into a p-type IC substrate in addition to a conventional n-type buried layer (NBL), prior to growth of a p-type epitaxial layer. The n-type dopants in the BISO implanted layer diffuse upward from the p-type substrate to between one-third and two-thirds of the thickness of the p-type epitaxial layer. The shallow n-type well extends from a top surface of the p-type epitaxial layer to the n-type BISO layer, forming a continuous n-type isolation structure from the top surface of the p-type epitaxial layer to the p-type substrate. The width of the n-type BISO layer may be less than the thickness of the epitaxial layer, and may be used alone or with the NBL to isolate components in the IC.

Abstract: Provided is a power semiconductor device including a guard ring region to protect control devices. The power semiconductor device includes a semiconductor body layer extending over a semiconductor substrate of a first conductivity type. The semiconductor body layer has a second conductivity type opposite the first conductivity type. A well of the first conductivity type extends in the semiconductor body layer and is configured to be electrically insulated from the semiconductor substrate. At least one control device is formed in the well, where the control device comprises at least one of PN junction. A guard ring region of the first conductivity type is laterally spaced from but surrounds the well. The guard ring region together with the semiconductor substrate and the semiconductor body layer form a parasitic bipolar transistor, and the guard ring region functions as a collector of the parasitic bipolar transistor.

Abstract: A method of a fabricating a multiple wavelength adapted photodiode and resulting photodiode includes the steps of providing a substrate having a first semiconductor type surface region on at least a portion thereof, implanting and forming a second semiconductor type shallow surface layer into the surface region, and forming a multi-layer anti-reflective coating (ARC) on the shallow surface layer. The forming step includes depositing or forming a thin oxide layer on the shallow surface layer and depositing a second dielectric layer different from the thin oxide layer on the thin oxide layer. An etch stop is formed on the second dielectric, wherein the etch stop includes at least one layer resistant to oxide etch. At least one oxide including layer (e.g. ILD) is then deposited on the etch stop. The oxide including layer and etch stop are then removed to expose at least a portion of the ARC to the ambient.

Abstract: A method of making an energy conversion device includes forming a plurality of pores within a substrate and forming a junction region within each of the plurality of pores. Each of the junction regions has a depletion region and each of the plurality of pores defines an opening size in the substrate and a spacing from adjacent pores so that the depletion regions of each of the pores is at least substantially in contact with the depletion region of the pores which are adjacent.

Abstract: The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Vss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device and its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

Abstract: A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so as to protrude from a surface opposite to a semiconductor substrate 1 toward a main surface of the semiconductor substrate 1 in the base extraction electrode 5B, and protruded length thereof is set to be equal to or smaller than one half of thickness of the insulation film 4 interposed between the main surface of the semiconductor substrate 1 and a lower surface of the base extraction electrode 5B.

Abstract: The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first plug region disposed in the uniform base region, a p-type first emitter region and a first collector region disposed in and at the top surface of the uniform base region, a graded base region disposed in the uniform base region and a first base contact region disposed in the first plug region. The graded base region encloses the bottom and the side of the first main electrode region. The doping profile in the graded base region intervening between the first emitter region and the first collector region is such that the impurity concentration is gradually decreases towards the second main electrode region from the first main electrode region.

Abstract: The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.

Abstract: The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first plug region disposed in the uniform base region, a p-type first emitter region and a first collector region disposed in and at the top surface of the uniform base region, a graded base region disposed in the uniform base region and a first base contact region disposed in the first plug region. The graded base region encloses the bottom and the side of the first main electrode region. The doping profile in the graded base region intervening between the first emitter region and the first collector region is such that the impurity concentration is gradually decreases towards the second main electrode region from the first main electrode region.

Abstract: A Si1-xGex layer 111b functioning as the base composed of an i—Si1-xGex layer and a p+ Si1-xGex layer is formed on a collector layer 102, and a Si cap layer 111a as the emitter is formed on the p+ Si1-xGex layer. An emitter lead electrode 129, which is composed of an n? polysilicon layer 129b containing phosphorus in a concentration equal to or lower than the solid-solubility limit for single-crystal silicon and a n+ polysilicon layer 129a containing phosphorus in a high concentration, is formed on the Si cap layer 111a in a base opening 118. The impurity concentration distribution in the base layer is properly maintained by suppressing the Si cap layer 111a from being doped with phosphorus (P) in an excessively high concentration. The upper portion of the Si cap layer 111a may contain a p-type impurity. The p-type impurity concentration distribution in the base layer of an NPN bipolar transistor is thus properly maintained.

Abstract: A method of making a bi-directional transient voltage suppression device is provided, which comprises: (a) providing a p-type semiconductor substrate; (b) epitaxially depositing a lower semiconductor layer of p-type conductivity; (c) epitaxially depositing a middle semiconductor layer of n-type conductivity over the lower layer; (d) epitaxially depositing an upper semiconductor layer of p-type conductivity over the middle layer; (e) heating the substrate, the lower epitaxial layer, the middle epitaxial layer and the upper epitaxial layer; (f) etching a mesa trench that extends through the upper layer, through the middle layer and through at least a portion of the lower layer, such that the mesa trench defines an active area for the device; and (g) thermally growing an oxide layer on at least those portions of the walls of the mesa trench that correspond to the upper and lower junctions of the device.

Abstract: A method of forming minimally spaced word lines is disclosed. A double exposure technique is employed at the gate formation level. A small trench is defined through gate stack layers by using a tapered etch or spacers to achieve the desired width of the trench. A filler material fills the trench and forms a filler plug. The gate layers adjacent to the trench are then patterned and etched and the filler plug is removed to obtain gate stacks spaced apart by a distance of less than about 400 Angstroms.

Abstract: A device and a method are provided for isolating a circuit well from a substrate of the same conductivity type. In particular, an integrated circuit is provided which includes a circuit well arranged over a semiconductor substrate with no layer of opposite conductivity type arranged between the well and the substrate. The integrated circuit may further include a pair of isolation wells extending along opposite lateral boundaries of the circuit well. The isolation wells and circuit well may be adapted such that a single continuous depletion region underlying the circuit well may be formed upon application of an isolation voltage between the substrate and the pair of isolation wells. The formation of such a depletion region may beneficially isolate the circuit well from the underlying substrate.

Abstract: The device is constituted by an N+ substrate, by an N− layer on the substrate, by a metal contact for a collector, by a buried P− base region, by a P+ base contact and insulation region within which an insulated N region is defined, by a metal contact on the base contact region for a base, by an N+ emitter region buried in the insulated region and forming a pn junction with the buried base region, by a P+ body region in the insulated region, by an N+ source region in the P+ region, by a metal contact for a source, and by a gate electrode. In order to achieve a low resistance Ron, the P+ body region extends as far as the buried N+ emitter region and an additional N+ region is provided within the body region and constitutes a drain region, defining, with the source region, the channel of a lateral MOSFET transistor.

Abstract: The thermal resistance Rth parameter is determined for a field effect transistor formed with a semiconductor film on a buried insulating material in SOI (semiconductor on insulator) technology. A p-n junction is formed with one of a drain region or a source region of the field effect transistor. The p-n junction is biased at a bias voltage. The p-n junction is heated to a plurality of temperatures. A current conducted through the p-n junction is measured at each of the plurality of temperatures of the p-n junction to generate a current versus temperature characteristic for the p-n junction. A respective current flowing through the p-n junction is measured as the field effect transistor is biased to dissipate each of a plurality of power dissipation levels and with the p-n junction being biased at the bias voltage.

Abstract: A bipolar transistor is vertically isolated from underlying silicon by an isolation layer of conductivity type opposite that of the collector. This isolation layer lies beneath the heavily doped buried layer portion of the collector, and is formed either by ion implantation prior to epitaxial growth of well regions, or by high energy ion implantation into the substrate prior to formation of the well and the heavily doped buried collector layer. Utilization of trench lateral isolation extending into the semiconductor material beyond the isolation layer permits blanket implant of the isolation layer, obviating the need for an additional masking step.

Abstract: A semiconductor device comprises an n-conductive type Si substrate, a n-conductive type Si film formed on the n-conductive type Si substrate, a p-conductive type SiGe film formed on the n-conductive type Si film, a p-conductive type Si film formed on the p-conductive type SiGe film, a n-conductive type Si film formed on the p-conductive type Si film, a base electrode formed by removing a part of the n-conductive type Si film or changing the conductive type of a part of the n-conductive type Si film to a p-conductive type, and joining a metal terminal to a part of the p-conductive type Si film exposed by removing the N-type Si film or to the part of the n-conductive type Si film whose conductive type is changed to a p-conductive type, an emitter electrode formed by joining a metal terminal to the n-conductive type Si film, and a collector electrode formed by joining a metal terminal to a back surface of the n-conductive type Si substrate.

Abstract: A bipolar transistor is vertically isolated from underlying silicon by an isolation layer of conductivity type opposite that of the collector. This isolation layer lies beneath the heavily doped buried layer portion of the collector, and is formed either by ion implantation prior to epitaxial growth of well regions, or by high energy ion implantation into the substrate prior to formation of the well and the heavily doped buried collector layer. Utilization of trench lateral isolation extending into the semiconductor material beyond the isolation layer permits blanket implant of the isolation layer, obviating the need for an additional masking step.

Abstract: A bipolar transistor is described whose I-V curve is such that it operates in two regions, one having low gain and low power consumption and another having higher gain and better current driving ability. Said transistor has a base region made up of two sub regions, the region closest to the emitter having a resistivity about an order a magnitude lower than the second region (which interfaces with the collector). A key feature of the invention is that the region closest to the collector is very uniformly doped, i.e. there is no gradient or built-in field present. In order to produce such a region, epitaxial growth along with boron doping is used rather than more conventional techniques such as ion implantation and/or diffusion.

Abstract: The inventive method provides improved semiconductor devices, such as MOSFET's with raised source/drain extensions on a substrate with isolation trenches etched into the surface of the substrate. The inventive method provides thin first dielectric spacers on the side of a gate and gate oxide and extend from the top of the gate to the surface of the substrate. Raised source/drain extensions are placed on the surface of a substrate, which extend from the first dielectric spacers to the isolation trenches. Thicker second dielectric spacers are placed adjacent to the first dielectric spacers and extend from the top of the first dielectric spacers to the raised source/drain extensions. Raised source/drain regions are placed on the raised source/drain extensions, and extend from the isolation trenches to the second dielectric spacers. The inventive semiconductor devices provide for very shallow source drain extensions which results in a reduced short channel effect.

Abstract: A thin silicon epitaxial layer, formed on a silicon substrate, is subdivided into electrically isolated pockets by a grid of oxidized regions of epitaxial silicon material which extend through the epitaxial layer to a laterally extending PN junction.

Abstract: A semiconductor circuit includes a semiconductor layer having a surface and a monolithic output stage formed in the semiconductor layer. The monolithic output stage extends to the surface of the semiconductor layer and has a periphery within the semiconductor layer, an output terminal, and a supply terminal. A barrier well is formed in the semiconductor layer and adjacent to at least a portion of the periphery of the monolithic output stage. The barrier well extends to the surface of the semiconductor layer and has a first conductivity. A diode having first and second diode regions is disposed in the semiconductor layer. The first diode region is coupled to the supply terminal. The diode is operable to prevent current flow from the barrier well to the supply terminal when the voltage between the supply and output terminals has a first polarity.

Abstract: An integrated edge structure for a high voltage semiconductor device comprising a PN junction represented by a diffused region of a first conductivity type extending from a semiconductor device top surface is described. The edge structure comprises a first, lightly doped ring of the first conductivity type obtained in a first, lightly doped epitaxial layer of a second conductivity type and surrounding said diffused region, and a second, lightly doped ring of the first conductivity type, comprising at least one portion superimposed on and merged with said first ring, obtained in a second, lightly doped epitaxial layer of the second conductivity type grown over the first epitaxial layer.

Abstract: A process for doping a P-type substrate (50) by forming a layer (52) of silicon nitride, implanting N-type impurities through this layer (FIG. 7), forming a resist mask (54) which leaves at least one area of the substrate (FIG. 8) containing a part of the nitride layer exposed, implanting N-type impurities first with an insufficient energy and then with a sufficient energy to traverse the nitride layer, subjecting (FIG. 9) the substrate to a high temperature treatment in an oxidizing environment to form silicon dioxide pads (55) on the areas of the substrate not covered by the nitride layer, removing the nitride layer and performing an implantation of P-type impurities into the areas delimited by the pads. The process then continues with the removal of the pads and, in the conventional manner, with the formation of an epitaxial layer and selective doping of this to form P-type and N-type regions in it.

Abstract: Integrated structure bipolar transistors with controlled storage time are manufactured by forming at least one bipolar transistor occupying a first area on a first surface of the silicon material, covering the first surface of the silicon material with an insulating material layer, and selectively removing the insulating material layer to open a window. The window has a second area much smaller than the first area occupied by the bipolar transistor. Therefore, by implanting into the silicon material a medium dose of platinum ions through the window and diffusing into the silicon material the implanted platinum ions, a uniform distribution of platinum inside the transistor is obtained.