Abstract: A method to fabricate a transistor, the method comprising: implanting dopants in a semiconductor to form a collector region having majority carriers of a first type; implanting dopants with a first dosage and implanting dopants with a second dosage in the collector region to form a base region having majority carriers of a second type, wherein the second dosage is at a lower energy than the first dosage; forming a gate oxide on the base region; forming a gate material on the gate oxide; forming the gate material and the gate oxide to leave uncovered an emitter area of the base region; and implanting dopants in the emitter area to form an emitter region having majority carriers of the first type.

Abstract: Methods of fabricating a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes epitaxially growing a source/drain structure covering the fin structure. In addition, the method includes epitaxially growing a capping layer over the source/drain structure. The capping layer has a top portion and a lower portion under the top portion. The top portion has a first thickness and the lower portion has a second. A ratio of the first thickness to the second thickness is in a range of about 1.01 to about 2. The method also includes etching the top portion and the lower portion of the capping layer. The method further includes forming a silicide layer over the source/drain structure and a contact over the silicide layer.

Abstract: A laminated magnetic core, which has a number of magnetic layers and a number of insulation layers which are arranged so that an insulation layer lies between each vertically adjacent pair of magnetic layers, is formed in a method that forms the magnetic layers with an electroplating process, and the insulation layers with a sputter depositing process.

Abstract: Methods for forming a layer of semiconductor material and a semiconductor-on-insulator structure are provided. A substrate including one or more devices or features formed therein is provided. A seed layer is bonded to the substrate, where the seed layer includes a crystalline semiconductor structure. A first portion of the seed layer that is adjacent to an interface between the seed layer and the substrate is amorphized. A second portion of the seed layer that is not adjacent to the interface is not amorphized and maintains the crystalline semiconductor structure. Dopant implantation is performed to form an N-type conductivity region or a P-type conductivity region in the first portion of the seed layer. A solid-phase epitaxial growth process is performed to crystallize the first portion of the seed layer. The SPE growth process uses the crystalline semiconductor structure of the second portion of the seed layer as a crystal template.

Abstract: The invention provides a method for fabricating a CMOS transistor and a method for fabricating an array substrate. The method for fabricating a CMOS transistor comprises a step of forming channels, which comprises: depositing an amorphous silicon layer on a substrate, and crystallizing the amorphous silicon layer into a poly-silicon layer; implanting boron atoms into the poly-silicon layer and then forming an N channel region and a P channel region by etching the poly-silicon layer implanted with the boron atoms; forming a photoresist-partially-retained region corresponding to the N channel region and a photoresist-completely-retained region corresponding to the P channel region through a single patterning process; and removing the photoresist in the photoresist-partially-retained-region and retaining a part of the photoresist in the photoresist-completely-retained region using an ashing process, implanting phosphorus atoms through ion implantation thereby forming an N channel and a P channel.

Abstract: A lateral bipolar transistor with deep emitter and deep collector regions is formed using multiple epitaxial layers of the same conductivity type. Deep emitter and deep collector regions are formed without the use of trenches. Vertically aligned diffusion regions are formed in each epitaxial layer so that the diffusion regions merged into a contiguous diffusion region after annealing to function as emitter or collector or isolation structures. In another embodiment, a lateral trench PNP bipolar transistor is formed using trench emitter and trench collector regions. In yet another embodiment, a lateral PNP bipolar transistor with a merged LDMOS transistor is formed to achieve high performance.

Abstract: Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming a dielectric material on a substrate. The method further includes forming a shallow trench structure and deep trench structure within the dielectric material. The method further includes forming a material within the shallow trench structure and deep trench structure. The method further includes forming active areas of the material separated by shallow trench isolation structures. The shallow trench isolation structures are formed by: removing the material from within the deep trench structure and portions of the shallow trench structure to form trenches; and depositing an insulator material within the trenches.

Abstract: An integrated circuit having a substrate with a first conductivity type of semiconductor material. A buried layer is formed in the substrate. The buried layer has a second conductivity type of semiconductor material. A first semiconductor layer is formed over the buried layer. The first semiconductor layer has the second conductivity type of semiconductor material. A trench is formed through the first semiconductor layer and buried layer and extends into the substrate. The trench is lined with an insulating layer and filled with an insulating material. A second semiconductor layer is formed in the first semiconductor layer. The second semiconductor layer has the first conductivity type of semiconductor material. A third semiconductor layer is formed in the second semiconductor layer. The third semiconductor layer has the second conductivity type of semiconductor material. The first, second, and third semiconductor layers form the collector, base, and emitter of a bipolar transistor.

Abstract: Disclosed are a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a narrow in-substrate collector region for reduced base-collector junction capacitance. The transistor has, within a substrate, a collector region positioned laterally adjacent to a trench isolation region. A relatively thin seed layer covers the trench isolation region and collector region. This seed layer has a monocrystalline center, which is aligned above and wider than the collector region (e.g., due to a solid phase epitaxy regrowth process), and a polycrystalline outer section. An intrinsic base layer is epitaxially deposited on the seed layer such that it similarly has a monocrystalline center section that is aligned above and wider than the collector region. An extrinsic base layer is the intrinsic base layer and has a monocrystalline extrinsic base-to-intrinsic base link-up region that is offset vertically from the collector region.

Abstract: In accordance with an embodiment, a semiconductor device includes a functional film, first and second trenches, and first and second insulating films. The functional film comprises first and second areas. The first trench is provided in the first area of the functional film and has a first width. The second trench is provided in the second area of the functional film and has a second width larger than the first width. The first insulating film is formed from a polymeric material as a precursor to fill the first trench. The second insulating film has a diameter larger than the first width and is formed from particulates and the polymeric material as precursors. The particulates fill the second trench. The polymeric material fills spaces between the particulates in the second trench and also fills gaps between the particulates and the second trench.

Abstract: Bipolar junction transistors are provided in which at least one of an emitter contact, a base contact, or a collector contact thereof is formed by epitaxially growing a doped SixGe1-x layer, wherein x is 0?x?1, at a temperature of less than 500° C. The doped SixGe1-x layer comprises crystalline portions located on exposed surfaces of a crystalline semiconductor substrate and non-crystalline portions that are located on exposed surfaces of a passivation layer which can be formed and patterned on the crystalline semiconductor substrate. The doped SixGe1-x layer of the present disclosure, including the non-crystalline and crystalline portions, contains from 5 atomic percent to 40 atomic percent hydrogen.

Abstract: Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.

Abstract: An ESD protection device is described, which includes a P-body region, a P-type doped region, an N-type doped region and an N-sinker region. The P-body region is configured in a substrate. The P-type doped region is configured in the middle of the P-body region. The N-type doped region is configured in the P-body region and surrounds the P-type doped region. The N-sinker region is configured in the substrate and surrounds the P-body region.

Abstract: In one embodiment, a semiconductor device is formed having vertical localized charge-compensated trenches, trench control regions, and sub-surface doped layers. The vertical localized charge-compensated trenches include at least a pair of opposite conductivity type semiconductor layers. The trench control regions are configured to provide a generally vertical channel region electrically coupling source regions to the sub-surface doped layers. The sub-surface doped layers are further configured to electrically connect the drain-end of the channel to the vertical localized charge compensation trenches. Body regions are configured to isolate the sub-surface doped layers from the surface of the device.

Abstract: An annular step portion provided to a periphery of a wafer housing portion is provided to an area with which an area of 1 to 6 mm from a boundary line with a chamfered surface of a wafer rear surface toward a wafer center comes in contact. As a result, it is possible to produce an epitaxial wafer having no scratch in a boundary area between the rear surface and the chamfered surface, and to eliminate particles generated due to a scratch in a device process.

Abstract: In sophisticated transistor elements, long-term threshold voltage shifts in transistors comprising a threshold adjusting semiconductor alloy may be reduced by reducing the roughness of an interface formed between the threshold adjusting semiconductor material and the gate dielectric material. To this end, a portion of the threshold adjusting semiconductor material may be oxidized and may be removed prior to forming the high-k dielectric material.

Abstract: Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties.

Abstract: The present invention relates to a semiconductor device which is capable of simultaneously improving a short channel effect of a PMOS and the current of an NMOS and a method for manufacturing the same. The semiconductor device includes first and second gates formed over first and second areas of a semiconductor substrate, respectively; and first and second junction areas formed in a portion of the semiconductor substrate corresponding to both sides of the first gate and a portion of the semiconductor substrate corresponding to both sides of the second gate, and including a projection, respectively, wherein the projection of the first junction area has a height higher than the height of the projection of the second junction area, and the second junction area is formed such that it has a depth from the surface of the semiconductor substrate deeper than the depth of the first junction area.

Abstract: Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties.

Abstract: A system and a method are disclosed for manufacturing double epitaxial layer N-type lateral diffusion metal oxide semiconductor transistors. In one embodiment two N-type buried layers are used to minimize the operation of a parasitic PNP bipolar transistor. The use of two N-type buried layers increases the base width of the parasitic PNP bipolar transistor without significantly decreasing the peak doping profiles in the two N-type buried layers. In one embodiment two N-type buried layers and one P-type buried layer are used to form a protection NPN bipolar transistor that minimizes the operation of parasitic NPN bipolar transistor. The N-type lateral diffusion metal oxide semiconductor transistors of the invention are useful in inductive full load or half bridge converter circuits that drive very high current.

Abstract: A method for producing a semiconductor including a material layer. In one embodiment a trench is produced having two opposite sidewalls and a bottom, in a semiconductor body. A foreign material layer is produced on a first one of the two sidewalls of the trench. The trench is filled by epitaxially depositing a semiconductor material onto the second one of the two sidewalls and the bottom of the trench.

Abstract: A technique for altering or repairing the operating state of a semiconductor device comprises field-controlled diffusion of mobile dopant atoms within the metal oxide crystal lattice. When heated (e.g., above 550 K) in the presence of an electric field (e.g., bias to ground of +/?50 V) the dopant atoms are caused to collect to form an ohmic contact, leaving a depletion region. Metal-semiconductor junction devices such as diodes, photo-diodes, photo-detectors, MESFETs, etc. may thereby be fabricated, repaired or modified.

Abstract: A technique for creating high quality Schottky barrier devices in doped (e.g., Li+) crystalline metal oxide (e.g., ZnO) comprises field-controlled diffusion of mobile dopant atoms within the metal oxide crystal lattice. When heated (e.g., above 550 K) in the presence of an electric field (e.g., bias to ground of +/?50 V) the dopant atoms are caused to collect to form an ohmic contact, leaving a depletion region. The size of the depletion region controls the thickness of the Schottky barrier. Metal-semiconductor junction devices such as diodes, photo-diodes, photo-detectors, MESFETs, etc. may thereby be fabricated.

Abstract: The invention relates to a method of manufacturing a bipolar transistor on a semiconductor substrate (11) which is provided with a first, a second and a third layer (1,2,3) of a first, second and third semiconductor material respectively, all of a first conductivity type. A first portion of the second layer (2) is transformed into a buried isolation region (15) comprising a first electrically insulating material. A first semiconductor region (6) of the first conductivity type, comprising, for example, a collector region, is formed from a second portion of the second layer (2) adjoining the buried isolation region (15) and a portion of the first layer (1) adjoining the second portion of the second layer (2). Then a base region (7) is formed on the buried isolation region (15) and on the first semiconductor region (6) by transforming the third layer (3) into a second conductivity type, which is opposite to the first conductivity type.

Abstract: There is disclosed a method for producing an epitaxial wafer with a buried diffusion layer comprising: implanting an impurity into a silicon single crystal wafer; subsequently diffusing the impurity in the wafer to form a diffusion layer; at least removing an oxide film on the diffusion layer; and thereafter forming a silicon epitaxial layer over the wafer to produce a silicon epitaxial wafer with a buried diffusion layer; wherein at least the oxide film on the diffusion layer is removed by etching with hydrofluoric acid to which a surfactant is added, and then the silicon epitaxial layer is formed. There can be provided a method for producing an epitaxial wafer with a buried diffusion layer in which generation of crystal defects in a silicon epitaxial layer is reduced effectively and an epitaxial wafer with a buried diffusion layer.

Abstract: A method of fabricating an integrated BiCMOS circuit is provided, the circuit including bipolar transistors 10 and CMOS transistors 12 on a substrate. The method comprises the step of forming an epitaxial layer 28 to form a channel region of a MOS transistor and a base region of a bipolar transistor. Growing of the epitaxial layer includes growing a first sublayer of silicon 28a, a first sublayer of silicon-germanium 28b onto the first sublayer of silicon, a second sublayer of silicon 28c onto the first sublayer of silicon-germanium, and a second sublayer of silicon-germanium 28d onto the second sublayer of silicon. Furthermore, an integrated BiCMOS circuit is provided, which includes an epitaxial layer 28 as described above.

Abstract: A technique for creating high quality Schottky barrier devices in doped (e.g., Li+) crystalline metal oxide (e.g., ZnO) comprises field-controlled diffusion of mobile dopant atoms within the metal oxide crystal lattice. When heated (e.g., above 550 K) in the presence of an electric field (e.g., bias to ground of +/?50 V) the dopant atoms are caused to collect to form an ohmic contact, leaving a depletion region. The size of the depletion region controls the thickness of the Schottky barrier. Metal-semiconductor junction devices such as diodes, photo-diodes, photo-detectors, MESFETs, etc. may thereby be fabricated.

Abstract: SiH3CH3 having the concentration of 1 to 10% is diluted with H2 and a portion of the diluted SiH3CH3, GeH4 and SiH4 (or DCS) are respectively supplied to a chamber of an epitaxial device at predetermined flow rates, and SiGe:C is formed by an epitaxial growth technique. By diluting the SiH3CH3, the concentration of oxygen-based impurity contained in the SiH3CH3 is reduced and hence, the oxygen-based impurity which is supplied to a chamber are reduced whereby the concentration of oxygen-based impurity contained in the SiGe:C formed in a film is reduced.

Abstract: A method of forming a field effect transistor comprises providing a semiconductor substrate, a gate electrode being formed over the semiconductor substrate. At least one cavity is formed adjacent the gate electrode. A strain-creating element is formed in the at least one cavity. The strain-creating element comprises a compound material comprising a first chemical element and a second chemical element. A first concentration ratio between a concentration of the first chemical element in a first portion of the strain-creating element and a concentration of the second chemical element in the first portion of the strain-creating element is different from a second concentration ratio between a concentration of the first chemical element in a second portion of the strain-creating element and a concentration of the second chemical element in the second strain-creating element.

Abstract: An electronic device contains a substrate, a sub-collector supported by the substrate, an un-doped layer having a selectively implanted buried sub-collector and supported by the sub-collector, an As-based nucleation layer partially supported by the un-doped layer, a collector layer supported by the As-based nucleation layer, a base layer supported by the collector layer, an emitter layer and a base contact supported by the base layer, an emitter cap layer supported by the emitter layer, an emitter contact supported by the emitter cap layer, and a collector contact supported by the sub-collector. A method provides for selecting a first InP layer, forming an As-based nucleation layer on the first InP layer, and epitaxially growing a second InP layer on the As-based nucleation layer.

Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a floor for a semiconductor device by utilizing a CMOS process. The method further includes providing a BiCMOS-like process on top of the floor to further fabricate the semiconductor device, wherein the BiCMOS-like process and the CMOS process provides the semiconductor device.

Abstract: An electronic device contains a substrate, a sub-collector supported by the substrate, an un-doped layer having a selectively implanted buried sub-collector and supported by the sub-collector, an As-based nucleation layer partially supported by the un-doped layer, a collector layer supported by the As-based nucleation layer, a base layer supported by the collector layer, an emitter layer and a base contact supported by the base layer, an emitter cap layer supported by the emitter layer, an emitter contact supported by the emitter cap layer, and a collector contact supported by the sub-collector. A method provides for selecting a first InP layer, forming an As-based nucleation layer on the first InP layer, and epitaxially growing a second InP layer on the As-based nucleation layer.

Abstract: An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.

Abstract: The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second gate on a substrate. Next, an oxide layer is formed on the first and second gates; and, a nitride layer is formed on the oxide layer. Portions of the nitride layer proximate the first gate, portions of the oxide layer proximate the first gate, and portions of the substrate proximate the first gate are removed so as to form source and drain recesses proximate the first gate. Following this, the method removes remaining portions of the nitride layer, including exposing remaining portions of the oxide layer. The removal of the remaining portions of the nitride layer only exposes the remaining portions of the oxide layer and the source and drain recesses.

Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

Abstract: Methods and apparatus are provided. A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug.

Abstract: An integrated circuit on a semiconductor chip is provided with a first bipolar transistor and a second bipolar transistor. The first bipolar transistor has a first collector region of a first conductivity type, grown by at least one epitaxial layer, and the second bipolar transistor has a second collector region of this first conductivity type grown by this epitaxial layer. The first collector region also has a first collector drift zone, and the second collector region has a second collector drift zone. Whereby, the first collector drift zone is shortened as compared to the second collector drift zone by partial etching of the epitaxial layer.

Abstract: A method for forming a feature in a layer with reduced line edge roughening is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A sidewall layer with a thickness less than 100 nm is formed over the sidewalls of the photoresist features by performing for a plurality of cycles. Each cycle comprises depositing a layer on the photoresist layer wherein the deposited layer has a thickness between a monolayer to 20 nm. Features are etched into the layer through the photoresist features. The photoresist layer and sidewall layer are stripped.

Abstract: A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer is formed on the first semiconductor layer and the substrate. Two gate electrodes are formed on the gate insulating layer such that the trench is located in between two gate electrodes. First and second impurity regions are formed in the substrate on both sides of each of the gate electrodes. Since the doped layer is locally formed in the trench area, the source and drain regions are completely separated from the heavily doped layer to weaken the electric field of PN junction, thereby improving refresh and preventing punchthrough between the source and drain.

Abstract: A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer is formed on the first semiconductor layer and the substrate. Two gate electrodes are formed on the gate insulating layer such that the trench is located in between two gate electrodes. First and second impurity regions are formed in the substrate on both sides of each of the gate electrodes. Since the doped layer is locally formed in the trench area, the source and drain regions are completely separated from the heavily doped layer to weaken the electric field of PN junction, thereby improving refresh and preventing punchthrough between the source and drain.

Abstract: This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.

Abstract: A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so as to protrude from a surface opposite to a semiconductor substrate 1 toward a main surface of the semiconductor substrate 1 in the base extraction electrode 5B, and protruded length thereof is set to be equal to or smaller than one half of thickness of the insulation film 4 interposed between the main surface of the semiconductor substrate 1 and a lower surface of the base extraction electrode 5B.

Abstract: The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first plug region disposed in the uniform base region, a p-type first emitter region and a first collector region disposed in and at the top surface of the uniform base region, a graded base region disposed in the uniform base region and a first base contact region disposed in the first plug region. The graded base region encloses the bottom and the side of the first main electrode region. The doping profile in the graded base region intervening between the first emitter region and the first collector region is such that the impurity concentration is gradually decreases towards the second main electrode region from the first main electrode region.

Abstract: In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component properties of the integrated silicon-germanium heterobipolar transistor.

Abstract: The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.

Abstract: In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substrate the first bipolar transistor has an N+-type first embedded diffusion layer having an impurity concentration higher than that of the epitaxial layer and the second bipolar transistor has an N-type second embedded diffusion layer having a lower impurity concentration and a deeper diffusion layer depth than the first embedded diffusion layer, whereby a high speed bipolar transistor and a high voltage bipolar transistor are formed on the same substrate.

Abstract: Semiconductor device fabrication methods include forming an oxide layer on a semiconductor substrate, forming an arrangement trench on the semiconductor substrate by patterning the oxide layer and the semiconductor substrate, forming a nitride layer on the arrangement trench and the oxide layer, forming a field trench on the semiconductor substrate by patterning the nitride layer, oxide layer, and the semiconductor substrate, and forming a pad oxide layer on inner walls of the field trench. The methods may also include removing the pad oxide layer on a bottom wall of the field trench, injecting ions into the bottom wall of the field trench so as to form an ion injected region, forming a buried layer by diffusing the ion injected region, and forming an epitaxial layer on the buried layer.

Abstract: The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first plug region disposed in the uniform base region, a p-type first emitter region and a first collector region disposed in and at the top surface of the uniform base region, a graded base region disposed in the uniform base region and a first base contact region disposed in the first plug region. The graded base region encloses the bottom and the side of the first main electrode region. The doping profile in the graded base region intervening between the first emitter region and the first collector region is such that the impurity concentration is gradually decreases towards the second main electrode region from the first main electrode region.

Abstract: A method of fabricating a semiconductor device according to the present invention includes a step A of forming a polycrystalline or amorphous preliminary semiconductor layer on a surface of a substrate so as to have an opening portion and a step B of simultaneously forming an epitaxial growth layer on an exposed portion of a surface of the substrate through the opening portion and a non-epitaxial growth layer on the preliminary semiconductor layer using a CVD method while heating the substrate inside a reaction chamber by means of a heat source inside the reaction chamber, the epitaxial growth layer being made of single crystalline semiconductor, and the non-epitaxial growth layer being comprised of a polycrystalline or amorphous semiconductor layer.

Abstract: In a semiconductor manufacturing method, an emitter region (211) and a base enhancement region (207) are formed to provide linear voltage, capacitance and low resistance characteristics. In the manufacturing method, a semiconductor device (200) is formed on a silicon substrate layer (101) with an epitaxial layer (203). Trenches (233) are cut into the epitaxial layer (203) and filled with oxide (601) to provide reduced junction capacitance and reduced base resistance. The emitter region (211) and the base enhancement region (207) are simultaneously formed through an anneal process.