Abstract: One illustrative device disclosed herein includes a semiconductor substrate and a bipolar junction transistor (BJT) device that comprises a collector region, a base region and an emitter region. In this example, the device also includes a field effect transistor and at least one base conductive contact structure that conductively and physically contacts the base region.

Abstract: According to an embodiment of the invention, a chip package is provided, which includes: a substrate having an upper surface and a lower surface; a hole extending from the upper surface toward the lower surface; an insulating layer located overlying a sidewall of the hole; and a material layer located overlying the sidewall of the hole, wherein the material layer is separated from the upper surface of the substrate by a distance and a thickness of the material layer decreases along a direction toward the lower surface.

Abstract: Embodiments of the present invention include a method for forming a semiconductor emitter and the resulting structure. The invention comprises forming an epitaxial base layer on a semiconductor substrate. A dielectric layer is deposited over the epitaxial base layer. An opening is etched in a portion of the dielectric layer exposing a portion of the epitaxial base layer and a spacer is deposited along the sidewall of the opening. The emitter is grown from the epitaxial base layer to overlap the top surface of the spacer and a portion of the dielectric layer. The single crystal emitter is formed without a mask and without the requirement of subsequent patterning processes.

Abstract: A shallow bipolar junction transistor comprising a high voltage n+ well implanted into a semiconductor substrate. The shallow bipolar junction transistor further comprises a bit line n+ implant (BNI) above the high voltage n+ well and an oxide nitride (ONO) layer above the high voltage n+ well. A portion of the ONO layer isolates the BNI from a shallow trench isolation (STI) region.

Abstract: A method and structure is directed to eDRAM cells with high-conductance electrodes. The method includes forming upper layers on a semiconductor substrate and forming an opening in the upper layers. The method further includes forming a trench in the semiconductor substrate, aligned with the opening. The method further includes forming a metal plate on all exposed surface in the trench by applying a metallic aqueous solution with an electrical bias to a backside of the semiconductor substrate.

Abstract: Disclosed herein is a nanowire including silicon rich oxide and a method for producing the same. The nanowire exhibits excellent electrically conducting properties and optical characteristics, and therefore is effectively used in a variety of applications including, for example, solar cells, sensors, photodetectors, light emitting diodes, laser diodes, EL devices, PL devices, CL devices, FETs, CTFs, surface plasmon waveguides, MOS capacitors and the like.

Abstract: A method for fabricating an integrated circuit comprising an electromigration barrier in a line of the integrated circuit includes forming a spacer; forming a segmented line adjacent to opposing sides of the spacer, the segmented line formed from a first conductive material; removing the spacer to form an empty line break; and filling the empty line break with a second conductive material to form an electromigration barrier that isolates electromigration effects within individual segments of the segmented line. An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.

Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including providing a single crystal substrate; forming an insulating layer on the single crystal substrate; forming a via through the insulating layer to provide an exposed portion of the single crystal substrate; forming amorphous Si on at least the exposed portion of the single crystal substrate; converting at least a portion of the amorphous Si into single crystal Si; and forming dopant regions in the single crystal Si. In one embodiment the diode of the present invention is integrated with a memory device.

Abstract: A semiconductor memory device includes a semiconductor substrate. An inter-layer dielectric is disposed on the semiconductor substrate. A bit line is disposed on the inter-layer dielectric. A bit line spacer is fabricated of a nitride layer containing boron and/or carbon and covers sidewalls of the bit line. A method of fabricating the semiconductor memory device is also provided.

Abstract: A bipolar transistor includes an isolation layer formed in a bipolar region on a semiconductor substrate, a conductive film formed over an upper portion of the isolation layer, n+ and p+ junction regions formed within the conductive film, a first silicide film formed over portions of an upper boundary of the n+ and p+ junction regions, the first silicide film defining openings over the upper boundary of the n+ and p+ junction regions, a second silicide film formed in the openings defined by the first silicide film over the upper boundary portions of the n+ and p+ junction regions, a plurality of plugs connected to the second silicide film, and a plurality of electrodes connected to each of the plugs.

Abstract: The present invention relates to a method of fabrication process which integrates the processing steps for fabricating the trench MIM capacitor with the conventional middle-of-line processing steps for fabricating metal contacts, so that the inner metallic electrode layer of the trench MIM capacitor and the metal contact of the FET or other logic circuitry components are formed by a single middle-of-line processing step and comprise essentially the same metallic material. The semiconductor device contains at least one trench metal-oxide-metal (MIM) capacitor and at least one other logic circuitry component, preferably at least one field effect transistor (FET). The trench MIM capacitor is located in a trench in a substrate and comprises inner and outer metallic electrode layers with a dielectric layer therebetween. The FET comprises a source region, a drain region, a channel region, and at least one metal contact connected with the source or drain region.

Abstract: A high fT and fmax bipolar transistor includes an emitter, a base, and a collector. The emitter has a lower portion and an upper portion that extends beyond the lower portion. The base includes an intrinsic base and an extrinsic base. The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.

Abstract: An integrated microelectronic circuit has a multi-layer interconnect structure overlying the transistors consisting of stacked metal pattern layers and insulating layers separating adjacent ones of said metal pattern layers. Each of the insulating layers is a dielectric material with plural gas bubbles distributed within the volume of the dielectric material to reduce the dielectric constant of the material, the gas bubbles being formed by ion implantation of a gaseous species into the dielectric material.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post which, in one exemplary embodiment, is situated between first and second link spacers. The bipolar transistor also comprises a conformal layer situated over the sacrificial post. The conformal layer may comprise silicon oxide, for example. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the sacrificial post, and the base. The sacrificial planarizing layer has a first thickness in a first region between the first and second link spacers and a second thickness in a second region outside of the first and second link spacers, where the second thickness is generally greater than the first thickness. Another embodiment is a method that achieves the above-described bipolar transistor.

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.

Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.

Abstract: A bipolar transistor has a high performance and high reliability, which are obtained by enhancing a withstanding voltage between an emitter and a base. The bipolar transistor includes a first impurity diffusion layer in a semiconducting substrate, an opening disposed in the first conductive film. A third impurity diffusion layer is formed so as to contain the second diffusion layer and side walls are formed on the side walls of the opening. A fourth impurity diffusion layer in the third impurity diffusion layer is formed in the opening surrounded by the side walls.

Abstract: A structure and method of making an NPN heterojunction bipolar transistor (100) includes a semiconductor substrate (11) with a first region (82) containing a dopant (86) for forming a base region of the transistor. A second region (84) adjacent to the first region is used to form an emitter region of the transistor. An interstitial trapping material (81) reduces diffusion of dopants in the base region during subsequent thermal processing.

Abstract: According to one embodiment of the invention, a method for manufacturing bipolar junction transistors includes disposing a first oxide layer between a semiconductor substrate and a base polysilicon layer, forming a dielectric layer outwardly from the base polysilicon layer, and forming an emitter region by removing a portion of the dielectric layer and a portion of the base polysilicon layer. The method further includes removing a portion of the first oxide layer to form undercut regions adjacent the emitter region and to enlarge the emitter region, and forming an oxide pad outwardly from the semiconductor substrate in the emitter region.

Abstract: The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. According to the present invention, the transistor has an auxiliary electrode to which a voltage is applied apart from a gate electrode and formed at both sides of the gate electrode. In a transistor that is turned on/off depending on a voltage applied to the gate electrode, a region where the gate electrode and the source/drain overlap is maintained to have the same voltage by the auxiliary electrode by always applying a high voltage to the auxiliary electrode upon an on operation of the transistor even when the gate electrode becomes a zero (0) volt upon a refresh operation of a DRAM device. Therefore, the present invention can prevent generation of GIDL current. Further, even though the gate electrode is continuously turned on/off, the auxiliary electrode always maintains the same voltage between the gate electrode and the bit line.

Abstract: A method of decreasing the dielectric constant of a dielectric layer. First, a dielectric layer is formed on a first conductive layer. A substance is then implanted into the dielectric layer.

Abstract: An epitaxial base bipolar transistor including an epitaxial single crystal layer on a single crystal single substrate; a raised emitter on a portion of the single crystal layer; a raised extrinsic base on a surface of the semiconductor substrate; an insulator between the raised emitter and the raised extrinsic base, wherein the insulator is a spacer; and a diffusion from the raised emitter and from the raised extrinsic base to provide an emitter diffusion and an extrinsic base diffusion in the single crystal layer, wherein the emitter diffusion has an emitter diffusion junction depth.

Abstract: A bipolar junction transistor includes a substrate, a first layer, a second layer, and a third layer. The first layer comprises non-single-crystalline semiconductor material having a first conductivity type deposited on the substrate. The second layer comprises non-single-crystalline semiconductor material having a second conductivity type deposited on at least a portion of the first layer. The third layer comprises non-single-crystalline semiconductor material having a conductivity type different than the second conductivity type deposited on at least a portion of the second layer. The first, second, and third layers form a collector, base, and emitter of the bipolar junction transistor.

Abstract: A resistor cascade has a multiplicity of electrical resistors connected in series, and each electrical resistor has at least one single-walled carbon nanotube.

Abstract: A method of manufacturing a semiconductor component includes providing a substrate (110), an electrically insulative layer (710 or 810) over the substrate, and an electrically conductive layer (820) over the electrically insulative layer. A hole (1510) is etched into a portion (910) of the electrically conductive layer and into a portion of the electrically insulative layer. Another electrically conductive layer (1710) is deposited in the hole, and the two electrically conductive layers are etched to leave a portion (1810) of the second electrically conductive layer in the hole. Then, an additional electrically conductive layer (1910) is grown over the substrate and over the portion of the second electrically conductive layer.

Abstract: A method of decapsulating a packaged die includes removing packaging material from the bottom section of a die-containing package to expose a die pan, removing the die pan, removing material between the die pan and the bottom surface of the die, using the bottom surface of the die to determine a grind plane substantially parallel to the top surface of the die, and removing packaging material from the top section of the die-containing package to form a top surface substantially planar to the grind plane, preferably intersecting the wire bonds on the face of the die.

Abstract: The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer; overetching the silicon nitride under the spacers; filling the overetched layer with highly-doped N-type polysilicon; depositing an N-type doped polysilicon layer; and diffusing the doping contained in the third and fourth layers to form the emitter of the bipolar transistor.

Abstract: The present invention relates to a method for fabricating an integrated circuit including MOS transistors and a bipolar transistor of NPN type, including the steps of: forming the MOS transistors, covering the entire structure with a protection layer, opening the protection layer at the base-emitter location of the bipolar transistor, forming a first P-type doped layer of polysilicon, a second layer of silicon nitride and a second oxide layer, opening these last three layers at the center of the emitter-base region of the bipolar transistor, and depositing a third silicon nitride layer, forming spacers, removing the apparent parts of the third layer of silicon nitride, and depositing a third N-type doped polysilicon layer.

Abstract: Impurities are formed in the active region of a semiconductor substrate by diffusion from a gate electrode sidewall spacer. A gate electrode is formed on a semiconductor substrate with a gate dielectric layer therebetween. Sidewall spacers are formed on the side surfaces of the gate electrode. Dopant atoms are subsequently introduce to transform the spacers into solid dopant sources. Dopant atoms are diffused from the spacers into the semiconductor substrate to form first doped regions.

Abstract: A method of fabricating a semiconductor device includes the steps of preparing a semiconductor substrate having a first region and a second region, forming a first gate electrode and a second gate electrode over the semiconductor substrate at the first and second regions, respectively, implanting a first impurity ion into the substrate of the first region using the first gate electrode as a mask, implanting a second impurity ion into the substrate of the second region using the second gate electrode as a mask, forming sidewall spacers at both sides of each of the first and second gate electrodes, and implanting the second impurity ion into the first and second regions using the first and second gate electrodes and the sidewall spacers as masks.

Abstract: Methods of forming bipolar junction transistors include the steps of forming a semiconductor substrate having a highly doped buried collector region therein and an intrinsic collector region extending from the buried collector region to a face of the semiconductor substrate. A first electrically insulating layer and first polysilicon layer are formed on the face. Separate masking and ion implantation steps are then performed to convert the first polysilicon layer into a highly doped first portion of first conductivity type and a highly doped second portion of second conductivity type. The first conductive layer may be patterned to define the emitter contact and base contact and expose the intrinsic collector region.

Abstract: A method for making a self-aligned isolated flash memory core without damaging tunnel oxide layers between memory element stacks and the silicon substrate supporting the stacks includes depositing three sidewall layers on the stacks, prior to etching isolation trenches between the stacks, to thereby shield the tunnel oxide during isolation trench etching.

Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

Abstract: A semiconductor device with a bipolar transistor that enables to realize a reliable, electric connection of an intrinsic base region with a base electrode is provided. A semiconductor substructure has a surface area. An intrinsic base region is formed in the surface area. An emitter region is formed in the surface area to be surounded by the intrinsic base region, and an emitter electrode is formed to be contacted with the emitter region. An insulator is formed to surround the emitter electrode. A base electrode is formed not to be contacted with the intrinsic base region A conductive region is formed to be contacted with the intrinsic base region and the base electrode. The substructure has a recess formed on the surface area. The conductive region is produced by supplying a conductive material to the recess to be contacted with the intrinsic base region and the base electrode. The intrinsic base region is electrically connected to the base electrode through the conductive region.

Abstract: An ultrahigh speed bipolar transistor has a base region which is formed from a P.sup.+ base polysilicon sidewall using a self-alignment method, and a base junction window which is formed in order to minimize the collector-base junction capacity. In the method for fabricating this transistor, an insulation layer of oxide silicon or nitrogen silicon is formed under the base polysilicon layer. Accordingly, impurities from the base polysilicon layer do not diffuse into the epitaxial layer during the diffusion process. Instead, the extrinsic base region is formed by the diffusion of impurities from the polysilicon sidewall which is connected to the base polysilicon layer. Therefore the length of the entire base region is shortened. Furthermore, the junction area between the collector region is also lowered. Thus, the collector-base junction capacity is decreased and a higher operating speed is obtained.

Abstract: A method of producing the bipolar transistor includes forming an aperture through a triple layer over an active region of an epitaxial layer, then forming a shallow polysilicon film at the bottom of the aperture. An intrinsic base region is formed by segregating a conductive impurity to the epitaxial layer by thermally oxidizing the polysilicon film. Then an extrinsic base region is formed by diffusing impurities into the epitaxial layer from a polysilicon sidewall formed on the aperture. In the transistor fabricated according to this method, an insulation layer of oxide silicon or nitrogen silicon is formed under the base polysilicon layer. Accordingly, impurities from the base polysilicon layer do not diffuse into the epitaxial layer during the diffusion process. Instead, the extrinsic base region is formed by the diffusion of impurities from the polysilicon sidewall which is connected to the base polysilicon layer. Therefore the length of the entire base region is shortened.

Abstract: The subject invention relates to a hybrid reinforcement material comprising a refractory metal core having a first coating comprising aluminum, oxygen and nitrogen, this coating of the general formula:Al.sub.x O.sub.y N.sub.zwhereinx is up to about 670 atomic % of the coatingy is from about 20 atomic % to about 55 atomic % ofthe coating; andz is from about 5 atomic % to about 45 atomic % of the coating, with the proviso that x+y+z=100, and having a second SiC coating.The subject invention further relates to a high strength, high temperature performance composite containing the hybrid reinforcement specified above.