Having Sidewall Patents (Class 438/366)
  • Patent number: 11764296
    Abstract: A method for fabricating a semiconductor device includes: forming a trench in a first major surface of a semiconductor body having a first conductivity type; forming a gate in the trench; forming a body region of a second conductivity type in the semiconductor body; implanting a second dopant species into a first region of the body region and a first dopant species into a second region of the body region, the first dopant species providing the first conductivity type, the second dopant species being different from the first dopant species and reducing the diffusion of the first dopant species in the semiconductor body; and thermally annealing the semiconductor body to form a source region that includes the first and second dopant species, and to produce a pn-junction between the source and body regions at a depth dpn from the first major surface, wherein 50 nm<dpn<300 nm.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: September 19, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder
  • Patent number: 11751492
    Abstract: A memory device is provided. The memory device includes a memory stack on a first dielectric layer, and a sidewall spacer on the memory stack. The memory device further includes a conductive cap on the sidewall spacer and the memory stack and an upper metal line on the conductive cap and the sidewall spacer, wherein the upper metal line wraps around the conductive cap, sidewall spacer, and memory stack.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: September 5, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dexin Kong, Ashim Dutta, Ekmini Anuja De Silva, Daniel Schmidt
  • Patent number: 11322595
    Abstract: The disclosure provides a heterojunction bipolar transistor and a preparation method thereof. Since an emitter region has the same physical structure as a base region, and improves frequency characteristics of the device; Simultaneously with biaxial strain, uniaxial strain is introduced. Carrier transmission time in the collector region will be effectively reduced. By this structure, the width of the effective collector region is reduced, the collector junction capacitance is reduced, and the frequency characteristics of the device are further improved; an appropriate choice of the thickness of the Si cap layer can effectively reduce the accumulation of carriers at an interface and increase the gain of the device; at the same time, the preparation method of the bipolar transistor is completely compatible with a 90-nanometer CMOS process, which effectively reduces the development and manufacturing cost of the device.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: May 3, 2022
    Assignee: Yanshan University
    Inventors: Chunyu Zhou, Zuowei Li, Guanyu Wang, Xin Geng
  • Patent number: 9111986
    Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An intrinsic base layer is formed on a semiconductor substrate, an etch stop layer is formed on the intrinsic base layer, and an extrinsic base layer is formed on the etch stop layer. A trench is formed that penetrates through the extrinsic base layer to the etch stop layer. The trench is formed by etching the extrinsic base layer selective to the etch stop layer. The first trench is extended through the etch stop layer to the intrinsic base layer by etching the etch stop layer selective to the intrinsic base layer. After the trench is extended through the etch stop layer, an emitter is formed using the trench.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: August 18, 2015
    Assignee: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, Peng Cheng, Vibhor Jain, Qizhi Liu, John J. Pekarik
  • Patent number: 9070697
    Abstract: A device for detecting a laser attack made on an integrated circuit chip comprises a bipolar transistor of a first type formed in a semiconductor substrate, that bipolar transistor comprising a parasitic bipolar transistor of a second type. A buried region, forming the base of the parasitic bipolar transistor, operates as a detector of the variations in current flowing caused by impingement of laser light on the substrate.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: June 30, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Fabrice Marinet, Jimmy Fort, Alexandre Sarafianos, Julien Mercier
  • Patent number: 8664698
    Abstract: High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. An emitter, intrinsic base and collector are formed in a semiconductor body. An emitter contact has a region that overlaps a portion of an extrinsic base contact. A sidewall is formed in the extrinsic base contact proximate a lateral edge of the overlap region of the emitter contact. The sidewall is amorphized during or after formation so that when the emitter contact and the extrinsic base contact are, e.g., silicided, some of the metal atoms forming the silicide penetrate into the sidewall so that part of the highly conductive silicided extrinsic base contact extends under the edge of the overlap region of the emitter contact closer to the intrinsic base, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: March 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jay P. John, James A. Kirchgessner, Vishal P. Trivedi
  • Patent number: 8603883
    Abstract: Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: December 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Peng Cheng, Qizhi Liu, Ljubo Radic
  • Patent number: 8551849
    Abstract: Aimed at providing a highly reliable semiconductor device appropriately increased in stress at the channel region so as to improve carrier injection rate, thereby dramatically improved in transistor characteristics, and made adaptable also to recent narrower channel width, and a method of manufacturing the same, and a method of manufacturing the same, a first sidewall composed of a stress film having expandability is formed on the side faces of a gate electrode, a second sidewall composed of a film having smaller stress is formed on the first sidewall, and a semiconductor, which is a SiC layer for example, is formed as being positioned apart from the first sidewall while placing the second sidewall in between.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: October 8, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyoshi Tamura
  • Patent number: 8502347
    Abstract: Bipolar junction transistors are provided in which at least one of an emitter contact, a base contact, or a collector contact thereof is formed by epitaxially growing a doped SixGe1-x layer, wherein x is 0?x?1, at a temperature of less than 500° C. The doped SixGe1-x layer comprises crystalline portions located on exposed surfaces of a crystalline semiconductor substrate and non-crystalline portions that are located on exposed surfaces of a passivation layer which can be formed and patterned on the crystalline semiconductor substrate. The doped SixGe1-x layer of the present disclosure, including the non-crystalline and crystalline portions, contains from 5 atomic percent to 40 atomic percent hydrogen.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: August 6, 2013
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Tak H. Ning, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8105960
    Abstract: A semiconductor structure is provided that includes a spacer directly abutting a topographic edge of at least one patterned material layer. The spacer is a non-removable polymeric block component of a self-assembled block copolymer. A method of forming such a semiconductor structure including the inventive spacer is also provided that utilizes self-assembled block copolymer technology.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Carl J. Radens
  • Patent number: 8084320
    Abstract: A non-volatile memory is described, which includes gate structures, doped regions, second spacers and contact plugs. The gate structures are disposed on the substrate, each of which includes a control gate and a gate dielectric layer. The control gates are disposed on the substrate, and two first spacers are deployed at both sides of each control gate. The gate dielectric layers are disposed between the control gates and the substrate, respectively. Each of the doped regions is formed in the substrate between two adjacent gate structures. The second spacers are disposed on the sidewalls of the gate structures. The contact plugs are formed between two adjacent second spacers, respectively.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: December 27, 2011
    Assignee: Winbond Electronics Corp.
    Inventors: Lu-Ping Chiang, Hsiu-Han Liao
  • Patent number: 7935606
    Abstract: A method in which an oxide layer is formed on material defining and surrounding an emitter window. The technique comprises depositing a non-conformal oxide layer on the surrounding material and in the emitter window, whereby the thickness of at least a portion of the oxide layer in the emitter window is smaller than the thickness of the oxide layer on the surrounding material outside the emitter window; and removing at least a portion of the oxide layer in the emitter window so as to reveal at least a portion of the bottom of the emitter window whilst permitting at least a portion of the oxide layer to remain on the surrounding material. The technique can be used in the manufacture of a self-aligned epitaxial base BJT (bipolar junction transistor) or SiGe HBT (hetero junction bipolar transistor).
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: May 3, 2011
    Assignee: X-Fab Semiconductor Foundries AG
    Inventor: Jun Fu
  • Patent number: 7932145
    Abstract: A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the oxide nitride structure and the base electrode; (e) removing a top layer of the oxide nitride structure; (f) removing a first portion of the dielectric layer; (g) forming an epitaxial layer over the semiconductor substrate; (h) forming a second spacer over the epitaxial layer; and (i) forming an emitter electrode over the epitaxial layer and adjacent to the second spacer.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: April 26, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jay P. John, James A. Kirchgessner, Matthew W. Menner
  • Patent number: 7902051
    Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including providing a single crystal substrate; forming an insulating layer on the single crystal substrate; forming a via through the insulating layer to provide an exposed portion of the single crystal substrate; forming amorphous Si on at least the exposed portion of the single crystal substrate; converting at least a portion of the amorphous Si into single crystal Si; and forming dopant regions in the single crystal Si. In one embodiment the diode of the present invention is integrated with a memory device.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: March 8, 2011
    Assignees: International Business Machines Corporation, Qimonda AG, Macronix International Co., Ltd.
    Inventors: Bipin Rajendran, Thomas Happ, Hsiang-Lan Lung
  • Publication number: 20100181649
    Abstract: Memory cells having memory elements self-aligned with the emitters of bipolar junction transistor access devices are described herein, as well as methods for manufacturing such devices. A memory device as described herein comprises a plurality of memory cells. Memory cells in the plurality of memory cells include a bipolar junction transistor comprising an emitter comprising a pillar of doped polysilicon. The memory cells include an insulating element over the emitter and having an opening extending through the insulating layer, the opening centered over the emitter. The memory cells also include a memory element within the opening and electrically coupled to the emitter.
    Type: Application
    Filed: January 22, 2009
    Publication date: July 22, 2010
    Applicants: Macronix International Co., Ltd., International Business Machines Corporation
    Inventors: Hsiang-Lan Lung, Erh-Kun Lai, Chung H. Lam, Bipin Rajendran
  • Patent number: 7709339
    Abstract: Method for producing a planar spacer, an associated bipolar transistor and an associated BiCMOS circuit arrangement. The invention relates to a method for production of a planar spacer, of an associated bipolar transistor and of an associated BiCMOS circuit arrangement, in which first and second spacer layers are formed after the formation of a sacrificial mask on a mount substrate. A first anisotropic etching process of the second spacer layer is carried out to produce auxiliary spacers. A second anisotropic etching step is then carried out, in order to produce the planar spacers, using the auxiliary spacers as an etch mask.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: May 4, 2010
    Assignee: Infineon Technologies AG
    Inventors: Claus Dahl, Armin Tilke
  • Publication number: 20100013051
    Abstract: A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the oxide nitride structure and the base electrode; (e) removing a top layer of the oxide nitride structure; (f) removing a first portion of the dielectric layer; (g) forming an epitaxial layer over the semiconductor substrate; (h) forming a second spacer over the epitaxial layer; and (i) forming an emitter electrode over the epitaxial layer and adjacent to the second spacer.
    Type: Application
    Filed: September 24, 2009
    Publication date: January 21, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jay P. John, James A. Kirchgessner, Matthew W. Menner
  • Patent number: 7615457
    Abstract: A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The collector pedestal can be formed on a surface of a collector active region exposed within an opening extending through first and second overlying dielectric regions, where the opening defines vertically aligned edges of the first and second dielectric regions.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: November 10, 2009
    Assignee: International Business Machines Corporation
    Inventors: Hiroyuki Akatsu, Rama Divakaruni, Gregory G. Freeman, David R. Greenberg, Marwan H. Khater, William R. Tonti
  • Patent number: 7611955
    Abstract: A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the oxide nitride structure and the base electrode; (e) removing a top layer of the oxide nitride structure; (f) removing a first portion of the dielectric layer; (g) forming an epitaxial layer over the semiconductor substrate; (h) forming a second spacer over the epitaxial layer; and (i) forming an emitter electrode over the epitaxial layer and adjacent to the second spacer.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: November 3, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jay P. John, James A. Kirchgessner, Matthew W. Menner
  • Patent number: 7521327
    Abstract: A high fT and fmax bipolar transistor includes an emitter, a base, and a collector. The emitter has a lower portion and an upper portion that extends beyond the lower portion. The base includes an intrinsic base and an extrinsic base. The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: April 21, 2009
    Assignee: International Business Machines Corporation
    Inventors: Alvin Jose Joseph, Qizhi Liu
  • Patent number: 7491617
    Abstract: A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: February 17, 2009
    Assignee: International Business Machines Corporation
    Inventors: David R. Greenberg, Shwu-Jen Jeng
  • Patent number: 7396723
    Abstract: A method of manufacturing an EEPROM device can reduce the cell area. The method of manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM) includes forming a mask pattern over a semiconductor substrate; forming a gate oxide layer over a top of the semiconductor substrate exposed through the mask pattern; forming access gates which are self-aligned with both side walls of the mask pattern, over a top of the gate oxide layer; removing the mask pattern; forming first dielectric spacers to be attached to side walls of the access gates; forming an insulating layer adapted to cover the access gates and the first dielectric spacers; and forming two cell gates, which are self-aligned with opposite side walls of the two access gates, respectively, each first dielectric spacer being interposed between a corresponding cell gate and a corresponding access gate, the cell gates separately arranged over a top of the insulating layer.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: July 8, 2008
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Dong-Oog Kim
  • Patent number: 7397070
    Abstract: In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: July 8, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Gordon M. Grivna
  • Patent number: 7338875
    Abstract: Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is described. A temporary spacer (e.g., an oxide spacer) is deposited over a dielectric separation layer. The temporary spacer and dielectric separation layers are then anisotropically etched, forming a dielectric “boot shape” on a lower edge of the dielectric separation layer. An area within this non-photolithographically produced boot region defines an emitter contact window. Since the boot tip is formed through deposition and etching techniques, the emitter window is automatically aligned (i.e., self-aligned) with an underlying base region. Feature sizes are determined by deposition and etching techniques. Consequently, photolithography of small features is eliminated.
    Type: Grant
    Filed: October 9, 2006
    Date of Patent: March 4, 2008
    Assignee: Atmel Corporation
    Inventor: Bohumil Lojek
  • Patent number: 7300850
    Abstract: In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: November 27, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Gordon M. Grivna
  • Patent number: 7288829
    Abstract: Disclosed is a method of forming a transistor in an integrated circuit structure that begins by forming a collector in a substrate and an intrinsic base above the collector. Then, the invention patterns an emitter pedestal for the lower portion of the emitter on the substrate above the intrinsic base. Before actually forming the emitter or associates spacer, the invention forms an extrinsic base in regions of the substrate not protected by the emitter pedestal. After this, the invention removes the emitter pedestal and eventually forms the emitter where the emitter pedestal was positioned.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: October 30, 2007
    Assignee: International Business Machines Corporation
    Inventors: Marwan H Khater, Francois Pagette
  • Publication number: 20070232009
    Abstract: By providing an additional detector system for detecting the actual substrate position during transfer from and to a load lock station, the reliability of the corresponding process tool may be significantly enhanced. For example, an invalid position of the substrate during transfer from and to the load lock station may be reliably detected, in particular when a malfunction of the positioning system occurs. Consequently, a corresponding counter-measure may be taken, such as immediate interruption of the transfer operation, thereby reducing the risk of substrate damage or breakage.
    Type: Application
    Filed: October 20, 2006
    Publication date: October 4, 2007
    Inventor: Marko Schulz
  • Patent number: 7271051
    Abstract: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: September 18, 2007
    Assignee: Micron Technology, Inc.
    Inventors: H. Montgomery Manning, Thomas M. Graettinger, Marsela Pontoh
  • Patent number: 7259050
    Abstract: A semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer having a first layer and a second layer formed on the sidewalls of the gate, wherein the first and second layers have comparable wet etch rates of at least 10 ? per minute using the same etchant.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: August 21, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hao Chen, Chia-Lin Chen, Tze Liang Lee, Shih-Chang Chen, Ju-Wang Hsu
  • Patent number: 7232732
    Abstract: Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is described. A temporary spacer (e.g., an oxide spacer) is deposited over a dielectric separation layer. The temporary spacer and dielectric separation layers are then anisotropically etched, forming a dielectric “boot shape” on a lower edge of the dielectric separation layer. An area within this non-photolithographically produced boot region defines an emitter contact window. Since the boot tip is formed through deposition and etching techniques, the emitter window is automatically aligned (i.e., self-aligned) with an underlying base region. Feature sizes are determined by deposition and etching techniques. Consequently, photolithography of small features is eliminated.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: June 19, 2007
    Assignee: Atmel Corporation
    Inventor: Bohumil Lojek
  • Patent number: 7169677
    Abstract: A method for fabricating a spacer structure includes: forming a gate insulation layer having a gate deposition-inhibiting layer, a gate layer and a covering deposition-inhibiting layer on a semiconductor substrate, and patterning the gate layer and the covering deposition-inhibiting layer in order to form gate stacks. An insulation layer is deposited selectively using the deposition-inhibiting layers, thereby permitting highly accurate formation of the spacer structure.
    Type: Grant
    Filed: May 14, 2003
    Date of Patent: January 30, 2007
    Assignee: Infineon Technologies AG
    Inventor: Helmut Tews
  • Patent number: 7118981
    Abstract: In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component properties of the integrated silicon-germanium heterobipolar transistor.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: October 10, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Alfred Haeusler, Philipp Steinmann, Scott Balster, Badih El-Kareh
  • Patent number: 7105415
    Abstract: The invention relates to a method for producing a bipolar transistor. A semiconductor substrate is provided that encompasses a collector area of a first conductivity type, which is embedded therein and is bare towards the top. A monocrystalline base area is provided and a base-connecting area of the second conductivity type is provided above the base area. An insulating area is provided above the base-connecting area and a window is formed in the insulating area and the base-connecting area so as to at least partly expose the base area. An insulating sidewall spacer is provided in the window in order to insulate the base-connecting area. An emitter layer which forms a monocrystalline emitter area above the base area and a polycrystalline emitter area above the insulating area and the sidewall spacer is differentially deposited and structured, and a tempering step is carried out.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: September 12, 2006
    Assignee: Infineon Technologies AG
    Inventors: Josef Bock, Thomas Meister, Reinhard Stengl, Herbert Schafer
  • Patent number: 7094636
    Abstract: A method of forming a conductive line includes forming conductive material received over a semiconductor substrate into a line having opposing sidewalls. Insulative material is deposited over the line, and is planarized. An insulating spacer forming layer is deposited over the line and the planarized insulative material. The spacer forming layer is anisotropically etched form a pair of insulative spacers over the opposing line sidewalls with the insulative material being received between at least one of the sidewalls and one insulative spacer formed thereover. The insulative material as so received has a maximum lateral thickness which is greater than a maximum lateral thickness of the one sidewall spacer.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: August 22, 2006
    Assignee: Micron Technology, Inc.
    Inventor: H. Montgomery Manning
  • Patent number: 7084028
    Abstract: A semiconductor device comprises a semiconductor substrate having a cavity region inside; a first insulation film formed on the inner wall of the cavity region; a first electrode formed on the inner wall of the first insulation film in the cavity region, and having a hollow cavity inside; a semiconductor region overlying the cavity region and including first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type which are adjacent to each other, said semiconductor region having a bottom surface on which the first electrode is formed via the first insulation film; a second insulation film covering the top surface of the semiconductor region; and a second electrode formed on the semiconductor region via the second insulation film and electrically insulated from the semiconductor region and the first electrode.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: August 1, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Fukuzumi
  • Patent number: 7005359
    Abstract: A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter pedestal.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: February 28, 2006
    Assignee: Intel Corporation
    Inventors: Shahriar Ahmed, Ravindra Soman, Anand Murthy, Mark Bohr
  • Patent number: 6943077
    Abstract: A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.
    Type: Grant
    Filed: April 7, 2003
    Date of Patent: September 13, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ai-Sen Liu, Baw-Ching Perng, Ming-Ta Lei, Yih-Shung Lin, Cheng-Chung Lin, Chia-Hui Lin
  • Patent number: 6924202
    Abstract: A heterojunction bipolar transistor (HBT), and manufacturing method therfor, comprising a semiconductor substrate having a collector region is provided. A base contact layer is formed over the collector region, and a base trench is formed in the base contact layer and the collector region. An intrinsic base structure having a sidewall portion and a bottom portion is formed in the base trench. An insulating spacer is formed over the sidewall portion of the intrinsic base structure, and an emitter structure is formed over the insulating spacer and the bottom portion of the intrinsic base structure. An interlevel dielectric layer is formed over the base contact layer and the emitter structure. Connections are formed through the interlevel dielectric layer to the collector region, the base contact layer, and the emitter structure. The intrinsic base structure is silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: August 2, 2005
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Jian Xun Li, Lap Chan, Purakh Raj Verma, Jia Zhen Zheng, Shao-fu Sanford Chu
  • Patent number: 6911368
    Abstract: In a bipolar double-poly transistor comprising a layer of base silicon (1?) on a silicon substrate (2?), a first layer of silicon dioxide (3?) on the base silicon layer (1?), an emitter window (4?) extending through the first layer (3?) of silicon dioxide and the base silicon layer (1?), a second layer (5?) of silicon dioxide in the emitter window (4?), silicon nitride spacers (6?) on the second layer (5?) of silicon dioxide in the emitter window (4?), and emitter silicon (9?) in the emitter window (4?), an isolating silicon nitride seal is provided to separate the base silicon (1?) from the emitter silicon (9?) to prevent short-circuiting between the base silicon (1?) and the emitter silicon (9?) in the transistor.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: June 28, 2005
    Assignee: Infineon Technologies AG
    Inventors: Ted Johansson, Hans Norström, Anders Lindgren
  • Patent number: 6900519
    Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: May 31, 2005
    Assignee: International Business Machines Corporation
    Inventors: Marc W. Cantell, James S. Dunn, David L. Harame, Robb A. Johnson, Louis D. Lanzerotti, Stephen A. St. Onge, Brian L. Tessier, Ryan W. Wuthrich
  • Patent number: 6887765
    Abstract: According to one embodiment of the invention, a method used in manufacturing an intermediate structure in a bipolar junction transistor includes implanting a base dopant in a semiconductor substrate to form a base, forming a dielectric layer outwardly from the semiconductor substrate, etching a portion of the dielectric layer to form an emitter region, forming an emitter polysilicon layer on the semiconductor substrate, and after forming the emitter polysilicon layer, annealing the semiconductor substrate.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: May 3, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory E. Howard, Angelo Pinto
  • Patent number: 6869854
    Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: March 22, 2005
    Assignee: International Business Machines Corporation
    Inventors: Marc W. Cantell, James S. Dunn, David L. Harame, Robb A. Johnson, Louis D. Lanzerotti, Stephen A. St. Onge, Brian L. Tessier, Ryan W. Wuthrich
  • Patent number: 6867105
    Abstract: A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: March 15, 2005
    Assignee: Infineon Technologies AG
    Inventors: Reinhard Stengl, Thomas Meister, Herbert Schäfer, Martin Franosch
  • Patent number: 6861325
    Abstract: A method for fabricating a lateral bipolar junction transistor in an active area of a substrate includes forming a base structure directly on a central portion of the active area without a gate oxide layer being formed on the substrate. The method also includes implanting a first type of dopant into the active area for forming an emitter region and a collector region, and forming contacts and interconnects for the base structure and emitter and collector regions.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: March 1, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James N. Pan, Matthew Buynoski
  • Patent number: 6846716
    Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: January 25, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Geoffrey C-F Yeap, Srinivas Jallepalli, Yongjoo Jeon, James David Burnett, Rana P. Singh, Paul A. Grudowski
  • Patent number: 6830967
    Abstract: According to an exemplary method in one embodiment, a transistor gate is fabricated on a substrate. Next, an etch stop layer may be deposited on the substrate. The etch stop layer may, for example, be TEOS silicon dioxide. Thereafter, a conformal layer is deposited over the substrate and the transistor gate. The conformal layer may, for example, be silicon nitride. An opening is then etched in the conformal layer. Next, a base layer is deposited on the conformal layer and in the opening. The base layer may, for example, be silicon-germanium. According to this exemplary embodiment, an emitter may be formed on the base layer in the opening. Next, the base layer is removed from the conformal layer. The conformal layer is then etched back to form a spacer adjacent to the transistor gate. In one embodiment, a structure is fabricated according to the above described exemplary method.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: December 14, 2004
    Assignee: Newport Fab, LLC
    Inventors: Kevin Q. Yin, Amol M. Kalburge, Klaus F. Schuegraf
  • Patent number: 6818492
    Abstract: This invention provides a semiconductor device which is excellent in high-frequency characteristics, wherein emitter diffusion is performed by a trench formed in a base region, the base resistance is further reduced, and the base-emitter capacitance is also reduced. A base electrode layer makes a contact with the whole surface of the base region. A tapered trench is provided in the base region. A finer emitter region is formed by emitter diffusion from the bottom portion of the trench. Since the base electrode is formed adjacently to the trench, the distance between an active region of the base and the base electrode layer can be shortened and a larger grounded area of a base can also be obtained, therefore the base resistance can be substantially reduced. In addition, by forming a fine region, the base-emitter capacitance between the base and emitter can also be reduced, therefore a transistor excellent in high-frequency characteristics can be obtained.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: November 16, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hirotoshi Kubo, Shigeyuki Murai, Hisaaki Tominaga, Hidetaka Sawame
  • Patent number: 6809353
    Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises first and second link spacers situated on the top surface of the base. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base between the first and second link spacers. The first and second link spacers may have a height, for example, approximately equal to or, in another embodiment, substantially less than a height of the sacrificial post. According to this exemplary embodiment, the bipolar transistor further comprises a non-sacrificial planarizing layer situated over the sacrificial post, first and second link spacers, and base. The non-sacrificial planarizing layer may comprise, for example, silicate glass. The sacrificial planarizing layer may have a height, for example, approximately equal to or, in another embodiment, greater than greater than a height of the first and second link spacers.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: October 26, 2004
    Assignee: Newport Fab, LLC
    Inventors: Amol M Kalburge, Marco Racanelli
  • Patent number: 6797579
    Abstract: A semiconductor device having a trench isolation structure and a method of fabricating the same are provided. The device has a trench region and an isolation structure. The trench region is disposed to define an active region at a predetermined region of an SOI substrate formed by sequentially stacking a buried insulating layer and an upper silicon layer on a base substrate. The isolation structure fills an inside of the trench region. The trench region has a deep trench region where the upper silicon layer penetrates to the buried insulating layer and a shallow trench region existing at an outside of the deep trench region. The method of forming a trench region with deep and shallow trench regions includes patterning an upper silicon layer of an SOI substrate. A trench oxide layer and a trench liner are conformally formed on a sidewall and a bottom of the trench region.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: September 28, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Han Yoo, Jae-Min Yu, Sang-Wook Park, Tae-Jung Lee
  • Patent number: 6784065
    Abstract: A low-power bipolar transistor is formed to have an intrinsic emitter region with a sub-lithographic width, and an oxide layer that is self aligned to an overlying extrinsic emitter. The small extrinsic emitter region reduces the maximum current that can flow through the transistor, while the self-aligned oxide layer and extrinsic emitter reduces the base-to-emitter junction size and device performance variability across the wafer.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: August 31, 2004
    Assignee: National Semiconductor Corporation
    Inventor: Abdalla Aly Naem