Forming Active Region From Adjacent Doped Polycrystalline Or Amorphous Semiconductor Patents (Class 438/365)
  • Patent number: 11462654
    Abstract: Disclosed is a solar cell including a semiconductor substrate, and a dopant layer disposed over one surface of the semiconductor substrate and having a crystalline structure different from that of the semiconductor substrate, the dopant layer including a dopant. The dopant layer includes a plurality of semiconductor layers stacked one above another in a thickness direction thereof, and an interface layer interposed therebetween. The interface layer is an oxide layer having a higher concentration of oxygen than that in each of the plurality of semiconductor layers.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: October 4, 2022
    Assignee: LG ELECTRONICS INC.
    Inventors: Wonjae Chang, Sungjin Kim, Juhwa Cheong, Junyong Ahn
  • Patent number: 9054149
    Abstract: A method of fabricating a bipolar transistor including emitter and base regions having first and second conductivity types, respectively, includes forming an isolation region at a surface of a semiconductor substrate, the isolation region having an edge that defines a boundary of an active area of the emitter region, and implanting dopant of the second conductivity type through a mask opening to form the base region in the semiconductor substrate. The mask opening spans the edge of the isolation region such that an extent to which the dopant passes through the isolation region varies laterally to establish a variable depth contour of the base region.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: June 9, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiangkai Zuo
  • Patent number: 9006059
    Abstract: The invention provides a method for fabricating a CMOS transistor and a method for fabricating an array substrate. The method for fabricating a CMOS transistor comprises a step of forming channels, which comprises: depositing an amorphous silicon layer on a substrate, and crystallizing the amorphous silicon layer into a poly-silicon layer; implanting boron atoms into the poly-silicon layer and then forming an N channel region and a P channel region by etching the poly-silicon layer implanted with the boron atoms; forming a photoresist-partially-retained region corresponding to the N channel region and a photoresist-completely-retained region corresponding to the P channel region through a single patterning process; and removing the photoresist in the photoresist-partially-retained-region and retaining a part of the photoresist in the photoresist-completely-retained region using an ashing process, implanting phosphorus atoms through ion implantation thereby forming an N channel and a P channel.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: April 14, 2015
    Assignee: Boe Technology Group Co., Ltd
    Inventor: Bing Sun
  • Patent number: 8941112
    Abstract: A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: January 27, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8936976
    Abstract: Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: January 20, 2015
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Prashant Majhi, Jack T. Kavalieros, Niti Goel, Wilman Tsai, Niloy Mukherjee, Yong Ju Lee, Gilbert Dewey, Willy Rachmady
  • Patent number: 8906771
    Abstract: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: December 9, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Mikhalev, Jim Fulford, Yongjun Jeff Hu, Gordon A. Haller, Lequn Liu
  • Patent number: 8865529
    Abstract: A thin-film transistor device manufacturing method and others according to the present disclosure includes: forming a plurality of gate electrodes above a substrate; forming a gate insulating layer on the plurality of gate electrodes; forming an amorphous silicon layer on the gate insulating layer; forming a buffer layer and a light absorbing layer above the amorphous silicon layer; forming a crystalline silicon layer by crystallizing the amorphous silicon layer with heat generated by heating the light absorbing layer using a red or near infrared laser beam; and forming a source electrode and a drain electrode on the crystalline silicon layer in a region that corresponds to each of the plurality of gate electrodes, and film thicknesses of the gate insulating layer, the amorphous silicon layer, the buffer layer, and the light absorbing layer satisfy predetermined expressions.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: October 21, 2014
    Assignee: Panasonic Corporation
    Inventor: Yuta Sugawara
  • Patent number: 8802535
    Abstract: Techniques for fabricating a field effect transistor (FET) device having a doped core and an undoped or counter-doped epitaxial shell are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A wafer is provided having a semiconductor material selected from the group consisting of silicon, silicon germanium and silicon carbon. At least one fin core is formed in the wafer. Ion implantation is used to dope the fin core. Corners of the fin core are reshaped to make the corners rounded or faceted. An epitaxial shell is grown surrounding the fin core, wherein the epitaxial shell includes a semiconductor material selected from the group consisting of silicon, silicon germanium and silicon carbon.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Siyuranga O. Koswatta, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8735290
    Abstract: A reactive evaporation method for forming a group III-V amorphous material attached to a substrate includes subjecting the substrate to an ambient pressure of no greater than 0.01 Pa, and introducing active group-V matter to the surface of the substrate at a working pressure of between 0.05 Pa and 2.5 Pa, and group III metal vapor, until an amorphous group III-V material layer is formed on the surface.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: May 27, 2014
    Assignee: Mosaic Crystal Ltd.
    Inventor: Moshe Einav
  • Patent number: 8734583
    Abstract: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy (SPE) process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The fin has a cross-sectional thickness in at least one direction less than a minimum feature size. The transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: May 27, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 8704217
    Abstract: A field effect transistor including a source electrode 107a, a drain electrode 107b, a gate electrode 103, an insulating film 105 and a semiconductor layer 109 containing a crystalline oxide, wherein the source electrode 107a and the drain electrode 107b are self-aligned with the gate electrode 103 with the insulating film 105 therebetween.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: April 22, 2014
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Koki Yano, Kazuyoshi Inoue, Shigekazu Tomai
  • Patent number: 8486797
    Abstract: Bipolar junction transistors are provided in which at least one of an emitter contact, a base contact, or a collector contact thereof is formed by epitaxially growing a doped SixGe1-x layer, wherein x is 0?x?1, at a temperature of less than 500° C. The doped SixGe1-x layer comprises crystalline portions located on exposed surfaces of a crystalline semiconductor substrate and non-crystalline portions that are located on exposed surfaces of a passivation layer which can be formed and patterned on the crystalline semiconductor substrate. The doped SixGe1-x layer of the present disclosure, including the non-crystalline and crystalline portions, contains from 5 atomic percent to 40 atomic percent hydrogen.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: July 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Tak H. Ning, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20130119384
    Abstract: A parasitic lateral PNP transistor is disclosed, in which, an N-type implanted region formed in each of two adjacent active regions forms a base region; a P-type doped polysilicon pseudo buried layer located under a shallow trench field oxide region between the two active regions serves as an emitter; and a P-type doped polysilicon pseudo buried layer located under each of the shallow trench field oxide regions on the outer side of the active regions serves as a collector region. The transistor has a C-B-E-B-C structure which alters the current path in the base region to a straight line, which can improve the current amplification capacity of the transistor and thus leads to a significant improvement of its current gain and frequency characteristics, and is further capable of reducing the area and increasing current intensity of the transistor. A manufacturing method of the parasitic lateral PNP transistor is also disclosed.
    Type: Application
    Filed: November 15, 2012
    Publication date: May 16, 2013
    Applicant: SHANGHAI HUA NEC ELECTRONICS CO., LTD.
    Inventor: Shanghai Hua Nec Electronics Co., Ltd.
  • Publication number: 20130037914
    Abstract: A bipolar junction transistor and a manufacturing method for the same are provided. The bipolar junction transistor includes a well region, an emitter electrode, a base electrode, a collector electrode, and a conductive layer. The emitter electrode, the base electrode and the collector electrode are separated from each other by the well region. The conductive layer is on the well region between the base electrode and the collector electrode.
    Type: Application
    Filed: August 8, 2011
    Publication date: February 14, 2013
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chin-Wei Chang, Ching-Lin Chan, Chin-Shien Lu, Ming-Tung Lee, Shuo-Lun Tu
  • Patent number: 8274081
    Abstract: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: September 25, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Mikhalev, Jim Fulford, Yongjun Jeff Hu, Gordon A. Haller, Lequn Liu
  • Patent number: 8252668
    Abstract: Provided is a photoelectric conversion device fabrication method that realizes both high productivity and high conversion efficiency by rapidly forming an n-layer having good coverage. The fabrication method for a photoelectric conversion device includes a step of forming a silicon photoelectric conversion layer on a substrate by a plasma CVD method. In the fabrication method for the photoelectric conversion device, the step of forming the photoelectric conversion layer includes a step of forming an i-layer formed of crystalline silicon and a step of forming, on the i-layer, an n-layer under a condition with a hydrogen dilution ratio of 0 to 10, inclusive.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: August 28, 2012
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Kengo Yamaguchi, Satoshi Sakai, Yoshiaki Takeuchi
  • Patent number: 8120242
    Abstract: A transistor capable of modulating, at low voltages, a large current flowing between an emitter electrode and a collector electrode. A process of producing the transistor, a light-emitting device comprising the transistor, and a display comprising the transistor. The transistor comprises an emitter electrode and a collector electrode. Between the emitter electrode and the collector electrode are situated a semiconductor layer and a sheet base electrode. It is preferred that the semiconductor layer be situated between the emitter electrode and the base electrode and also between the collector electrode and the base electrode to constitute a second semiconductor layer and a first semiconductor layer, respectively. It is also preferred that the thickness of the base electrode be 80 nm or less. Furthermore, a dark current suppressor layer is situated at least between the emitter electrode and the base electrode, or between the collector electrode and the base electrode.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: February 21, 2012
    Assignees: Osaka University, Sumitomo Chemical Company, Ltd., Dai Nippon Printing Co., Ltd., Ricoh Company, Ltd.
    Inventors: Masaaki Yokoyama, Kenichi Nakayama
  • Patent number: 8062949
    Abstract: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: November 22, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 8021951
    Abstract: Provided is a semiconductor device including: a silicon substrate; at least two trenches spaced apart from each other, being in parallel with each other, and being formed by vertically etching the silicon substrate from a surface thereof; an electrically insulating film for burying therein at least bottom surfaces of the trenches; a base region formed in a region of the silicon substrate located between the two trenches; and an emitter region and a collector region formed on portions of side surfaces of the trenches, respectively, the portions of the sides located above the insulating film and formed in the base region.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: September 20, 2011
    Assignee: Seiko Instruments Inc.
    Inventor: Kazuhiro Tsumura
  • Patent number: 7935606
    Abstract: A method in which an oxide layer is formed on material defining and surrounding an emitter window. The technique comprises depositing a non-conformal oxide layer on the surrounding material and in the emitter window, whereby the thickness of at least a portion of the oxide layer in the emitter window is smaller than the thickness of the oxide layer on the surrounding material outside the emitter window; and removing at least a portion of the oxide layer in the emitter window so as to reveal at least a portion of the bottom of the emitter window whilst permitting at least a portion of the oxide layer to remain on the surrounding material. The technique can be used in the manufacture of a self-aligned epitaxial base BJT (bipolar junction transistor) or SiGe HBT (hetero junction bipolar transistor).
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: May 3, 2011
    Assignee: X-Fab Semiconductor Foundries AG
    Inventor: Jun Fu
  • Patent number: 7902051
    Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including providing a single crystal substrate; forming an insulating layer on the single crystal substrate; forming a via through the insulating layer to provide an exposed portion of the single crystal substrate; forming amorphous Si on at least the exposed portion of the single crystal substrate; converting at least a portion of the amorphous Si into single crystal Si; and forming dopant regions in the single crystal Si. In one embodiment the diode of the present invention is integrated with a memory device.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: March 8, 2011
    Assignees: International Business Machines Corporation, Qimonda AG, Macronix International Co., Ltd.
    Inventors: Bipin Rajendran, Thomas Happ, Hsiang-Lan Lung
  • Patent number: 7892935
    Abstract: A semiconductor process is provided. The semiconductor process includes providing a substrate. Then, a surface treatment is performed to the substrate to form a buffer layer on the substrate. Next, a first pre-amorphous implantation is performed to the substrate.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: February 22, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Wei Chen, Chao-Ching Hsieh, Tsai-Fu Hsiao, Yu-Lan Chang, Tsung-Yu Hung, Chun-Chieh Chang
  • Patent number: 7893476
    Abstract: Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achieve higher on-currents a nanowire-based TFET with a germanium (Ge) tunnel barrier in an otherwise silicon (Si) channel is used. A nanowire is introduced such that the lattice mismatch between silicon and germanium does not result in a highly defective interface. A dynamic power reduction as well as a static power reduction can result, compared to conventional MOSFET configurations. Multiple layers of logic can therefore be envisioned with these nanowire Si/Ge TFETs resulting in ultra-high on-chip transistor densities.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: February 22, 2011
    Assignee: IMEC
    Inventor: Anne S. Verhulst
  • Patent number: 7868437
    Abstract: A mounting structure for an IC tag where an IC chip for mounting (10) is mounted so as to be electrically connected to antenna patterns (44a), (44b). The assembly process that mounts the IC chip for mounting (10) on the antenna patterns (44a), (44b) is simplified, which makes it possible to reduce the manufacturing cost of IC tags. The IC chip for mounting 10 is formed by winding conductive wires (12a), (12b) so as to encircle an outer surface of an IC chip (20) between two opposite edges of the IC chip (20) in a state where the conductive wires (12a), (12b) mechanically contact electrodes formed on the IC chip (20) and are electrically connected to the electrodes, so that the IC chip for mounting (10) is joined to the antenna patterns (44a), (44b) via the conductive wires (12a), (12b).
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: January 11, 2011
    Assignee: Fujitsu Limited
    Inventor: Shuichi Takeuchi
  • Patent number: 7790582
    Abstract: A method for fabricating a polysilicon liquid crystal display device includes: forming a first amorphous silicon layer on a substrate; forming a photoresist pattern on the first amorphous silicon layer; forming a second amorphous silicon layer over the photoresist pattern and the first amorphous silicon layer; defining a channel region on the first amorphous silicon layer; crystallizing the first and second silicon layers; forming an active layer by patterning the crystallized silicon layers; forming a first insulating layer on the active layer; forming a gate electrode on the first insulating layer; forming source and drain electrodes electrically connected to the active layer; and forming a pixel electrode electrically connected to the drain electrode.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: September 7, 2010
    Assignee: LG Display Co., Ltd.
    Inventor: Kum-Mi Oh
  • Patent number: 7785991
    Abstract: A process is provided for integrating a III-N component, such as GaN, on a (001) or (100) nominal silicon substrate. There are arranged a texture of elementary areas each comprising an individual surface, with the texture comprising at least one hosting area intended to receive a III-N component. A mask layer is deposited on non-hosting areas which are not intended to receive a III-N type component. The hosting area is locally prepared so as to generate on the surface of the area one domain comprising one single type of terrace. There is grown by Molecular Beam Epitaxy or Metalorganic Vapor Phase Epitaxy on the hosting area one intermediary AlN buffer layer, followed by the growth of one III-N based material so as to realize a substantially monocrystalline structure. There is eliminated the mask layer located on non-hosting areas as well as surface polycrystalline layers deposited above the mask layers, and MOS/CMOS structures are subsequent integrated on at least some of the non-hosting areas.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: August 31, 2010
    Assignee: STMicroelectronics SA
    Inventors: Sylvain Joblot, Fabrice Semond, Jean Massies, Yvon Cordier, Jean-Yves Duboz
  • Patent number: 7772048
    Abstract: A semiconductor device is made by steps of removing portions of a first capping layer, removing portions of a sacrificial layer, recessing sidewalls, and forming fin structures. The step of removing portions of the first capping layer forms a first capping structure that covers portions of the sacrificial layer. The step of removing portions of the sacrificial layer removes portions of the sacrificial layer that are not covered by the first capping structure to define an intermediate structure. The step of recessing the sidewalls recesses sidewalls of the intermediate structure relative to edge regions of the first capping structure to form a sacrificial structure having recessed sidewalls. The step of forming fin structures forms fin structures adjacent to the recessed sidewalls.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: August 10, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert E. Jones, Rickey S. Brownson
  • Patent number: 7736962
    Abstract: A junction field effect transistor comprises an insulating layer formed in a substrate. A source region of a first conductivity type is formed on the insulating layer, and a drain region of the first conductivity type is formed on the insulating layer and spaced apart from the drain region. A channel region of the first conductivity type is located between the source region and the drain region and formed on the insulating layer. A gate region of the second conductivity type surrounds all surfaces of a length of the channel region such that the channel region is embedded within the gate region.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: June 15, 2010
    Assignee: SuVolta, Inc.
    Inventor: Kiyoshi Mori
  • Patent number: 7736997
    Abstract: A flexible electronic device excellent in heat liberation characteristics and toughness and a production method for actualizing thereof in low cost and with satisfactory reproducibility are provided. A protection film is adhered onto the surface of a substrate on which surface a thin film device is formed. Successively, the substrate is soaked in an etching solution to be etched from the back surface thereof so as for the residual thickness of the substrate to fall within the range larger than 0 ?m and not larger than 200 ?m. Then, a flexible film is adhered onto the etched surface of the substrate, and thereafter the protection film is peeled to produce a flexible electronic device.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: June 15, 2010
    Assignee: NEC Corporation
    Inventor: Kazushige Takechi
  • Patent number: 7670917
    Abstract: In one aspect there is provided a method of manufacturing a semiconductor device comprising forming gate electrodes over a semiconductor substrate, forming source/drains adjacent the gate electrodes, depositing a stress inducing layer over the gate electrodes. A laser anneal is conducted on at least the gate electrodes subsequent to depositing the stress inducing layer at a temperature of at least about 1100° C. for a period of time of at least about 300 microseconds, and the semiconductor device is subjected to a thermal anneal subsequent to conducting the laser anneal.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: March 2, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Amitabh Jain, Manoj Mehrotra
  • Patent number: 7659213
    Abstract: By incorporating carbon by means of ion implantation and a subsequent flash-based or laser-based anneal process, strained silicon/carbon material with tensile strain may be positioned in close proximity to the channel region, thereby enhancing the strain-inducing mechanism. The carbon implantation may be preceded by a pre-amorphization implantation, for instance on the basis of silicon. Moreover, by removing a spacer structure used for forming deep drain and source regions, the degree of lateral offset of the strained silicon/carbon material with respect to the gate electrode may be determined substantially independently from other process requirements. Moreover, an additional sidewall spacer used for forming metal silicide regions may be provided with reduced permittivity, thereby additionally contributing to an overall performance enhancement.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: February 9, 2010
    Assignee: GlobalFoundries, Inc.
    Inventors: Andy Wei, Thorsten Kammler, Jan Hoentschel, Manfred Horstmann
  • Patent number: 7642168
    Abstract: A system and method are disclosed for providing a self aligned bipolar transistor using a sacrificial polysilicon external base. An active region of a transistor is formed and a sacrificial polysilicon external base is formed above the active region of the transistor and covered with a silicon oxide layer. Then an emitter window is etched and filled with silicon nitride. An etch procedure is subsequently performed to remove the sacrificial polysilicon external base. A layer of doped polysilicon material is then deposited to fill a cavity within the transistor formed by the removal of the sacrificial polysilicon external base. A polysilicon emitter structure is subsequently formed in the emitter window. The self aligned bipolar transistor architecture of the invention is compatible with BiCMOS technology.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: January 5, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Mingwei Xu, Steven J. Adler
  • Patent number: 7635634
    Abstract: In an embodiment of the invention, an amorphous phase dielectric material is selectively formed over a substrate. The amorphous phase dielectric material is then converted into a crystalline phase dielectric material.
    Type: Grant
    Filed: April 16, 2007
    Date of Patent: December 22, 2009
    Assignees: Infineon Technologies AG, IMEC VZW
    Inventors: Chris Stapelmann, Gert Jaschke, Armin Tilke
  • Patent number: 7625803
    Abstract: The invention includes a memory device having a capacitor in combination with a transistor. The memory device can be within a TFT construction. The capacitor is configured to provide both area and perimeter components of capacitance for capacitive enhancement. The capacitor includes a reference plate which splits into at least two prongs. Each of the prongs is surrounded by a lateral periphery. A dielectric material extends around the lateral peripheries of the prongs, and a storage node surrounds an entirety of the lateral peripheries of the prongs. The storage node is separated from the reference plate by at least the dielectric material. Also, the invention includes electronic systems comprising novel capacitor constructions.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: December 1, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 7585740
    Abstract: A system and method comprises forming an intrinsic base on a collector. The system and method further includes forming a fully silicided extrinsic base on the intrinsic base by a self-limiting silicidation process at a predetermined temperature and for a predetermined amount of time, the silicidation substantially stopping at the intrinsic base. The system and method further includes forming an emitter which is physically insulated from the extrinsic base and the collector, and which is in physical contact with the intrinsic base.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: September 8, 2009
    Assignee: International Business Machines Corporation
    Inventors: David C. Ahlgren, Guy M. Cohen, Christian Lavoie, Francois Pagette, Anna W. Topol
  • Patent number: 7557010
    Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: July 7, 2009
    Assignee: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh
  • Patent number: 7541250
    Abstract: A method for forming a self-aligned twin well region is provided. The method includes implanting a first well type doping species into the DHL such that its distribution remains stopped in the DHL above the silicon substrate, etching away a portion of the DHL using a photoresist mask, implanting a second well type doping species into the portions of the silicon substrate exposed by the etching, and moving a portion of the first well type doping species into the silicon substrate.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: June 2, 2009
    Assignee: Atmel Corporation
    Inventors: Gayle W. Miller, Jr., Bryan D. Sendelweck
  • Patent number: 7479438
    Abstract: The invention, in one aspect, provides a semiconductor device that comprises a bipolar transistor located over and within a semiconductor substrate, a collector located within a tub of the bipolar transistor and having an amorphous region formed at least partially therein, a base located over the collector, and an emitter located over the base. There is also provided a method of fabricating the semiconductor device.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: January 20, 2009
    Assignee: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Daniel C. Kerr, Nace M. Rossi
  • Patent number: 7465638
    Abstract: There is provided a bipolar transistor (with a respective fabrication method) that provides superior noise characteristics and gain diffusion. The fabricating method includes forming a first base region at a collector region, which in turn is formed on a substrate. A first silicon layer is formed on the base region, and a second silicon layer is formed on the first silicon layer using a forming method different from the method used in forming the first silicon layer. An emitter region is then formed from impurities at the base region by performing a thermal process.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: December 16, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kye-Won Maeng, Sung-Ryoul Bae, Dong-Kyun Nam, Tae-Jin Kim
  • Patent number: 7446009
    Abstract: A semiconductor device manufacturing method including forming a conductive layer and a silicon film on a semiconductor substrate including an active region, forming an emitter electrode containing a first impurity on the silicon film above the active region, partially etching the silicon film using the emitter electrode as a mask, forming an insulative film covering the semiconductor substrate and a side wall film covering a side surface of the emitter electrode, introducing a second impurity into the conductive layer and silicon film so that the second impurity reaches the active region to form an impurity region containing the second impurity in parts of the conductive layer and silicon film, and diffusing the first impurity contained in the emitter electrode into the silicon film to form in the silicon film a first region containing the first impurity and a second region free of the first impurity.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: November 4, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Daichi Suma, Yoshikazu Ibara, Tatsuhiko Koide, Koichi Saito
  • Patent number: 7425491
    Abstract: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: September 16, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 7343661
    Abstract: A method for making condenser microphones includes: forming a fixed electrode layer structure of a plurality of fixed electrode units; forming a sacrificial layer of a plurality of sacrificial units on one side of the fixed electrode layer structure; forming a diaphragm layer structure of a plurality of diaphragm units on the sacrificial layer; forming a patterned mask layer on an opposite side of the fixed electrode layer structure opposite to the sacrificial layer; forming a plurality of etching channels, each of which extends through the patterned mask layer and the fixed electrode layer structure; removing a portion of the sacrificial layer of each of the sacrificial units so as to form a spacer between a respective one of the fixed electrode units and a respective one of the diaphragm units; and removing the patterned mask layer.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: March 18, 2008
    Assignee: Taiwan Carol Electronics Co., Ltd.
    Inventors: Ray-Hua Horng, Zong-Ying Lin, Jean-Yih Tsai, Chao-Chih Chang
  • Patent number: 7232732
    Abstract: Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is described. A temporary spacer (e.g., an oxide spacer) is deposited over a dielectric separation layer. The temporary spacer and dielectric separation layers are then anisotropically etched, forming a dielectric “boot shape” on a lower edge of the dielectric separation layer. An area within this non-photolithographically produced boot region defines an emitter contact window. Since the boot tip is formed through deposition and etching techniques, the emitter window is automatically aligned (i.e., self-aligned) with an underlying base region. Feature sizes are determined by deposition and etching techniques. Consequently, photolithography of small features is eliminated.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: June 19, 2007
    Assignee: Atmel Corporation
    Inventor: Bohumil Lojek
  • Patent number: 7169677
    Abstract: A method for fabricating a spacer structure includes: forming a gate insulation layer having a gate deposition-inhibiting layer, a gate layer and a covering deposition-inhibiting layer on a semiconductor substrate, and patterning the gate layer and the covering deposition-inhibiting layer in order to form gate stacks. An insulation layer is deposited selectively using the deposition-inhibiting layers, thereby permitting highly accurate formation of the spacer structure.
    Type: Grant
    Filed: May 14, 2003
    Date of Patent: January 30, 2007
    Assignee: Infineon Technologies AG
    Inventor: Helmut Tews
  • Patent number: 7098113
    Abstract: A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accordingly, in a first approach the standard process flow will be followed until reaching the point where contact openings and metal are to be processed. In this approach slots are etched that are preferably 5 to 6 um deep and 5 to 6 um wide. These slots are then oxidized and will be subsequently metalized. When used for making metal contacts to the buried layer or for ground the oxide is removed from the bottom of the slots by an anisotropic etch. Subsequently when these slots receive metal they will provide contacts to the buried layer where this is desired and to the substrate when a ground is desired. In a second approach the above-identified process is completed up through the slot process without processing the lateral PNPs.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: August 29, 2006
    Assignee: Micrel, Inc.
    Inventors: John Durbin Husher, Ronald L. Schlupp
  • Patent number: 7005359
    Abstract: A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter pedestal.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: February 28, 2006
    Assignee: Intel Corporation
    Inventors: Shahriar Ahmed, Ravindra Soman, Anand Murthy, Mark Bohr
  • Patent number: 6951802
    Abstract: A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element solution, but there is a problem in that uniformity in the amount of added catalyst element within a substrate is poor. The non-uniformity in the amount of added catalyst element within the substrate is thought to influence fluctuation in crystallinity of a crystalline semiconductor film that has undergone thermal crystallization, and exert a bad influence on the electrical characteristics of TFTs finally structured by the crystalline semiconductor film. The present invention solves this problem with the aforementioned conventional technique.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: October 4, 2005
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Misako Nakazawa, Toshiji Hamatani, Naoki Makita
  • Patent number: 6924216
    Abstract: A method of forming the active regions of field effect transistors is proposed. According to the proposed method, shallow implanting profiles for both the halo structures and the source and drain regions can be obtained by carrying out a two-step damaging and amorphizing implantation process. During a first step, the substrate is damaged during a first light ion implantation step and subsequently substantially fully amorphized during a second heavy ion implantation step.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: August 2, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas Feudel, Manfred Horstmann, Rolf Stephan
  • Patent number: 6919253
    Abstract: A method of fabricating a semiconductor device according to the present invention includes a step A of forming a polycrystalline or amorphous preliminary semiconductor layer on a surface of a substrate so as to have an opening portion and a step B of simultaneously forming an epitaxial growth layer on an exposed portion of a surface of the substrate through the opening portion and a non-epitaxial growth layer on the preliminary semiconductor layer using a CVD method while heating the substrate inside a reaction chamber by means of a heat source inside the reaction chamber, the epitaxial growth layer being made of single crystalline semiconductor, and the non-epitaxial growth layer being comprised of a polycrystalline or amorphous semiconductor layer.
    Type: Grant
    Filed: February 7, 2003
    Date of Patent: July 19, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tohru Saitoh, Katsuya Nozawa, Minoru Kubo, Shigetaka Aoki
  • Patent number: 6913981
    Abstract: Embodiments of a bipolar transistor are disclosed, along with methods for making the transistor. An exemplary transistor includes a collector region in a semiconductor substrate, a base layer overlying the collector region and bound by a field oxide layer, a dielectric isolation layer overlying the base layer, and an emitter structure overlying the dielectric isolation layer and contacting the base layer through a central aperture in the dielectric layer. The transistor may be a heterojunction bipolar transistor with the base layer formed of a selectively grown silicon germanium alloy. A dielectric spacer may be formed adjacent the emitter structure and over a portion of the base layer.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: July 5, 2005
    Assignee: Micrel, Incorporated
    Inventors: Jay Albert Shideler, Jayasimha Swamy Prasad, Ronald Lloyd Schlupp, Robert William Bechdolt