Abstract: Methods of forming bipolar junction transistors include the steps of forming a semiconductor substrate having a highly doped buried collector region therein and an intrinsic collector region extending from the buried collector region to a face of the semiconductor substrate. A first electrically insulating layer and first polysilicon layer are formed on the face. Separate masking and ion implantation steps are then performed to convert the first polysilicon layer into a highly doped first portion of first conductivity type and a highly doped second portion of second conductivity type. The first conductive layer may be patterned to define the emitter contact and base contact and expose the intrinsic collector region.

Abstract: A silicon on insulator (SOI) process is disclosed which includes the steps of forming an etch stop layer in a starting wafer, forming an insulating layer on the etch stop layer, bonding this wafer to a handle wafer, thinning the start wafer down to the etch stop and then recovering a device layer from the etch stop layer by outgassing dopants from the etch stop layer.

Abstract: A process for forming a structure of a high-frequency bipolar transistor on a layer of a semiconductor material with conductivity of a first type. The process includes forming a first shallow base region by implantation along a selected direction of implantation and using a dopant with a second type of conductivity. The region extends from a first surface of the semiconductor material layer and encloses, toward said first surface, an emitter region with conductivity of the first type. In accordance with the invention, the implantation step includes at least one process phase at which the direction of implantation is maintained at a predetermined angle significantly greatly than zero degrees from the direction of a normal line to said first surface. Preferably, the implantation angle is of about 45 degrees.

Abstract: A method of forming a double polysilicon NPN transistor using a self-aligned process flow. The method includes use of a sacrificial oxide layer deposited over an epitaxial silicon layer prior to deposition and doping of the polysilicon layer from which the base electrode is formed. The sacrificial oxide layer acts as an etch stop for the plasma etch used to pattern the polysilicon layer. After patterning of the doped polysilicon layer, the sacrificial layer is removed using a wet etch. Etching of the oxide layer is performed in a manner which undercuts the doped polysilicon layer. Polysilicon is then deposited by a CVD process in the undercut region from which the initial polysilicon layer has been removed. The CVD deposited polysilicon fills in the gap between the doped polysilicon layer and the underlying epitaxial silicon layer caused by the oxide etch. The CVD deposited polysilicon is then oxidized.

Abstract: This invention provides a thin metallic sheet structure having excellent sound damping characteristics which can lower the sound pressure level of a sound inherent to a thin metallic sheet structure when this structure is patted, and can quickly damp the sound by a simple structure. In a flat sheet-like or box-like structure comprising a thin metallic external sheet and beams for reinforcing the external sheet, a thin metallic sheet structure having excellent sound damping characteristics according to the present invention employs the construction wherein the reinforcing beams 2 are brought into contact with one of the surfaces of the thin metallic external sheet 1 through a sound damping sheet 3, and the coupling state between the sound damping sheet 3 and the thin metallic external plate 1 or the reinforcing beams 2 is a non-coupling state or a discrete coupling state on at least one of the surfaces of the sound damping sheet 3.

Abstract: Emitter widths of 0.3 .mu.m on double polysilicon bipolar transistors are achieved using O.8 .mu.m photolithography and a double spacer process. The emitter width reduction is confirmed with structural and electrical measurements. The double-spacer device exhibits superior low current f.sub.T and f.sub.max.

Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

Abstract: A method for producing a multiplicity of microelectronic circuits on SOI produces n-CMOS or p-CMOS transistors, NPN transistors or PNP transistors, for instance, through the use of a standardized process, in an especially simple way. All that is required to do so is to adapt the implantations that are performed.

Abstract: A method of manufacturing a bipolar transistor having an improved polysilicon emitter is disclosed. More specifically, hydrogen terminations or OH group terminations adhered (bonded) to an emitter-forming region are eliminated by a heat treatment in an inert gas atmosphere before forming emitter polysilicon. Subsequently, an amorphous silicon film for forming an emitter polysilicon is formed at a low temperature.

Abstract: A semiconductor device with a bipolar transistor that enables to realize a reliable, electric connection of an intrinsic base region with a base electrode is provided. A semiconductor substructure has a surface area. An intrinsic base region is formed in the surface area. An emitter region is formed in the surface area to be surounded by the intrinsic base region, and an emitter electrode is formed to be contacted with the emitter region. An insulator is formed to surround the emitter electrode. A base electrode is formed not to be contacted with the intrinsic base region A conductive region is formed to be contacted with the intrinsic base region and the base electrode. The substructure has a recess formed on the surface area. The conductive region is produced by supplying a conductive material to the recess to be contacted with the intrinsic base region and the base electrode. The intrinsic base region is electrically connected to the base electrode through the conductive region.

Abstract: A high-frequency bipolar transistor structure includes a base region of a first conductivity type formed in a silicon layer of a second conductivity type, the base region comprising an intrinsic base region surrounded by an extrinsic base region, an emitter region of the second conductivity type formed inside the intrinsic base region, the extrinsic base region and the emitter region being contacted by a first polysilicon layer and a second polysilicon layer respectively. The first and the second polysilicon layers are respectively contacted by a base metal electrode and an emitter metal electrode. Between the extrinsic base region and the first polysilicon layer, a silicide layer is provided to reduce the extrinsic base resistance of the bipolar transistor.

Abstract: An ultrahigh speed bipolar transistor has a base region which is formed from a P.sup.+ base polysilicon sidewall using a self-alignment method, and a base junction window which is formed in order to minimize the collector-base junction capacity. In the method for fabricating this transistor, an insulation layer of oxide silicon or nitrogen silicon is formed under the base polysilicon layer. Accordingly, impurities from the base polysilicon layer do not diffuse into the epitaxial layer during the diffusion process. Instead, the extrinsic base region is formed by the diffusion of impurities from the polysilicon sidewall which is connected to the base polysilicon layer. Therefore the length of the entire base region is shortened. Furthermore, the junction area between the collector region is also lowered. Thus, the collector-base junction capacity is decreased and a higher operating speed is obtained.

Abstract: A method for manufacturing a bipolar junction transistor which includes the steps of forming spaced-apart base and collector regions in a surface region of a semiconductor substrate, forming a first insulating film on the semiconductor substrate, forming an emitter contact hole in the first insulating film, to thereby expose a first portion of the base region, forming a first conductive layer on the first insulating film and the exposed first portion of said base region, the first conductive layer being comprised of a first conductive material such as polysilicon, ion-implanting impurities into the first conductive layer, forming base and collector contact holes in a first resultant structure comprised of the first insulating film and the first conductive layer, to thereby expose a second portion of the base region spaced-apart from the first portion of the base region, and a portion of the collector region, respectively, forming a second conductive layer on a second resultant structure obtained by the preced

Abstract: A hole in the site for the emitter layer of the npn transistor of a complementary bipolar transistor is made in a step independent from a step of making a hole in the site for the emitter layer of the pnp transistor, and an n.sup.+ -type polycrystalline Si film doped with an n-type impurity upon being made is used to make the emitter electrode of the npn transistor. Independently from this step, a p.sup.+ -type polycrystalline Si film doped with a p-type impurity upon being made is used to make the emitter electrode of the pnp transistor. The n-type impurity diffusing from the emitter electrode makes an n.sup.+ -type emitter layer of the npn transistor, whereas the p-type impurity diffusing from the emitter electrode makes a p.sup.+ -type emitter layer of the pnp transistor. Thus the method can produce complementary bipolar transistors with a higher performance, and is suitable for combination with a process for fabricating sub-half-micron bipolar CMOSs.