Abstract: A method for forming a p-type halo implant as ROM cell isolation in a flat-cell mask ROM process is described. A P-well is formed within a semiconductor substrate and an oxide layer is formed overlying a surface of the substrate. A photomask is formed overlying the oxide layer wherein openings are left within the photomask exposing portions of the oxide layer. First, ions are implanted through the exposed portions of the oxide layer into the underlying semiconductor substrate whereby buried bit lines are formed. Thereafter, second ions are implanted through the exposed portions of the oxide layer whereby halo regions are formed encompassing the buried bit lines. The halo regions provide ROM isolation and punch-through protection for the buried bit lines. Thereafter, the photomask is removed and fabrication of flat-cell mask ROM device is completed.

Abstract: A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device between the P++ substrate and the P- epitaxial layer. A connecting p+ implant is placed within the epitaxial layer above the buried p+ blanket layer implant. In one exemplary embodiment, the device includes a shallow P-well with the P+ connecting implant in a position within the epitaxial layer connecting the shallow P-well and the buried P+ blanket implant layer.

Abstract: A semiconductor device having a structure including no LDD region while being structured in such a manner that fixed charges are charged in portions of a gate oxide film overlapping with side walls of a gate electrode formed on the gate oxide film so as to reduce the intensity of electric field between the source and drain of a transistor included in the semiconductor device. The charged-up positive or negative fixed charges serve to invert the conductivity of the channel region portion of a semiconductor substrate on which the gate oxide film is formed, thereby providing the same effect as the LDD region. The invention also provides a method for fabricating the semiconductor device.

Abstract: A semiconductor device having an electrostatic discharge protection device and at least one accompanying device selected from the group comprising of a N or P channel MOS transistor, CMOS, bipolar transistor and BiCMOS, in which the electrostatic discharge protection device comprises a vertical type bipolar transistor including; a semiconductor substrate; an epitaxial layer laminated on the semiconductor substrate; a buried collector of a first conductivity type which is formed of the semiconductor substrate or which is formed from the surface of the semiconductor substrate to the epitaxial layer; a base of a second conductivity type which is a lightly doped well and formed on the epitaxial layer; and an emitter of the first conductivity type and formed on the surface layer of the base of the second conductivity type; and in which the base is adapted to have impurity concentration and depth so that a punch-through is generated between the emitter and the collector of the electrostatic discharge protection dev

Abstract: A method for fabricating a CMOS device having BILLI (buried implanted layers for lateral isolation) structure capable of effectively preventing latch-up is disclosed, having the following steps. A mask pattern is formed on the semiconductor substrate of a predetermined conductivity type to expose a region where the MOS transistor, having a same conductivity type as that of the substrate, is to be formed wherein the mask pattern has a vertical boundary face having a gradual slope. A buried layer is then formed in the form of island by ion-implanting the impurity ions into the substrate to pass through the mask pattern, the buried layer having a same conductivity type as that of the substrate, and being formed to be continuous under the vertical boundary face of the mask pattern.

Abstract: A semiconductor device is provided in which a vertical NPN transistor and a vertical PNP transistor electrically isolated from each other are formed on a p-type semiconductor substrate. An n-type buried separating region of the vertical PNP transistor is formed by high-energy ion implantation after formation of the n.sup.+ type buried collector region of the vertical NPN transistor, and a p.sup.+ type buried collector region of the vertical PNP transistor is formed subsequently to formation of an n-type epitaxial layer and a device separating region whereby the thickness of the n-type epitaxial layer is optimized to a required minimum value. A method for producing a semiconductor device is also provided in which a first vertical bipolar transistor of a first conductivity type and a second vertical bipolar transistor of a second conductivity type, electrically isolated from each other, are formed on a semiconductor substrate having a pre-set conductivity type.

Abstract: To enable a high speed operation and to increase the current gain, the disclosed a method of manufacturing a semiconductor device, comprising the steps of: forming a first semiconductor layer with a first-conductivity type in a semiconductor substrate; forming a second semiconductor layer with a second-conductivity type different from the first-conductivity type on the first semiconductor layer; insulation separating the formed second semiconductor layer into a first semiconductor region and a second semiconductor region by an insulating film; changing the second semiconductor region to the first-conductivity type; forming a pattern of an insulating film or a photoresist film having a hole at a partial area of the first semiconductor region of the semiconductor substrate; and implanting first-conductivity type impurities and second-conductivity type impurities at the first semiconductor region, respectively by use of the formed pattern as a mask, to form a first-conductivity type impurity region contacting wi

Abstract: A method for forming a patterned photoresist layer. There is first provided a substrate. There is then formed over the substrate a blanket photoresist layer. The blanket photoresist layer is then implanted with a first ion beam to form an ion implanted blanket photoresist layer. The first ion beam employs a first ion having a first energy and a first dose sufficient such that an ion implanted patterned photoresist layer formed from the ion implanted blanket photoresist layer will not substantially outgas when the ion implanted patterned photoresist layer is exposed to a second beam. The ion implanted blanket photoresist layer is then patterned to form the ion implanted patterned photoresist layer. The method may be employed in selective high energy beam processing of the substrate. The method is particularly suited to selective high energy ion implant processing of semiconductor substrates employed within integrated circuit microelectronics fabrications.

Abstract: In an NPN bipolar transistor having a special structure in which each impurity region is formed by ion implantation, a width of a base region is significantly reduced, and therefore, current amplification factor hfe is increased, resulting in improvement in performance thereof. Furthermore, a Bi-CMOS transistor can be manufactured using a CMOS process. The use of the bipolar transistor having a special structure for a driving circuit allows implementation of a driving circuit having large driving force with slight increase in cost.

Abstract: A first photoresist layer has opening portions in a region where an n-channel MOS transistor should be formed and in a region where a collector leading region should be formed. Then, phosphorous is implanted with taking the first photoresist layer as a mask. The first photoresist layer is then removed and a second photoresist layer is formed. The second photoresist layer has opening portions in a region where an emitter region should be formed and in the region where the collector leading region should be formed. Phosphorous is implanted with taking the second photoresist layer as a mask to form an n-type selective diffusion region in a region below the region where the emitter region should be formed and in the region where the collector leading region should be formed. Then, the second photoresist layer is removed. A polycrystalline silicon layer is formed over the entire surface and arsenic is implanted therein to make it n-type.

Abstract: A bipolar transistor with a relatively deep emitter region is formed in a BICMOS device using the source/drain mask used to form the source and drain regions of MOSFETs of the device and the base region mask which would otherwise be required in any event to diffuse an emitter region of the bipolar transistor. The emitter is diffused or implanted to a depth greater than the depth to which a source and a drain region of the MOSFET are diffused. By using only the base region and source/drain region masks, and developing in sequence, each of two coatings of photoresist applied on top of one another, an access opening to the emitter region is define solely by the co-location of openings in each of the two coatings, thereby allowing the emitter region to be separately and additionally implanted. The access to the base region for the additional implication is achieved using only a few additional photo-ops and not as a result of using an additional emitter mask.

Abstract: A semiconductor device (10) is formed in a semiconductor substrate (11) that acts as a collector region. A base region (12) is formed in the semiconductor substrate (11) and an emitter region (52) is formed such that it contacts at least a portion of the base region (12). A conductive layer (28) is used to provide electrical connection to the emitter region (52). The portion of the conductive layer (28) above the emitter region (52) is counter-doped to address the problems of an interfacial oxide layer (27) that exists between the emitter region (52) and the conductive layer (28).

Abstract: It is the object of the invention to provide a method for fabricating a semiconductor device, such as a bipolar transistor, with improved characteristics when used in a semiconductor integrated circuit, without increasing the steps in fabricating process. In forming the graft base of the bipolar transistor, oxygen ions with higher energy than that of impurities are injected through the same mask. Thereafter, an insulating film is formed under the graft base region, by activating thermal treatment. Moreover, in a semiconductor integrated circuit of BiCMOS type, insulation films are formed under a source and a drain of a P-type transistor.