Lightly Doped Junction Isolated Resistor Patents (Class 438/383)
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Patent number: 11887945Abstract: The present disclosure relates to a semiconductor device with isolation and/or protection structures. A semiconductor device can include a substrate, a first transistor and a second transistor, wherein the first transistor and the second transistor are formed on the substrate, and an isolation structure formed on the substrate. The isolation structure can be formed on the substrate between the first transistor and the second transistor. The isolation structure can be configured to isolate the first transistor and the second transistor.Type: GrantFiled: September 30, 2020Date of Patent: January 30, 2024Assignee: WOLFSPEED, INC.Inventors: Lei Zhao, Fabian Radulescu
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Patent number: 11800822Abstract: A memory device includes a bottom electrode, a magnetic tunnel junction (MTJ) structure, an inner spacer, and an outer spacer. The MTJ structure is over the bottom electrode. The bottom electrode has a top surface extending past opposite sidewalls of the MTJ structure. The inner spacer contacts the top surface of the bottom electrode and one of the opposite sidewalls of the MTJ structure. The outer spacer contacts an outer sidewall of the inner spacer. The outer spacer protrudes from a top surface of the inner spacer by a step height.Type: GrantFiled: January 10, 2022Date of Patent: October 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu
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Patent number: 11658227Abstract: A method for manufacturing a semiconductor structure is provided. The method comprises the following steps. A first silicon-containing gate electrode is formed on a semiconductor substrate in a first region. A second silicon-containing gate electrode is formed on the semiconductor substrate in a second region. A gate silicide element is formed on an upper surface of the first silicon-containing gate electrode. A source silicide element and a drain silicide element are formed on the semiconductor substrate on opposing sides of the second silicon-containing gate electrode respectively. The gate silicide element, the source silicide element and the drain silicide element are formed simultaneously.Type: GrantFiled: January 6, 2022Date of Patent: May 23, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Pei-Lun Jheng, Chao-Sheng Cheng
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Patent number: 10014379Abstract: One method disclosed includes forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers, removing a portion of the sidewall spacers to define recessed sidewall spacers, removing a portion of the final gate structure to define a recessed final gate structure and forming an etch stop on the recessed sidewall spacers and the recessed final gate structure. A transistor device disclosed herein includes a final gate structure that has an upper surface positioned at a first height level above a surface of a substrate, sidewall spacers positioned adjacent the final gate structure, the sidewall spacers having an upper surface that is positioned at a second, greater height level above the substrate, an etch stop layer formed on the upper surfaces of the sidewall spacers and the final gate structure, and a conductive contact that is conductively coupled to a contact region of the transistor.Type: GrantFiled: October 29, 2014Date of Patent: July 3, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Xiuyu Cai
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Patent number: 8962421Abstract: A method for fabricating a FinFET integrated circuit includes depositing a first polysilicon layer at a first end of a diffusion region and a second polysilicon layer at a second end of the diffusion region; diffusing an n-type material into the diffusion region to form a diffused resistor; and epitaxially growing a silicon material between the first and second polysilicon layers to form fins structures over the diffused resistor and spanning between the first and second polysilicon layers.Type: GrantFiled: November 15, 2012Date of Patent: February 24, 2015Assignee: GLOBALFOUNDRIES, Inc.Inventors: Gopal Srinivasan, Andy Wei, Dinesh Somasekhar, Ali Keshavarzi, Subi Kengeri
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Patent number: 8946039Abstract: Aspects of the present invention relate to an approach for implanting and forming a polysilicon resistor with a single implant dose. Specifically, a mask having a set of openings is formed over a resistor surface. The set of openings are typically formed in a column-row arrangement according to a predetermined pattern. Forming the mask in this manner allows the resistor surface to have multiple regions/zones. A first region is defined by the set of openings in the mask, and a second region is defined by the remaining portions of the mask. The resistor is then subjected to a single implant dose via the openings. Implanting the resistor in this manner allows the resistor to have multiple resistance values (i.e., a first resistance value in the first region, and a second resistance value in the second region).Type: GrantFiled: February 15, 2013Date of Patent: February 3, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Jagar Singh, Shesh Mani Pandey, Roderick Miller, Nam Sung Kim
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Patent number: 8928043Abstract: A high voltage FET device provides drain voltage information with less overall silicon area consumption by forming a spiral resistance poly structure over a drift region of the high voltage FET device. The spiral resistance poly structure has an inner most end coupled to a drain region, and an outer most end coupled to a reference ground.Type: GrantFiled: April 25, 2013Date of Patent: January 6, 2015Assignee: Monolithic Power Systems, Inc.Inventor: Joseph Urienza
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Patent number: 8823137Abstract: A semiconductor device includes first and second wells formed side by side as impurity diffusion regions of a first conductive type in a semiconductor substrate, below an intermediate dielectric film that covers a major surface of the substrate. A conductive layer formed above the intermediate dielectric film is held at a potential. A first resistive layer is formed on the intermediate dielectric film and is electrically connected to the first well. A second resistive layer is formed on the intermediate dielectric film and is electrically connected to the second well. The first resistive layer and first well form a first resistance element. The second resistive layer and second well form a second resistance element.Type: GrantFiled: June 18, 2013Date of Patent: September 2, 2014Assignee: LAPIS Semiconductor Co., Ltd.Inventors: Hidekazu Kikuchi, Hisao Ohtake, Danya Sugai
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Patent number: 8772121Abstract: A method of manufacturing a phase change memory device includes forming a lower electrode layer pattern and an insulating interlayer covering the lower electrode layer pattern, forming a first opening in the insulating interlayer to expose the lower electrode layer pattern, forming an oxide layer pattern on the sidewall of the first opening and a lower electrode under the oxide layer pattern by partially removing the oxide layer and the lower electrode layer pattern, forming an insulation layer filling a remaining portion of the first opening, removing the oxide layer pattern by a wet etching process to form a second opening, and forming a phase change material pattern on the lower electrode such that the phase change material pattern fills the second opening.Type: GrantFiled: April 10, 2012Date of Patent: July 8, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-Man Hwang, Jun-Soo Bae, Sung-Un Kwon, Kwang-Ho Park
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Patent number: 8748934Abstract: The present disclosure discloses a vertical selection transistor, a memory cell having the vertical selection transistor, a three-dimensional memory array structure and a method for fabricating the three-dimensional memory array structure. The vertical selection transistor comprises: an upper electrode; a lower electrode; a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer vertically stacked between the lower electrode and the upper electrode; and a gate stack formed on a side of the second semiconductor layer, in which the first semiconductor layer and the third semiconductor layer are first type doped layers, the second semiconductor layer and the fourth semiconductor layer are second type doped layers, and a doping concentration of the second semiconductor layer is lower than that of the first semiconductor layer or that of the third semiconductor layer respectively.Type: GrantFiled: March 12, 2012Date of Patent: June 10, 2014Assignee: Tsinghua UniversityInventors: Liyang Pan, Fang Yuan
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Patent number: 8735294Abstract: A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device includes a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one implementation, a method for fabricating a vertically arranged LDMOS device includes forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material.Type: GrantFiled: October 25, 2012Date of Patent: May 27, 2014Assignee: International Rectifier CorporationInventor: Igor Bol
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Patent number: 8685827Abstract: A method for manufacturing a semiconductor device, comprising forming a first gate stack portion on a substrate, the first gate stack portion including a first gate oxide layer and a first polysilicon layer on the first gate oxide layer, forming a second gate stack portion on the substrate, the second gate stack portion including a second gate oxide layer and a second polysilicon layer on the second gate oxide layer, forming a resistor portion on the substrate, the resistor portion including a third gate oxide layer and a third polysilicon layer on the third gate oxide layer, covering the resistor portion with a photoresist, removing respective first portions of the first and second polysilicon layers from the first and second gate stack portions, removing the photoresist from the resistor portion, and after removing the photoresist from the resistor portion, removing respective remaining portions of the first and second polysilicon layers from the first and second gate stack portions.Type: GrantFiled: July 13, 2011Date of Patent: April 1, 2014Assignee: Samsung Electronics Co., LtdInventors: Ju Youn Kim, Jedon Kim
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Patent number: 8679932Abstract: A system and method is disclosed for manufacturing thin film resistors using a trench and chemical mechanical polishing. A trench is etched in a layer of dielectric material and a thin film resistor layer is deposited so that the thin film resistor layer lines the trench. A thin film resistor protection layer is then deposited to fill the trench. Then a chemical mechanical polishing process removes excess portions of the thin film resistor layer and the thin film resistor protection layer. An interconnect metal is then deposited and patterned to create an opening over the trench. A central portion of the thin film resistor protection material is removed down to the thin film resistor layer at the bottom of the trench. The resulting structure is immune to the effects of topography on the critical dimensions (CDs) of the thin film resistor.Type: GrantFiled: January 30, 2006Date of Patent: March 25, 2014Assignee: National Semiconductor CorporationInventor: Rodney Hill
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Publication number: 20140057407Abstract: Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities.Type: ApplicationFiled: November 7, 2013Publication date: February 27, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chang Cheng, Ruey-Hsin Liu, Chih-Wen Yao, Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai
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Patent number: 8652921Abstract: A semiconductor device has a substrate that includes a cell array region and a dummy pattern region surrounding the cell array region. The cell array region includes a cell structure having a plurality of cell active pillars extending in a vertical direction from the cell array region of the substrate and includes cell gate patterns and cell gate interlayer insulating patterns alternately stacked on the substrate. The cell gate patterns and cell gate interlayer insulating patterns have sides facing the cell active pillars. The dummy pattern region includes a damp-proof structure.Type: GrantFiled: February 5, 2013Date of Patent: February 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Jun Lee, Woonkyung Lee
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Patent number: 8481397Abstract: A method is provided for making a resistive polycrystalline semiconductor device, e.g., a poly resistor of a microelectronic element such as a semiconductor integrated circuit. The method can include: (a) forming a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, a first polycrystalline semiconductor region adjacent the metal gate layer having a predominant dopant type of either n or p, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region; and (b) forming first and second contacts in conductive communication with the second polycrystalline semiconductor region, the first and second contacts being spaced apart so as to achieve a desired resistance.Type: GrantFiled: March 8, 2010Date of Patent: July 9, 2013Assignee: International Business Machines CorporationInventors: Roger A. Booth, Jr., Kangguo Cheng, Rainer Loesing, Chengwen Pei, Xiaojun Yu
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Patent number: 8482100Abstract: A resistor array includes a semiconductor substrate, a plurality of isolation regions, a plurality of dummy active regions and a plurality of unit resistors. The plurality of isolation regions are formed in the semiconductor substrate. The plurality of dummy active regions are formed in the semiconductor substrate between the plurality of isolation regions. The plurality of unit resistors are formed on the plurality of dummy active regions.Type: GrantFiled: September 1, 2011Date of Patent: July 9, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Young-Jin Cho
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Patent number: 8426287Abstract: A method of manufacturing a semiconductor device includes the steps of forming a gate electrode of a transistor on an insulator layer on a surface of a semiconductor substrate, forming an isolation region by performing ion implantation of an impurity of a first conductivity type into the semiconductor substrate, forming a lightly doped drain region by performing, after forming a mask pattern including an opening portion narrower than a width of the gate electrode on an upper layer of the gate electrode of the transistor, ion implantation of an impurity of a second conductivity type near the surface of the semiconductor substrate with the mask pattern as a mask, and forming a source region and a drain region of the transistor by performing ion implantation of an impurity of the second conductivity type into the semiconductor substrate after forming the gate electrode of the transistor.Type: GrantFiled: November 12, 2010Date of Patent: April 23, 2013Assignee: Sony CorporationInventor: Masashi Yanagita
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Patent number: 8334187Abstract: Methods of fabricating an integrated circuit device, such as a thin film resistor, are disclosed. An exemplary method includes providing a semiconductor substrate; forming a resistive layer over the semiconductor substrate; forming a hard mask layer over the resistive layer, wherein the hard mask layer includes a barrier layer over the resistive layer and a dielectric layer over the barrier layer; and forming an opening in the hard mask layer that exposes a portion of the resistive layer.Type: GrantFiled: June 28, 2010Date of Patent: December 18, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wen Chang, Der-Chyang Yeh, Chung-Yi Yu, Hsun-Chung Kuang, Hua-Chou Tseng, Chih-Ping Chao, Ming Chyi Liu, Yuan-Tai Tseng
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Publication number: 20120175749Abstract: A structure comprises first and at least second fin structures are formed. Each of the first and at least second fin structures has a vertically oriented semiconductor body. The vertically oriented semiconductor body is comprised of vertical surfaces. A doped region in each of the first and at least second fin structures is comprised of a concentration of dopant ions present in the semiconductor body to form a first resistor and at least a second resistor, and a pair of merged fins formed on outer portions of the doped regions of the first and at least second fin structures. The pair of merged fins is electrically connected so that the first and at least second resistors are electrically connected in parallel with each other.Type: ApplicationFiled: January 6, 2011Publication date: July 12, 2012Applicant: International Business Machines CorporationInventors: Wilfried E. Haensch, Pranita Kulkarni, Tenko Yamashita
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Patent number: 8183107Abstract: Semiconductor devices are formed with reduced variability between close proximity resistors, improved end resistances, and reduced random dopant mismatch. Embodiments include ion implanting a dopant, such as B, at a relatively high dosage, e.g. about 4 to about 6 keV, and at a relatively low implant energy, e.g., about 1.5 to about 2E15/cm2.Type: GrantFiled: May 27, 2009Date of Patent: May 22, 2012Assignee: Globalfoundries Inc.Inventors: Kaveri Mathur, James F. Buller, Andreas Kurz
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Publication number: 20120112823Abstract: An integrated circuit with a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. A method for forming a matching resistance heater. A method for operating an SOI integrated circuit containing a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair.Type: ApplicationFiled: November 3, 2011Publication date: May 10, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Andrew Marshall
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Publication number: 20120083091Abstract: A semiconductor includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.Type: ApplicationFiled: December 13, 2011Publication date: April 5, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John E. Barth, JR., Kerry Bernstein
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Patent number: 8143674Abstract: A semiconductor device having a resistor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a first circuit region and a second circuit region. A lower interlayer insulating layer is provided over the semiconductor substrate. A first hole passing through the lower interlayer insulating layer in the first circuit region and a second hole passing through the lower interlayer insulating layer in the second circuit region are provided. A first semiconductor pattern and a second semiconductor pattern are sequentially stacked in the first hole. A first resistor having the same crystalline structure as the second semiconductor pattern is provided in the second hole.Type: GrantFiled: December 20, 2010Date of Patent: March 27, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Won Ha, Sang-Yoon Kim
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Patent number: 7928515Abstract: A semiconductor device includes a dual gate CMOS logic circuit having gate electrodes with different conducting types and a trench capacitor type memory on a same substrate includes a trench of the substrate for the trench capacitor, a dielectric film formed in the trench, a first poly silicon film formed inside of the trench, and a cell plate electrode located above the dielectric film. The cell plate electrode includes a first poly silicon film formed on the dielectric film partially filling the trench, and a second poly silicon film formed on the first poly silicon film to completely fill the trench. The second poly silicon film includes a sufficient film thickness for forming gate electrodes, wherein the impurity concentration of the first poly silicon film is higher than the impurity concentration of the second poly silicon film.Type: GrantFiled: June 11, 2008Date of Patent: April 19, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Masayoshi Asano, Yoshiyuki Suzuki, Tetsuya Ito, Hajime Wada
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Patent number: 7871890Abstract: A semiconductor device having a resistor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a first circuit region and a second circuit region. A lower interlayer insulating layer is provided over the semiconductor substrate. A first hole passing through the lower interlayer insulating layer in the first circuit region and a second hole passing through the lower interlayer insulating layer in the second circuit region are provided. A first semiconductor pattern and a second semiconductor pattern are sequentially stacked in the first hole. A first resistor having the same crystalline structure as the second semiconductor pattern is provided in the second hole.Type: GrantFiled: October 9, 2008Date of Patent: January 18, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Won Ha, Sang-Yoon Kim
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Patent number: 7732293Abstract: A diode structure fabrication method. In a P? substrate, an N+ layer is implanted. The N+ layer has an opening whose size affects the breakdown voltage of the diode structure. Upon the N+ layer, an N? layer is formed. Then, a P+ region is formed to serve as an anode of the diode structure. An N+ region can be formed on the surface of the substrate to serve as a cathode of the diode structure. By changing the size of the opening in the N+ layer during fabrication, the breakdown voltage of the diode structure can be changed (tuned) to a desired value.Type: GrantFiled: August 4, 2008Date of Patent: June 8, 2010Assignee: International Business Machines CorporationInventor: Steven H. Voldman
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Patent number: 7691717Abstract: A polysilicon containing resistor includes: (1) a p dopant selected from the group consisting of boron and boron difluoride; and (2) an n dopant selected from the group consisting of arsenic and phosphorus. Each of the p dopant and the n dopant has a dopant concentration from about 1e18 to about 1e21 dopant atoms per cubic centimeter. A method for forming the polysilicon resistor uses corresponding implant doses from about 1e14 to about 1e16 dopant ions per square centimeter. The p dopant and the n dopant may be provided simultaneously or sequentially. The method provides certain polysilicon resistors with a sheet resistance percentage standard deviation of less than about 1.5%, for a polysilicon resistor having a sheet resistance from about 100 to about 5000 ohms per square.Type: GrantFiled: July 19, 2006Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, Ebenezer E. Eshun, John E. Florkey, Robert M. Rassel, Kunal Vaed
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Publication number: 20100052100Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.Type: ApplicationFiled: August 29, 2008Publication date: March 4, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John E. Barth, JR., Kerry Bernstein
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Patent number: 7611957Abstract: The invention provides a method of manufacturing a semiconductor device having a semiconductor resistor layer, which reduces a difference between a theoretical resistance value and a measured resistance value. An interlayer insulation film is formed on the whole surface of a semiconductor substrate, and then the interlayer insulation film is selectively etched to form contact holes partially exposing a polysilicon resistor layer, a source region and a drain region. The patterning size of the polysilicon resistor layer is designed by defining the lengths between the adjacent contact holes on the polysilicon resistor layer as the lengths of resistor elements. Then, ion implantation is performed to the polysilicon resistor layer through the contact holes to form low resistance regions (regions where high concentration of impurities are implanted) on the polysilicon resistor layer.Type: GrantFiled: January 30, 2007Date of Patent: November 3, 2009Assignee: Sanyo Electric Co., Ltd.Inventors: Eiji Nishibe, Toshihiro Hachiyanagi
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Publication number: 20090242997Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.Type: ApplicationFiled: March 28, 2008Publication date: October 1, 2009Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Tian-Fu Chiang, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
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Publication number: 20090098703Abstract: A semiconductor device having a resistor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a first circuit region and a second circuit region. A lower interlayer insulating layer is provided over the semiconductor substrate. A first hole passing through the lower interlayer insulating layer in the first circuit region and a second hole passing through the lower interlayer insulating layer in the second circuit region are provided. A first semiconductor pattern and a second semiconductor pattern are sequentially stacked in the first hole. A first resistor having the same crystalline structure as the second semiconductor pattern is provided in the second hole.Type: ApplicationFiled: October 9, 2008Publication date: April 16, 2009Inventors: Dae-Won Ha, Sang-Yoon Kim
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Publication number: 20090090977Abstract: An integrated semiconductor device includes a resistor and an FET device formed from a stack of layers. The stack of layers includes a dielectric layer formed on a substrate; a metal conductor layer having lower electrical resistance formed on the dielectric layer; and a polysilicon layer formed on the metal conductor layer. A resistor stack is formed by patterning a portion of the original stack of layers into a resistor. An FET stack is formed from another portion of the original stack of layers. The FET stack is doped to form a gate electrode and the resistor stack is doped aside from the resistor portion thereof. Then terminals are formed at distal ends of the resistor in a doped portion of the polysilicon layer. Alternatively, the polysilicon layer is etched away from the resistor stack followed by forming terminals at distal ends of the metal conductor in the resistor stack.Type: ApplicationFiled: October 9, 2007Publication date: April 9, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory G. Freeman, William K. Henson
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Patent number: 7504292Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, and epitaxially growing a lightly-doped source/drain (LDD) region adjacent the gate stack, wherein carbon is simultaneously doped into the LDD region.Type: GrantFiled: December 5, 2006Date of Patent: March 17, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Keh-Chiang Ku, Pang-Yen Tsai, Chun-Feng Nieh, Li-Ting Wang
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Publication number: 20080315319Abstract: A semiconductor device includes a dual gate CMOS logic circuit having gate electrodes with different conducting types and a trench capacitor type memory on a same substrate includes a trench of the substrate for the trench capacitor, a dielectric film formed in the trench, a first poly silicon film formed inside of the trench, and a cell plate electrode located above the dielectric film. The cell plate electrode includes a first poly silicon film formed on the dielectric film partially filling the trench, and a second poly silicon film formed on the first poly silicon film to completely fill the trench. The second poly silicon film includes a sufficient film thickness for forming gate electrodes, wherein the impurity concentration of the first poly silicon film is higher than the impurity concentration of the second poly silicon film.Type: ApplicationFiled: June 11, 2008Publication date: December 25, 2008Applicant: FUJITSU LIMITEDInventors: Masayoshi ASANO, Yoshiyuki SUZUKI, Tetsuya ITO, Hajime WADA
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Patent number: 7439145Abstract: A diode structure fabrication method. In a P? substrate, an N+ layer is implanted. The N+ layer has an opening whose size affects the breakdown voltage of the diode structure. Upon the N+ layer, an N? layer is formed. Then, a P+ region is formed to serve as an anode of the diode structure. An N+ region can be formed on the surface of the substrate to serve as a cathode of the diode structure. By changing the size of the opening in the N+ layer during fabrication, the breakdown voltage of the diode structure can be changed (tuned) to a desired value.Type: GrantFiled: September 1, 2006Date of Patent: October 21, 2008Assignee: International Business Machines CorporationInventor: Steven H. Voldman
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Patent number: 7419881Abstract: In a phase changeable memory device and a method of formation thereof, the phase changeable memory device comprises: a lower electrode pattern on an interlayer insulating layer; an insulating pattern located on the lower electrode pattern; a phase changeable pattern penetrating the insulating pattern and the lower electrode pattern to contact the lower electrode pattern and the interlayer insulating layer; and an upper electrode on the phase changeable pattern.Type: GrantFiled: October 18, 2005Date of Patent: September 2, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Byeong-Ok Cho, Suk-Ho Joo, Kyung-Chang Ryoo, Kyung-Rae Byun
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Publication number: 20080122574Abstract: A polysilicon containing resistor includes: (1) a p dopant selected from the group consisting of boron and boron difluoride; and (2) an n dopant selected from the group consisting of arsenic and phosphorus. Each of the p dopant and the n dopant has a dopant concentration from about 1e18 to about 1e21 dopant atoms per cubic centimeter. A method for forming the polysilicon resistor uses corresponding implant doses from about 1e14 to about 1e16 dopant ions per square centimeter. The p dopant and the n dopant may be provided simultaneously or sequentially. The method provides certain polysilicon resistors with a sheet resistance percentage standard deviation of less than about 1.5%, for a polysilicon resistor having a sheet resistance from about 100 to about 5000 ohms per square.Type: ApplicationFiled: July 19, 2006Publication date: May 29, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, Ebenezer E. Eshun, John E. Florkey, Robert M. Rassel, Kunal Vaed
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Patent number: 7323751Abstract: A thin film resistor and at least one metal interconnect are formed in an integrated circuit. A first dielectric layer is formed over a metal interconnect layer. A thin film resistor is formed on the first dielectric layer and a second dielectric layer formed over the thin film resistor. Thin film resistor vias and the at least one trench are formed concurrently in the second dielectric layer. A trench via is then formed in the at least one trench. The trench via, the at least one trench and the thin film resistor vias are filled with a contact material layer to form thin film resistor contacts and at least one conductive line coupled to the metal interconnect layer.Type: GrantFiled: June 3, 2003Date of Patent: January 29, 2008Assignee: Texas Instruments IncorporatedInventors: Eric Williams Beach, Rajneesh Jaiswal
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Patent number: 7307024Abstract: A flash memory and a fabrication method thereof, which is capable of improving a whole capacitance of the flash memory by forming a tunneling oxide and a floating gate only in a portion where injection of electrons occurs. A flash memory wherein a tunneling oxide and a floating gate are formed only in a portion where injection of electrons occurs and a gate insulation film is formed on a semiconductor substrate between two portions of the tunneling oxide.Type: GrantFiled: December 30, 2003Date of Patent: December 11, 2007Assignee: Dongbu Hitek Co., Ltd.Inventor: Geon-Ook Park
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Patent number: 7300836Abstract: This invention is directed to a manufacturing method of a semiconductor device having a MOS transistor and a diffusion resistance layer formed on a same semiconductor substrate, where current leakage from the diffusion resistance layer is minimized. The manufacturing method of the semiconductor device of the invention has following features. That is, a CVD insulation film is formed on a whole surface of an n-type well including on a gate electrode and a p+-type diffusion resistance layer formed thereon. Then, a second photoresist layer is formed having an opening above a part of the diffusion resistance layer. By using this second photoresist layer as a mask, an anisotropic etching is performed to the CVD insulation film to form a sidewall spacer on a sidewall of the gate electrode.Type: GrantFiled: December 15, 2004Date of Patent: November 27, 2007Assignee: Sanyo Electric Co., Ltd.Inventor: Yoshihiko Miyawaki
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Patent number: 7250333Abstract: A method and apparatus for a linearized output driver and terminator is described. In one embodiment the method includes forming a gate electrode on a substrate, the portion of the substrate covered by the gate electrode defining a channel. The method further includes forming a first source/drain doped region on laterally opposed sides of the gate electrode in the substrate. The method also includes forming a spacer on laterally opposed sides of the gate electrode on the substrate. The method also includes forming a linearized drain contact region at a location within the first source/drain doped region sufficiently distant from the gate electrode to define a series resistor in the first source/drain doped region disposed between the gate electrode and the linearized drain contact area based on an expected resistivity of the source/drain doped region, the series resistor coupled electrically to the channel.Type: GrantFiled: March 20, 2003Date of Patent: July 31, 2007Assignee: Intel CorporationInventors: Sanjay Dabral, Krishna Seshan
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Patent number: 7163868Abstract: In accordance with the present invention, a gate electrode structure with inclined planes is used as a mask when performing an ion implantation process. The inclined planes are used to define the lightly doped drain (LDD) region in the active area. Therefore, the width of the LDD can be defined by the geometry of the inclined planes.Type: GrantFiled: June 8, 2004Date of Patent: January 16, 2007Assignee: Chunghwa Picture Tubes, Ltd.Inventor: Te-Ming Chu
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Patent number: 7135367Abstract: A silicon oxide film as an insulating film is accumulated so as to cover a whole surface of a silicon substrate including a surface of a resistance element by, for example, a thermal CVD method, just after a resist pattern is removed. This silicon oxide film is processed to form a silicide block on the resistance element, and side wall spacers at both side surfaces of gate electrodes, and so on, of respective transistors, at the same time.Type: GrantFiled: May 31, 2005Date of Patent: November 14, 2006Assignee: Fujitsu LimitedInventors: Tomohiko Tsutsumi, Taiji Ema, Hideyuki Kojima, Toru Anezaki
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Patent number: 7071070Abstract: A method of fabricating a capacitor is described. A dielectric layer is formed over a substrate. An upper electrode having multiple openings therein is formed over the dielectric layer. Then, a doping step is performed to the substrate through the openings to form a single doped region as a lower electrode in the substrate under the upper electrode.Type: GrantFiled: September 24, 2004Date of Patent: July 4, 2006Assignee: United Microelectronics Corp.Inventor: Jing-Horng Gau
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Patent number: 7064414Abstract: A structure and associated method for annealing a trapped charge from a semiconductor device. The semiconductor structure comprises a substrate and a first heating element. The substrate comprises a bulk layer, an insulator layer and a device layer. The first heating element is formed within the bulk layer. A first side of the first heating element is adjacent to a first portion of the insulator layer. The first heating element is adapted to be selectively activated to generate thermal energy to heat the first portion of the insulator layer and anneal a trapped electrical charge from the first portion of the insulator layer.Type: GrantFiled: November 12, 2004Date of Patent: June 20, 2006Assignee: International Business Machines CorporationInventors: John M Aitken, Ethan H. Cannon, Philip J. Oldiges, Alvin W. Strong
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Patent number: 7059859Abstract: In a semiconductor device having a MOS transistor and a diffused resistor layer, a leakage current of a diffused resistor layer is suppressed. A film of gate electrode material is formed over the entire surface of an N-type well, a photoresist layer is formed to mask a region to form a gate electrode and portions of the diffused resistor layer and the gate electrode and a damage prevention films are formed by anisotropically etching the film of gate electrode material. After forming a CVD insulation film over the entire surface of the N-type well, sidewall spacers are formed on sidewalls of the gate electrode and the damage prevention films by anisotropically etching the CVD insulation film. A source layer and a drain layer of the MOS transistor and contact regions to the diff-used resistor layer are formed by doping portions of the N-type well and the diffused resistor layer with high concentration P-type impurities using the gate electrode, the damage prevention film and the sidewall spacers as a mask.Type: GrantFiled: January 21, 2005Date of Patent: June 13, 2006Assignee: Sanyo Electric Co., Ltd.Inventor: Yoshihiko Miyawaki
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Patent number: 7029956Abstract: A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure over the SiC substrate.Type: GrantFiled: September 19, 2003Date of Patent: April 18, 2006Assignee: International Business Machines Corp.Inventors: Louis L. Hsu, Li-Kong Wang
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Patent number: 7002235Abstract: A semiconductor device has a semiconductor support substrate, a buried insulation film disposed on the semiconductor support substrate, and a single-crystal silicon active layer disposed on the buried insulation film. The buried insulation film has portions which have been removed so that remaining portions of the buried insulating film form buried insulating film island regions. The single-crystal silicon active layer has portions which have been removed so that remaining portions of the single-crystal silicon active layer form single-crystal silicon active layer island regions defining single-crystal silicon resistors of a resistance circuit.Type: GrantFiled: March 24, 2003Date of Patent: February 21, 2006Assignee: Seiko Instruments Inc.Inventor: Hisashi Hasegawa
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Patent number: 6984869Abstract: The present invention provides a diffusion resistor that is formed in the substrate. A diffusion region is formed within the substrate that contains first and second contact regions extending downward from the surface of the substrate. Third and fourth contacts are also located within the diffusion region between the first and second contacts and define a conduction channel therebetween. This contact also extends downward from the surface of the substrate. These contacts are connected to metal layers. The first and second contacts form the two ends of the diffusion resistor; the third and fourth contacts connect to N+p? diodes such that application of a voltage to these contacts forms respective depletion regions within the diffusion region. The depletion regions change in size depending on the voltage applied to their respective contact, thereby changing the resistance of the depletion resistor.Type: GrantFiled: December 8, 2003Date of Patent: January 10, 2006Assignee: LSI Logic CorporationInventors: Sean Christopher Erickson, Kevin Roy Nunn, Jonathan Alan Shaw