Abstract: An inductor structure and a manufacturing method for the same are provided. The inductor structure includes conductive layers and conductive elements. The conductive layers overlap in a vertical direction. Each of the conductive elements is coupled between two conductive layers of the conductive layers.

Abstract: A method for forming a capacitor array structure includes the following operations. A base is formed, which includes a substrate, a stack structure located on the substrate and a mask layer located on the stack structure in which an etching window that penetrates the mask layer in a direction perpendicular to the substrate is provided. The stack structure is etched along the etching window to form a capacitor hole that penetrates the stack structure along the direction perpendicular to the substrate. A conductive layer that fills up the capacitor hole and the etching window and covers a top surface of the mask layer is formed. The conductive layer and the mask layer at a top surface of the stack structure are removed, and the conductive layer remaining in the capacitor hole forms a lower electrode.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a first nitride layer, a first sacrificial layer, a second nitride layer, a second sacrificial layer and a third nitride layer in sequence over the substrate; forming a first opening and a second opening, wherein the first opening exposes a first landing pad in the substrate, and the second opening exposes a second landing pad in the substrate; forming a first electrode in the first opening and a second electrode in the second opening; removing the first sacrificial layer and the second sacrificial layer concurrently; and forming a conductive layer, conformal to the first electrode, the second electrode, the first nitride layer, the second nitride layer and the third nitride layer.

Abstract: A semiconductor device includes a substrate, conductive features on the substrate, and a passivation layer over the conductive features to define conductive pads in the respective conductive features through exposed portions of each of the conductive features. Each corner of the conductive pads is free of right angle, the substrate has a pair of long sides from a top view perspective, the shape of each of the conductive pads is a parallelogram. Each of the conductive pads has a pair of long sides and a pair of short sides from a top view perspective, a portion of the conductive pads have the long sides sloped away from a first pad density area of the substrate and toward one long side of the substrate, and the rest of the conductive pads have the long sides sloped toward the first pad density area and toward the other long side of the substrate.

Abstract: A capacitor includes a plurality of lower bottom electrodes, a lower supporter supporting the lower bottom electrodes and including a plurality of lower supporter openings, upper bottom electrodes formed on the lower bottom electrodes, respectively, and an upper supporter supporting the upper bottom electrodes and including a plurality of upper supporter openings, wherein the lower supporter openings and the upper supporter openings do not vertically overlap each other.

Abstract: A memory cell and formation thereof. The memory cell including: a first dielectric material having a via; a dielectric spacer on a sidewall of the via, and a second dielectric material pinching off the via and forming a seam.

Abstract: Semiconductor devices are provided. A semiconductor device includes a first portion of a lower electrode structure on a substrate. The semiconductor device includes a first support pattern being in contact with a first portion of a sidewall of the first portion of the lower electrode structure. The semiconductor device includes a second portion of the lower electrode structure on a second portion of the sidewall of the first portion of the lower electrode structure. The semiconductor device includes an upper electrode on the second portion of the lower electrode structure and on the first support pattern. Moreover, the semiconductor device includes a dielectric layer between the upper electrode and the second portion of the lower electrode structure.

Abstract: A coil component includes a support substrate; first and second coil portions, respectively arranged on the support substrate; a body embedding the support substrate and the first and second coil portions therein; first and second lead-out portions, respectively connected to end portions of the first and second coil portions and exposed from one surface to be spaced apart from each other; and first and second connection portions, respectively connecting the end portions of the first and second coil portions to the first and second lead-out portions, wherein a line width of one end of each of the first and second connection portions connected to the respective end portion of the first and second coil portions is smaller than a line width of another end of each of the first and second connection portions connected to a respective one of the first and second lead-out portions.

Abstract: A method for fabricating a semiconductor device, including the steps of: providing a substrate having an etch stop layer formed thereon; forming a preliminary stacked structure on the etch stop layer, the preliminary stacked structure including a lower sacrifice layer contacting the etch stop layer, a support layer, and an upper sacrifice layer; forming a hole penetrating the preliminary stacked structure and the etch stop layer; forming a conductive pattern in the hole; removing the upper sacrifice layer and a portion of the support layer; removing the lower sacrifice layer; forming a first conductive layer covering the conductive pattern; and forming a dielectric layer covering the first conductive layer, a remaining portion of the support layer, and the etch stop layer.

Abstract: According to some embodiments, an integrated circuit device is disclosed. The integrated circuit device include at least one inductor having at least one turn, a magnetic coupling ring positioned adjacent to the at least one inductor, the magnetic coupling ring comprising at least two magnetic coupling turns, the at least two magnetic coupling turns are disposed adjacent to the at least one turn to enable magnetic coupling between the at least two magnetic coupling turns and the at least one turn The integrated circuit device also includes a power electrode and a ground electrode, wherein the power electrode and the ground electrode are coupled to the at least one inductor and the magnetic coupling ring to provide a first current in the at least one inductor having a direction opposite to a second current in the magnetic coupling ring to cancel at least a portion of a magnetic field generated by the at least one inductor.

Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric film extending on the lower electrode along a side surface of the lower electrode that is perpendicular to the substrate, an upper electrode on the capacitor dielectric film, an interface layer including a hydrogen blocking film and a hydrogen bypass film on the upper electrode, the hydrogen blocking film including a conductive material, and a contact plug penetrating the interface layer and electrically connected to the upper electrode.

Abstract: Certain aspects of the present disclosure provide a capacitor assembly, a stacked capacitor assembly, an integrated circuit (IC) assembly comprising such a stacked capacitor assembly, and methods for fabricating the same. One exemplary capacitor assembly generally includes a first array of trench capacitors and a second array of trench capacitors. The second array of trench capacitors may be disposed adjacent to and electrically coupled to the first array of trench capacitors. Additionally, the second array of trench capacitors may be inverted with respect to the first array of trench capacitors.

Abstract: A cost-effective solar energy collection system, including: 1) new solar PV panel wiring and power conversion system designed to allow tracking panel-to-panel shading while maintaining maximized power output, 2) the companion new combined structural and electrical inter-panel connector system supporting the new wiring scheme, and 3) the new panel structural support for the new inter-panel connector system, 4) the robotic array assembly and installation system used to assemble the new inter-panel connector and new panel structural support system into solar array sections in the field with a robotic crawler to move the assembled solar array sections to their final positions, and 5) the post system and installer for supporting the solar array sections. It is a fully integrated solar energy system for rapid installation and higher energy output which together creates a transformative change for the solar energy field.

Abstract: Capacitor forming methods may include sequentially forming a first mold layer, a first support material layer, and a second mold layer on a substrate, forming a mask pattern on the second mold layer, forming a recess in the second mold layer, the first support material layer, and the first mold layer using the mask pattern as a mask, forming a lower electrode in the recess, removing the mask pattern by a dry cleaning process, reducing a width of an upper portion of the lower electrode, removing the first mold layer, forming a dielectric layer on a surface of the lower electrode, and forming an upper electrode on the dielectric layer.

Abstract: A method for fabricating a semiconductor device includes: forming a mold structure including a mold layer and a supporter layer over a semiconductor substrate; forming an opening penetrating the mold structure; forming a protective layer on a bottom surface and a sidewall of the opening; forming a lower electrode over the protective layer; selectively etching the supporter layer to form a supporter that supports the lower electrode; removing the mold layer to define a non-exposed portion and an exposed portion of an outer wall of the protective layer; and selectively trimming the exposed portion of the protective layer to form a protective layer pattern between the supporter and the lower electrode.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a 3D metal insulator metal (MIM) capacitor structure with an increased capacitance per unit area in a semiconductor structure. The MIM structure includes a substrate, an oxide layer formed over the substrate, and a first metal layer formed over the oxide layer. The first metal layer includes a plurality of mandrels formed on a surface of the first metal layer. The MIM structure also includes a dielectric layer formed over the first metal layer and the plurality of mandrels, a second metal layer formed over on the dielectric layer, and one or more interconnect structures electrically connected to the first and second metal layers.

Abstract: An integrated circuit structure comprises a first dielectric layer disposed above a substrate. The integrated circuit structure comprises an interconnect structure comprising a first interconnect on a first metal layer, a second interconnect on a second metal layer, and a via connecting the first interconnect and the second interconnect, the first interconnect being on or within the first dielectric layer. A metal-insulator-metal (MIM) capacitor is formed in or on the first dielectric layer in the first metal layer adjacent to the interconnect structure. The MIM capacitor comprises a bottom electrode plate comprising a first low resistivity material, an insulator stack on the bottom electrode plate, the insulator stack comprising at least one of an etch stop layer and a high-K dielectric layer; and a top electrode plate on the insulator stack, the top electrode plate comprising a second low resistivity material.

Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.

Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.

Abstract: A semiconductor memory device includes a capacitor having a bottom electrode and a top electrode, a dielectric layer between the bottom and top electrodes, and an interface layer between the top electrode and the dielectric layer, the interface layer including a metal oxide and an additional constituent at a grain boundary of the interface layer.

Abstract: A package structure has a chip, a molding compound encapsulating the chip and an inductor structure disposed above the chip. A vertical projection of the inductor structure at least partially overlaps with a vertical projection of the chip.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first conductive structure disposed over the device, and the first conductive structure includes a first sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer disposed on the first portion, a second conductive structure disposed adjacent the first conductive structure, and the second conductive structure includes a second sidewall having a third portion and a fourth portion. The semiconductor device structure further includes a second spacer layer disposed on the third portion, and an air gap is formed between the first conductive structure and the second conductive structure. The second portion, the first spacer layer, the fourth portion, and the second spacer layer are exposed to the air gap.

Abstract: A method for fabricating a semiconductor device includes: forming a lower array including a plurality of bottom electrodes over a semiconductor substrate, a supporter supporting the bottom electrodes, and a dielectric layer that is formed over the bottom electrodes and the supporter; forming a gap-fill layer covering side portions of the lower array and an upper portion of the lower array; forming a capping portion covering the upper portion of the lower array over the gap-fill layer; performing a pull-back process of the gap-fill layer to form a gap-fill electrode aligned with the capping portion; and forming a low-resistivity electrode over the gap-fill electrode.

Abstract: The present disclosure provides a semiconductor memory device with air gaps between conductive features for reducing capacitive coupling and a method for preparing the semiconductor memory device. The semiconductor memory device includes an isolation layer defining a first active region in a substrate; a first doped region positioned in the first active region; a first word line buried in a first trench adjacent to the first doped region; a high-level bit line contact positioned on the first doped region; a first air gap surrounding the high-level bit line contact; wherein the first word line comprises a lower electrode structure and an upper electrode structure on the lower electrode structure; wherein the upper electrode structure comprises: a source layer substantially covering a sidewall of the first trench; a conductive layer on the source layer; and a work-function adjustment layer disposed between the source layer and the conductive layer.

Abstract: The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

Abstract: Methods and systems for laser etching substrates to fine tune antennas for wireless communication are provided. A method includes laser etching an antenna element design into a substrate material. The antenna element design is for receiving conductive material to form an antenna structure. The method also includes laser etching a first area of the substrate material to change an intrinsic property of the substrate material in order to control an electrical characteristic of the antenna structure.

Abstract: A semiconductor device includes a first vertical transistor, a second vertical transistor adjacent to the first vertical transistor, and an air gap inserted between the first vertical transistor and the second vertical transistor. The first vertical transistor includes a first channel region, a first word line wrapping the first channel region, and a first word line dielectric layer between the first channel region and the first word line. The second vertical transistor includes a second channel region, a second word line wrapping the second channel region, and a second word line dielectric layer between the second channel region and the second word line. The first word line and the second word line respectively have a top width and a bottom width, and the top width is greater than the bottom width.

Abstract: The disclosure provides a method for passivating a silicon carbide epitaxial layer, relating to the technical field of semiconductors. The method includes the following steps: introducing a carbon source and a silicon source into a reaction chamber, and growing a silicon carbide epitaxial layer on a substrate; and turning off the carbon source, introducing a nitrogen source and a silicon source into the reaction chamber, and growing a silicon nitride thin film on an upper surface of the silicon carbide epitaxial layer. The silicon nitride thin film grown by the method has few defects and high quality, and may be used as a lower dielectric layer of a gate electrode in a field effect transistor. It does not additionally need an oxidation process to form a SiO2 dielectric layer, thereby reducing device fabrication procedures.

Abstract: A method of forming a semiconductor structure includes following steps. A substrate is formed. The substrate has an active region, an isolation structure adjacent to the active region, and a contact on the active region. A dielectric stack is formed on the substrate. The dielectric stack is etched to form an opening such that the contact of the substrate is exposed. The opening has a bottom portion and a top portion communicated to the bottom portion. The dielectric stack is etched again to expand the bottom portion of the opening.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes: a substrate: a drain region vertically disposed on the substrate; a body region vertically disposed on the drain region; a source region vertically disposed on the body region; a bit-line connected to the drain region and extending in a first direction; and a word-line connected to the source region and extending in a second direction that is different from the first direction. The drain region, the body region, and the source region together define a pillar extending in a third direction that is perpendicular to the first and second direction.

Abstract: A Monolithic Microwave Integrated Circuit (MMIC) structure having a thermally conductive substrate; a semiconductor layer disposed on a first portion of an upper surface of the substrate; an active mesa-shaped semiconductor device layer disposed on the semiconductor layer; and a passive electrical device disposed directly on a second portion of the upper surface of the substrate.

Abstract: A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad and connected to the landing pad, the lower electrode including an outer portion, the outer portion including first and second regions, and an inner portion inside the outer portion, a dielectric film on the lower electrode to extend along the first region of the outer portion, and an upper electrode on the dielectric film, wherein the outer portion of the lower electrode includes a metal dopant, a concentration of the metal dopant in the first region of the outer portion being different from a concentration of the metal dopant in the second region of the outer portion.

Abstract: A semiconductor device includes a substrate, a bit line structure on the substrate, a contact plug structure being adjacent to the bit line structure and extending in a vertical direction perpendicular to an upper surface of the substrate, and a capacitor electrically connected to the contact plug structure. The contact plug structure includes a lower contact plug, a metal silicide pattern, and an upper contact plug that are sequentially stacked on the substrate. The metal silicide pattern has an L-shaped cross section.

Abstract: A method of fabricating a semiconductor device includes providing a high-k dielectric layer arranged on a channel region including a first transistor area and a second transistor area. The method further includes depositing a multivalent oxide layer directly on the high-k dielectric layer of the first transistor area. The method includes depositing a first work function metal on the multivalent oxide layer of the first transistor area and directly on the high-k dielectric layer of the second transistor area.

Abstract: A polycrystalline silicon resistor is large in coefficient of fluctuation in resistance between before and after the completion of a package molding process. To enable highly accurate trimming, it is desired to implement a resistor that is hardly subjected to stress produced in a substrate during a package molding process. A resistance element is formed of a plurality of wiring layers and has a repetitive pattern of a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and an interlayer conductive layer coupling the first conductive layer and the second conductive layer together.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture. The structure includes: a capacitor including: a bottom plate of a first conductive material; an insulator material on the bottom plate; and a top plate of a second conductive material on the insulator material; and a plurality of wirings on a same level as the bottom plate and composed of the second conductive material.

Abstract: Semiconductor devices including a capacitor in which electrostatic capacity is improved by a simplified process and/or methods for fabricating the same are provided. The semiconductor device including an insulating structure defining a first trench on a substrate, a first conductive layer in the insulating structure, a first portion of an upper surface of the first conductive layer exposed by the first trench, a capacitor structure including a first electrode pattern on the first conductive layer, a dielectric pattern on the first electrode pattern, and a second electrode pattern on the dielectric pattern, the first electrode pattern extending along sidewalls and a bottom surface of the first trench and an upper surface of the insulating structure, and a first wiring pattern on the capacitor structure may be provided.

Abstract: An optical apparatus that includes: a semiconductor substrate formed from a first material, the semiconductor substrate including a first n-doped region; and a photodiode supported by the semiconductor substrate, the photodiode including an absorption region configured to absorb photons and to generate photo-carriers from the absorbed photons, the absorption region being formed from a second material different than the first material and including: a first p-doped region; and a second n-doped region coupled to the first n-doped region, wherein a second doping concentration of the second n-doped region is less than or substantially equal to a first doping concentration of the first n-doped region.

Abstract: In a capacitor of an integrated circuit, a crystallization induction film is obtained by oxidizing a surface of an electrode, and a dielectric structure is formed on the crystallization induction film, to reduce defect density generated in the dielectric film, improve leakage current, and reduce equivalent oxide thickness.

Abstract: The present invention provides a device for manufacturing a multi-layer stacked structure and a method for manufacturing a thin film capacitor. The method includes providing a carrier substrate, forming a plurality of first material layers and a plurality of second layers that are alternately stacked on top of one another to form a multi-layer stacked structure, and then forming two terminal electrode structures for respectively enclosing two opposite side portions of the multi-layer stacked structure. One of the first material layer and the second material layer has a plurality of conductive particles randomly distributed therein. The conductive particles are heated to form a spherical structure or a sphere-like structure with low melting point and high surface energy at a temperature that is smaller than the degradation temperature of polymers. Therefore, the dielectric constant of the multi-layer stacked structure and the thin film capacitor can be increased.

Abstract: A method for back end of line (BEOL) integration for one or more interconnects includes forming one or more interconnects by depositing conductive material on a diffusion barrier layer in respective ones of one or more trenches formed within an interlevel dielectric, forming one or more cap layers on respective ones of the one or more interconnects, and selectively etching the diffusion barrier relative to the one or more cap layers to remove portions of the diffusion barrier layer along the interlevel dielectric.

Abstract: The instant invention provides a capacitor package structure having a functional coating and the method for manufacturing the same. The method includes coating a silane coupling agent with a general formula of Y(CH2)nSiX3 on a capacitor element for forming the functional coating, in which X can be a same or different substituents and is selected from the group consisting of chloride, methoxy group, ethoxy group, methoxyethoxy group and acetoxy group, Y is a vinyl group, an amino group, an epoxy group, a methacryloyloxy group, a thiol group, a uramino group or an isobutyl group; and coating a conductive dispersion on the functional coating for enabling a polymer composite material in the functional coating to be connected to the surface of the capacitor element through the silane coupling agent.

Abstract: A semiconductor may include a substrate including a cell array region and a TSV region, an insulation layer disposed on the substrate and having a recess region on the TSV region, a capacitor on the insulation layer of the cell array region, a dummy support pattern disposed on the insulation layer of the TSV region and overlapping the recess region, when viewed in plan, and a TSV electrode penetrating the dummy support pattern and the substrate.

Abstract: In a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, a stacked structure including interlayer insulating layers and interlayer sacrificial layers that are alternately stacked is formed on a substrate. A trench is formed passing through the stacked structure on the substrate. A crystalline liner insulating layer is formed on a sidewall of the trench. A ferroelectric insulating layer and a channel layer are formed on the crystalline liner insulating layer. The interlayer sacrificial layers and the crystalline liner insulating layer are selectively removed to form a recess selectively exposing the ferroelectric insulating layer. The recess is filled with a conductive layer to form an electrode layer.

Abstract: A method of forming insulating structures in a semiconductor device is provided in the present invention, which includes the steps of forming a first mask layer with mandrels and a peripheral portion surrounding the mandrels, forming spacers on sidewalls of first mask layer, filling up the space between spacers with a second mask layer, removing the spacers to form opening patterns, performing an etch process with the first mask layer and the second mask layer as an etch mask to form trenches in the substrate, and filling up the trenches with an insulating material to form insulating structures.

Abstract: Apparatus for communication across a capacitively coupled channel are disclosed herein. An example circuit includes a first plate substantially parallel to a substrate, thereby forming a first capacitance intermediate the first plate and the substrate. A second plate is substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate. A third plate is substantially parallel to the substrate, thereby forming a second capacitance intermediate the third plate and the substrate. A fourth plate is substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate. An inductor is connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.

Abstract: An interposer includes a first redistribution layer, an organic substrate, a capacitor, a hard mask layer, a conductive pillar, and a second redistribution layer. The organic substrate is on the first redistribution layer. The capacitor is embedded in the organic substrate and includes a first electrode layer, a second electrode layer, and a capacitor dielectric layer between the first electrode layer and the second electrode layer. The first electrode layer electrically connects with the first redistribution layer. The hard mask layer is on the organic substrate. The conductive pillar is embedded in the organic substrate and the hard mask layer and electrically connects with the first redistribution layer. The second redistribution layer is on the hard mask layer and electrically connects with the second electrode layer and the conductive pillar.

Abstract: Provided is an inductor structure. In embodiments of the invention, the inductor structure includes a first laminated stack. The first laminated stack includes layers of an insulating material alternating with layers of a first magnetic material. The inductor structure includes a laminated second stack formed on the first laminated stack. The second laminated stack includes layers of the insulating material alternating with layers of a second magnetic material. The second magnetic material has a greater permeability than does the first magnetic material.

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate comprising a diffusion region, a transistor structure on the substrate, and a resistive random access memory (RRAM) on the substrate, wherein the resistive random access memory includes at least one metal silicide layer in direct contact with the diffusion region, and a lower electrode, a resistive switching layer and an upper electrode are sequentially disposed on the metal silicide layer.

Abstract: Micro-electromechanical (MEMS) devices and methods of forming are provided. The MEMS device includes a first substrate including a first conductive feature, a first movable element positioned over the first conductive feature, a second conductive feature, and a second movable element positioned over the second conductive feature. The MEMS device also includes a cap bonded to the first substrate, where the cap and the first substrate define a first sealed cavity and a second sealed cavity. The first conductive feature and the first movable element are disposed in the first sealed cavity and the second conductive feature and the second movable element are disposed in the second sealed cavity. A pressure of the second cavity is higher than a pressure of the first sealed cavity, and an out gas layer is disposed in a recess of the cap that partially defines the second sealed cavity.