Making Passive Device (e.g., Resistor, Capacitor, Etc.) Patents (Class 438/381)
  • Patent number: 11309212
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first conductive structure disposed over the device, and the first conductive structure includes a first sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer disposed on the first portion, a second conductive structure disposed adjacent the first conductive structure, and the second conductive structure includes a second sidewall having a third portion and a fourth portion. The semiconductor device structure further includes a second spacer layer disposed on the third portion, and an air gap is formed between the first conductive structure and the second conductive structure. The second portion, the first spacer layer, the fourth portion, and the second spacer layer are exposed to the air gap.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: April 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11271073
    Abstract: A method for fabricating a semiconductor device includes: forming a lower array including a plurality of bottom electrodes over a semiconductor substrate, a supporter supporting the bottom electrodes, and a dielectric layer that is formed over the bottom electrodes and the supporter; forming a gap-fill layer covering side portions of the lower array and an upper portion of the lower array; forming a capping portion covering the upper portion of the lower array over the gap-fill layer; performing a pull-back process of the gap-fill layer to form a gap-fill electrode aligned with the capping portion; and forming a low-resistivity electrode over the gap-fill electrode.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: March 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Seung Muk Kim
  • Patent number: 11264390
    Abstract: The present disclosure provides a semiconductor memory device with air gaps between conductive features for reducing capacitive coupling and a method for preparing the semiconductor memory device. The semiconductor memory device includes an isolation layer defining a first active region in a substrate; a first doped region positioned in the first active region; a first word line buried in a first trench adjacent to the first doped region; a high-level bit line contact positioned on the first doped region; a first air gap surrounding the high-level bit line contact; wherein the first word line comprises a lower electrode structure and an upper electrode structure on the lower electrode structure; wherein the upper electrode structure comprises: a source layer substantially covering a sidewall of the first trench; a conductive layer on the source layer; and a work-function adjustment layer disposed between the source layer and the conductive layer.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: March 1, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Cheng Liao
  • Patent number: 11264333
    Abstract: The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: March 1, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Han-Wen Chen, Steven Verhaverbeke, Guan Huei See, Giback Park, Giorgio Cellere, Diego Tonini, Vincent Dicaprio, Kyuil Cho
  • Patent number: 11235424
    Abstract: Methods and systems for laser etching substrates to fine tune antennas for wireless communication are provided. A method includes laser etching an antenna element design into a substrate material. The antenna element design is for receiving conductive material to form an antenna structure. The method also includes laser etching a first area of the substrate material to change an intrinsic property of the substrate material in order to control an electrical characteristic of the antenna structure.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: February 1, 2022
    Assignee: Motorola Mobility LLC
    Inventors: Istvan J. Szini, Aiman Shibli
  • Patent number: 11217589
    Abstract: A semiconductor device includes a first vertical transistor, a second vertical transistor adjacent to the first vertical transistor, and an air gap inserted between the first vertical transistor and the second vertical transistor. The first vertical transistor includes a first channel region, a first word line wrapping the first channel region, and a first word line dielectric layer between the first channel region and the first word line. The second vertical transistor includes a second channel region, a second word line wrapping the second channel region, and a second word line dielectric layer between the second channel region and the second word line. The first word line and the second word line respectively have a top width and a bottom width, and the top width is greater than the bottom width.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: January 4, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jhen-Yu Tsai
  • Patent number: 11183385
    Abstract: The disclosure provides a method for passivating a silicon carbide epitaxial layer, relating to the technical field of semiconductors. The method includes the following steps: introducing a carbon source and a silicon source into a reaction chamber, and growing a silicon carbide epitaxial layer on a substrate; and turning off the carbon source, introducing a nitrogen source and a silicon source into the reaction chamber, and growing a silicon nitride thin film on an upper surface of the silicon carbide epitaxial layer. The silicon nitride thin film grown by the method has few defects and high quality, and may be used as a lower dielectric layer of a gate electrode in a field effect transistor. It does not additionally need an oxidation process to form a SiO2 dielectric layer, thereby reducing device fabrication procedures.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: November 23, 2021
    Assignee: THE 13TH RESEARCH INSTITUTE OF CHINA ELECTRONICS
    Inventors: Jia Li, Weili Lu, Yulong Fang, Jiayun Yin, Bo Wang, Yanmin Guo, Zhirong Zhang, Zhihong Feng
  • Patent number: 11145659
    Abstract: A method of forming a semiconductor structure includes following steps. A substrate is formed. The substrate has an active region, an isolation structure adjacent to the active region, and a contact on the active region. A dielectric stack is formed on the substrate. The dielectric stack is etched to form an opening such that the contact of the substrate is exposed. The opening has a bottom portion and a top portion communicated to the bottom portion. The dielectric stack is etched again to expand the bottom portion of the opening.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: October 12, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Yen-Ching Wu, Rou-Wei Wang, Shuo Jia
  • Patent number: 11133312
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes: a substrate: a drain region vertically disposed on the substrate; a body region vertically disposed on the drain region; a source region vertically disposed on the body region; a bit-line connected to the drain region and extending in a first direction; and a word-line connected to the source region and extending in a second direction that is different from the first direction. The drain region, the body region, and the source region together define a pillar extending in a third direction that is perpendicular to the first and second direction.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: September 28, 2021
    Assignees: SK hynix Inc.
    Inventor: Hagyoul Bae
  • Patent number: 11127652
    Abstract: A Monolithic Microwave Integrated Circuit (MMIC) structure having a thermally conductive substrate; a semiconductor layer disposed on a first portion of an upper surface of the substrate; an active mesa-shaped semiconductor device layer disposed on the semiconductor layer; and a passive electrical device disposed directly on a second portion of the upper surface of the substrate.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: September 21, 2021
    Assignee: Raytheon Company
    Inventors: Matthew C. Tyhach, Jarrod Vaillancourt
  • Patent number: 11069768
    Abstract: A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad and connected to the landing pad, the lower electrode including an outer portion, the outer portion including first and second regions, and an inner portion inside the outer portion, a dielectric film on the lower electrode to extend along the first region of the outer portion, and an upper electrode on the dielectric film, wherein the outer portion of the lower electrode includes a metal dopant, a concentration of the metal dopant in the first region of the outer portion being different from a concentration of the metal dopant in the second region of the outer portion.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: July 20, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Lim Park, Se Hyoung Ahn, Sang Yeol Kang, Chang Mu An, Kyoo Ho Jung
  • Patent number: 11037930
    Abstract: A semiconductor device includes a substrate, a bit line structure on the substrate, a contact plug structure being adjacent to the bit line structure and extending in a vertical direction perpendicular to an upper surface of the substrate, and a capacitor electrically connected to the contact plug structure. The contact plug structure includes a lower contact plug, a metal silicide pattern, and an upper contact plug that are sequentially stacked on the substrate. The metal silicide pattern has an L-shaped cross section.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: June 15, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD
    Inventors: Taejin Park, Keunnam Kim, Huijung Kim, Sohyun Park, Jaehwan Cho, Yoosang Hwang
  • Patent number: 11018062
    Abstract: A method of fabricating a semiconductor device includes providing a high-k dielectric layer arranged on a channel region including a first transistor area and a second transistor area. The method further includes depositing a multivalent oxide layer directly on the high-k dielectric layer of the first transistor area. The method includes depositing a first work function metal on the multivalent oxide layer of the first transistor area and directly on the high-k dielectric layer of the second transistor area.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: May 25, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Choonghyun Lee, Jingyun Zhang, Pouya Hashemi
  • Patent number: 10958250
    Abstract: A polycrystalline silicon resistor is large in coefficient of fluctuation in resistance between before and after the completion of a package molding process. To enable highly accurate trimming, it is desired to implement a resistor that is hardly subjected to stress produced in a substrate during a package molding process. A resistance element is formed of a plurality of wiring layers and has a repetitive pattern of a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and an interlayer conductive layer coupling the first conductive layer and the second conductive layer together.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: March 23, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Chiemi Hashimoto, Kosuke Yayama, Katsumi Tsuneno, Tomokazu Matsuzaki
  • Patent number: 10910304
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture. The structure includes: a capacitor including: a bottom plate of a first conductive material; an insulator material on the bottom plate; and a top plate of a second conductive material on the insulator material; and a plurality of wirings on a same level as the bottom plate and composed of the second conductive material.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: February 2, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Anthony K. Stamper, Daisy A. Vaughn, Stephen R. Bosley, Zhong-Xiang He
  • Patent number: 10892318
    Abstract: Semiconductor devices including a capacitor in which electrostatic capacity is improved by a simplified process and/or methods for fabricating the same are provided. The semiconductor device including an insulating structure defining a first trench on a substrate, a first conductive layer in the insulating structure, a first portion of an upper surface of the first conductive layer exposed by the first trench, a capacitor structure including a first electrode pattern on the first conductive layer, a dielectric pattern on the first electrode pattern, and a second electrode pattern on the dielectric pattern, the first electrode pattern extending along sidewalls and a bottom surface of the first trench and an upper surface of the insulating structure, and a first wiring pattern on the capacitor structure may be provided.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: January 12, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shaofeng Ding, Jeong Hoon Ahn
  • Patent number: 10861888
    Abstract: An optical apparatus that includes: a semiconductor substrate formed from a first material, the semiconductor substrate including a first n-doped region; and a photodiode supported by the semiconductor substrate, the photodiode including an absorption region configured to absorb photons and to generate photo-carriers from the absorbed photons, the absorption region being formed from a second material different than the first material and including: a first p-doped region; and a second n-doped region coupled to the first n-doped region, wherein a second doping concentration of the second n-doped region is less than or substantially equal to a first doping concentration of the first n-doped region.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: December 8, 2020
    Assignee: Artilux, Inc.
    Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen, Che-Fu Liang, Yuan-Fu Lyu, Chien-Lung Chen, Chung-Chih Lin, Kuan-Chen Chu
  • Patent number: 10847603
    Abstract: In a capacitor of an integrated circuit, a crystallization induction film is obtained by oxidizing a surface of an electrode, and a dielectric structure is formed on the crystallization induction film, to reduce defect density generated in the dielectric film, improve leakage current, and reduce equivalent oxide thickness.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun-min Moon, Su-hwan Kim, Hyun-jun Kim, Seong-yul Park, Young-lim Park, Jae-wan Chang
  • Patent number: 10755862
    Abstract: The present invention provides a device for manufacturing a multi-layer stacked structure and a method for manufacturing a thin film capacitor. The method includes providing a carrier substrate, forming a plurality of first material layers and a plurality of second layers that are alternately stacked on top of one another to form a multi-layer stacked structure, and then forming two terminal electrode structures for respectively enclosing two opposite side portions of the multi-layer stacked structure. One of the first material layer and the second material layer has a plurality of conductive particles randomly distributed therein. The conductive particles are heated to form a spherical structure or a sphere-like structure with low melting point and high surface energy at a temperature that is smaller than the degradation temperature of polymers. Therefore, the dielectric constant of the multi-layer stacked structure and the thin film capacitor can be increased.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: August 25, 2020
    Assignee: APAQ TECHNOLOGY CO., LTD.
    Inventor: Ming-Goo Chien
  • Patent number: 10699945
    Abstract: A method for back end of line (BEOL) integration for one or more interconnects includes forming one or more interconnects by depositing conductive material on a diffusion barrier layer in respective ones of one or more trenches formed within an interlevel dielectric, forming one or more cap layers on respective ones of the one or more interconnects, and selectively etching the diffusion barrier relative to the one or more cap layers to remove portions of the diffusion barrier layer along the interlevel dielectric.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: June 30, 2020
    Assignee: International Business Machines Corporation
    Inventors: Cornelius B. Peethala, Raghuveer R. Patlolla, Chih-Chao Yang, Roger A. Quon
  • Patent number: 10658122
    Abstract: The instant invention provides a capacitor package structure having a functional coating and the method for manufacturing the same. The method includes coating a silane coupling agent with a general formula of Y(CH2)nSiX3 on a capacitor element for forming the functional coating, in which X can be a same or different substituents and is selected from the group consisting of chloride, methoxy group, ethoxy group, methoxyethoxy group and acetoxy group, Y is a vinyl group, an amino group, an epoxy group, a methacryloyloxy group, a thiol group, a uramino group or an isobutyl group; and coating a conductive dispersion on the functional coating for enabling a polymer composite material in the functional coating to be connected to the surface of the capacitor element through the silane coupling agent.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: May 19, 2020
    Assignee: APAQ TECHNOLOGY CO., LTD.
    Inventor: Yi-Ying Wang
  • Patent number: 10535533
    Abstract: A semiconductor may include a substrate including a cell array region and a TSV region, an insulation layer disposed on the substrate and having a recess region on the TSV region, a capacitor on the insulation layer of the cell array region, a dummy support pattern disposed on the insulation layer of the TSV region and overlapping the recess region, when viewed in plan, and a TSV electrode penetrating the dummy support pattern and the substrate.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: January 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yanghee Lee, Jonghyuk Park, Choongseob Shin, Hyojin Oh, Boun Yoon, Ilyoung Yoon
  • Patent number: 10490571
    Abstract: In a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, a stacked structure including interlayer insulating layers and interlayer sacrificial layers that are alternately stacked is formed on a substrate. A trench is formed passing through the stacked structure on the substrate. A crystalline liner insulating layer is formed on a sidewall of the trench. A ferroelectric insulating layer and a channel layer are formed on the crystalline liner insulating layer. The interlayer sacrificial layers and the crystalline liner insulating layer are selectively removed to form a recess selectively exposing the ferroelectric insulating layer. The recess is filled with a conductive layer to form an electrode layer.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: November 26, 2019
    Assignee: SK hynix Inc.
    Inventors: Hyangkeun Yoo, Joong Sik Kim
  • Patent number: 10475795
    Abstract: A method of forming insulating structures in a semiconductor device is provided in the present invention, which includes the steps of forming a first mask layer with mandrels and a peripheral portion surrounding the mandrels, forming spacers on sidewalls of first mask layer, filling up the space between spacers with a second mask layer, removing the spacers to form opening patterns, performing an etch process with the first mask layer and the second mask layer as an etch mask to form trenches in the substrate, and filling up the trenches with an insulating material to form insulating structures.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: November 12, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Li-Wei Feng
  • Patent number: 10447202
    Abstract: Apparatus for communication across a capacitively coupled channel are disclosed herein. An example circuit includes a first plate substantially parallel to a substrate, thereby forming a first capacitance intermediate the first plate and the substrate. A second plate is substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate. A third plate is substantially parallel to the substrate, thereby forming a second capacitance intermediate the third plate and the substrate. A fourth plate is substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate. An inductor is connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: October 15, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Subhashish Mukherjee, Kumar Anurag Shrivastava, Sreeram Subramanyam Nasum
  • Patent number: 10381302
    Abstract: An interposer includes a first redistribution layer, an organic substrate, a capacitor, a hard mask layer, a conductive pillar, and a second redistribution layer. The organic substrate is on the first redistribution layer. The capacitor is embedded in the organic substrate and includes a first electrode layer, a second electrode layer, and a capacitor dielectric layer between the first electrode layer and the second electrode layer. The first electrode layer electrically connects with the first redistribution layer. The hard mask layer is on the organic substrate. The conductive pillar is embedded in the organic substrate and the hard mask layer and electrically connects with the first redistribution layer. The second redistribution layer is on the hard mask layer and electrically connects with the second electrode layer and the conductive pillar.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Shih-Fan Kuan, Tieh-Chiang Wu
  • Patent number: 10355070
    Abstract: Provided is an inductor structure. In embodiments of the invention, the inductor structure includes a first laminated stack. The first laminated stack includes layers of an insulating material alternating with layers of a first magnetic material. The inductor structure includes a laminated second stack formed on the first laminated stack. The second laminated stack includes layers of the insulating material alternating with layers of a second magnetic material. The second magnetic material has a greater permeability than does the first magnetic material.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • Patent number: 10283564
    Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate comprising a diffusion region, a transistor structure on the substrate, and a resistive random access memory (RRAM) on the substrate, wherein the resistive random access memory includes at least one metal silicide layer in direct contact with the diffusion region, and a lower electrode, a resistive switching layer and an upper electrode are sequentially disposed on the metal silicide layer.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: May 7, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chien Liu, Chao-Ching Hsieh, Yu-Ru Yang, Hsiao-Pang Chou
  • Patent number: 10266400
    Abstract: Micro-electromechanical (MEMS) devices and methods of forming are provided. The MEMS device includes a first substrate including a first conductive feature, a first movable element positioned over the first conductive feature, a second conductive feature, and a second movable element positioned over the second conductive feature. The MEMS device also includes a cap bonded to the first substrate, where the cap and the first substrate define a first sealed cavity and a second sealed cavity. The first conductive feature and the first movable element are disposed in the first sealed cavity and the second conductive feature and the second movable element are disposed in the second sealed cavity. A pressure of the second cavity is higher than a pressure of the first sealed cavity, and an out gas layer is disposed in a recess of the cap that partially defines the second sealed cavity.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Fung Chang, Len-Yi Leu, Lien-Yao Tsai
  • Patent number: 10211183
    Abstract: A semiconductor device is made by providing a substrate, forming a first insulation layer over the substrate, forming a first conductive layer over the first insulation layer, forming a second insulation layer over the first conductive layer, and forming a second conductive layer over the second insulation layer. A portion of the second insulation layer, first conductive layer, and second conductive layer form an integrated passive device (IPD). The IPD can be an inductor, capacitor, or resistor. A plurality of conductive pillars is formed over the second conductive layer. One conductive pillar removes heat from the semiconductor device. A third insulation layer is formed over the IPD and around the plurality of conductive pillars. A shield layer is formed over the IPD, third insulation layer, and conductive pillars. The shield layer is electrically connected to the conductive pillars to shield the IPD from electromagnetic interference.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: February 19, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Kang Chen, Haijing Cao
  • Patent number: 10109706
    Abstract: The present disclosure describes a method or forming vertical natural capacitor (VNCAP) and the resulting device. The method includes applying a patterned mask over an insulation layer. The method includes forming using the patterned mask, a dielectric trench in the insulation layer. The method includes depositing a high dielectric constant k (high k) layer in the dielectric trench. The method includes forming a first trench and a second trench in the high k dielectric layer. The high k dielectric layer is disposed between the first trench and the second trench. The method includes depositing metal in the first trench and the second trench.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Devender, Sunil K. Singh, M. Golam Faruk, Dewei Xu
  • Patent number: 9917081
    Abstract: A semiconductor device includes a semiconductor substrate having a fin-type field effect transistor (finFET) on a first region and a fin varactor on a second region. The finFET includes a first semiconductor fin that extends from an upper finFET surface thereof to the upper surface of the first region to define a first total fin height. The fin varactor includes a second semiconductor fin that extends from an upper varactor surface thereof to the upper surface of the second region to define a second total fin height that is different from the first total fin height of the finFET.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: March 13, 2018
    Assignees: GLOBALFOUNDRIES, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Junli Wang, Ruilong Xie, Tenko Yamashita
  • Patent number: 9911657
    Abstract: A semiconductor device includes a semiconductor substrate having a fin-type field effect transistor (finFET) on a first region and a fin varactor on a second region. The finFET includes a first semiconductor fin that extends from an upper finFET surface thereof to the upper surface of the first region to define a first total fin height. The fin varactor includes a second semiconductor fin that extends from an upper varactor surface thereof to the upper surface of the second region to define a second total fin height that is different from the first total fin height of the finFET.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: March 6, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Junli Wang, Ruilong Xie, Tenko Yamashita
  • Patent number: 9887155
    Abstract: A semiconductor device including a conductive element and an interface surface fabricated atop the conductive element, and a method for fabricating such a device are described. An exemplary device includes a substrate having a conductive element and a metal layer fabricated atop the conductive element. An oxide layer is fabricated atop the metal layer, thus forming an interface surface. During polishing (e.g., planarization), in which an upper portion of the interface surface is removed, the presence of the interface surface greatly reduces the loading on the conductive element. A second substrate fabricated using the same process may be stacked atop the first substrate and bonded using a hybrid bonding process.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: February 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Yin Liu, Kai-Wen Cheng, Xin-Hua Huang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 9881787
    Abstract: Methods for depositing titanium oxide films by atomic layer deposition are disclosed. Titanium oxide films may include a titanium nitride cap, an oxygen rich titanium nitride cap or a mixed oxide nitride layer. Also described are methods for self-aligned double patterning including titanium oxide spacer films.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: January 30, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chien-Teh Kao, Benjamin Schmiege, Xuesong Lu, Juno Yu-Ting Huang, Yu Lei, Yung-Hsin Lee, Srinivas Gandikota, Rajkumar Jakkaraju, Chikuang Charles Wang, Ghazal Saheli, Benjamin C. Wang, Xinliang Lu, Pingyan Lei
  • Patent number: 9847378
    Abstract: A resistive memory device includes a conductor and a resistive memory stack in contact with the conductor. The resistive memory stack includes a multi-component electrode and a switching region. The multi-component electrode includes a base electrode having a surface, and an inert material electrode on the base electrode surface in a form of i) a thin layer, or ii) discontinuous nano-islands. A switching region is in contact with the conductor and with the inert material electrode when the inert material electrode is in the form of the thin layer; or the switching region is in contact with the conductor, with the inert material electrode, and with an oxidized portion of the base electrode when the inert material electrode is in the form of the discontinuous nano-islands.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: December 19, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Xia Sheng, Yoocharn Jeon, Jianhua Yang, Hans S. Cho, Richard H. Henze
  • Patent number: 9834847
    Abstract: A cluster of non-collapsed nanowires, a template to produce the same, methods to obtain the template and to obtain the cluster by using the template, and devices having the cluster. The cluster and the template both have an interconnected region and an interconnection-free region.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: December 5, 2017
    Assignees: IMEC VZW, King Abdulaziz City of Science and Technology
    Inventors: Cedric Huyghebaert, Alaa Abd-Elnaiem, Philippe Vereecken
  • Patent number: 9764948
    Abstract: Micro-electromechanical (MEMS) devices and methods of forming are provided. An outgas layer is deposited on a surface of a cap wafer. The cap wafer is bonded to a substrate in a manner that forms a first sealed cavity including a first movable element and a second sealed cavity including a second movable element. The out gas layer is annealed to release gas from the out gas layer into the second sealed cavity and increase a pressure of the second sealed cavity so that the second sealed cavity has a higher pressure than the first sealed cavity after the annealing.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Fung Chang, Len-Yi Leu, Lien-Yao Tsai
  • Patent number: 9754934
    Abstract: A variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer overlying a substrate, a second main capacitor electrode spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode. The movable capacitor electrode can be caused to be in a first position ohmically electrically connected to the fixed main capacitor electrode such that the variable capacitor has a first capacitance value or in a second position spaced from the fixed main capacitor electrode such that the variable capacitor has a second capacitance value.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: September 5, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 9691684
    Abstract: An integrated circuit device is provided which includes a through-silicon via (TSV) structure and one or more decoupling capacitors, along with a method of manufacturing the same. The integrated circuit device may include a semiconductor structure including a semiconductor substrate, a TSV structure passing through the semiconductor substrate, and a decoupling capacitor formed in the semiconductor substrate and connected to the TSV structure. The TSV structure and the one or more decoupling capacitors may be substantially simultaneously formed. A plurality of decoupling capacitors may be disposed within a keep out zone (KOZ) of the TSV structure. The plurality of decoupling capacitors may have the same or different widths and/or depths. An isopotential conductive layer may be formed to reduce or eliminate a potential difference between different parts of the TSV structure.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: June 27, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-hwa Park, Sung-hee Kang, Kwang-jin Moon, Byung-lyul Park, Suk-chul Bang
  • Patent number: 9640608
    Abstract: A capacitor includes a bottom electrode and a top electrode positioned above the bottom electrode. The top electrode and the bottom electrode are conductively coupled to one another. A middle electrode is positioned between the bottom electrode and the top electrode. A lower dielectric layer is positioned between the bottom electrode and the middle electrode. An upper dielectric layer positioned between the middle electrode and the top electrode. A first contact is conductively coupled to the top electrode. A second contact is conductively coupled to the middle electrode.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: May 2, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ki Young Lee, Woong Lae Cho, Jae Ho Joung
  • Patent number: 9627138
    Abstract: Apparatus for integrated capacitors and associated methods are disclosed. In one embodiment, an integrated capacitor includes a first plurality of metal members that are fabricated using a first plurality of metal layers, and are oriented in a first orientation. The integrated capacitor also includes a second plurality of metal members that are fabricated using a second plurality of metal layers. The second plurality of metal members are oriented transverse to the first orientation. The integrated capacitor further includes a third plurality of metal members, which are fabricated using a third plurality of metal layers, and are oriented in the first orientation.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: April 18, 2017
    Assignee: Altera Corporation
    Inventors: Shuxian Chen, Albert Ratnakumar, Yan Cui, Jeffrey T. Watt
  • Patent number: 9576965
    Abstract: A semiconductor device includes a bit line disposed over a semiconductor substrate, a supporting film being perpendicular to the bit line, a first storage node contact disposed at a lower part of a region disposed between the bit line and the supporting film, and a second storage node contact having a line shape, disposed over the first storage node contact and the bit line, isolated by the supporting film, and patterned in a diagonal direction across the bit line.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: February 21, 2017
    Assignee: SK HYNIX INC.
    Inventors: Jae Man Yoon, Young Bog Kim, Yun Seok Chun, Woong Choi, Woo Jun Lee
  • Patent number: 9548266
    Abstract: A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: January 17, 2017
    Assignee: NXP USA, INC.
    Inventors: Sergio A. Ajuria, Phuc M. Nyugen, Douglas M. Reber
  • Patent number: 9540729
    Abstract: Processes are provided for depositing titanium nanolaminate thin films that can be used, for example, in integrated circuit fabrication, such as in forming spacers in a pitch multiplication process. In some embodiments a titanium nanolaminate film comprising titanium oxide layers and titanium nitride layers is deposited on a three-dimensional feature, such as an existing mask feature. The conformal titanium nanolaminate film may be directionally etched so that only the titanium nanolaminate deposited or formed on the sidewalls of the existing three-dimensional feature remains. The three-dimensional feature is then removed via an etching process, leaving the pitch doubled titanium nanolaminate film.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: January 10, 2017
    Assignee: ASM IP HOLDING B.V.
    Inventors: Seiji Okura, Hidemi Suemori, Viljami J. Pore
  • Patent number: 9493340
    Abstract: A MEMS device, such as an accelerometer or gyroscope, fabricated in interconnect metallization compatible with a CMOS microelectronic device. In embodiments, a proof mass has a first body region utilizing a thick metal layer that is separated from a thin metal layer. The thick metal layer has a film thickness that is significantly greater than that of the thin metal layer for increased mass. The proof mass further includes a first sensing structure comprising the thin metal layer, but lacking the thick metal layer for small feature sizes and increased capacitive coupling to a surrounding frame that includes a second sensing structure comprising the thin metal layer, but also lacking the thick metal layer. In further embodiments, the frame is released and includes regions with the thick metal layer to better match film stress-induced static deflection of the proof mass.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: November 15, 2016
    Assignee: Intel Corporation
    Inventors: Rashed Mahameed, Kristen L. Dorsey, Mamdouh O. Abdelmejeed, Mohamed A. Abdelmoneum
  • Patent number: 9373676
    Abstract: The semiconductor device has an insulation layer formed over a semiconductor substrate, a conductor plug 46 buried in the insulation layer, a capacitor formed above the insulation layer and the conductor plug and including a lower electrode formed of the first conduction film and the second conduction film formed over the first conduction film and formed of Pt, Pt alloy, Pd or Pd alloy, a capacitor dielectric film formed of a ferroelectric or a high dielectric formed over the lower electrode and an upper electrode formed over the capacitor dielectric film, the capacitor dielectric film contains a first element of Pb or Bi, and the concentration peak of the first element diffused in the lower electrode from the capacitor dielectric film positioning in the interface between the first conduction film and the second conduction film.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: June 21, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Wensheng Wang
  • Patent number: 9362168
    Abstract: According to an embodiment, a non-volatile memory device includes a first wiring provided on an underlayer, a first memory cell array provided on the first wiring and including a plurality of memory cells, a first select element including a first control electrode provided between the first wiring and the first memory cell array. The device also includes a second wiring provided at the same level as the first wiring and electrically connected to the first control electrode, and a first plug electrically connecting the first control electrode and the second wiring, one end of the first plug being in contact with the second wiring, and a side surface of the first plug being in contact with the first control electrode.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: June 7, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiharu Tanaka
  • Patent number: 9324706
    Abstract: A method is provided for forming an integrated circuit chip with a variable capacitor disposed in a metallization. A back end of line metallization is formed over the semiconductor substrate. The variable capacitor is formed within a cavity of the back end of line metallization. The variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer of the back end of line metallization, a second main capacitor electrode electrically connected to a second metal layer of the back end of line metallization and vertically spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: April 26, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 9318545
    Abstract: A metal resistor structure and a method for forming the same are provided. The method includes: providing a substrate including a first and a second metallic plugs disposed in a first and a second regions respectively; forming a first metallic layer on the substrate; forming an insulating material layer on the first metallic layer; patterning the insulating material layer to form a first and a second insulating layer above the first and the second regions respectively; forming a second metallic layer overlaying exposed part of the first metallic layer, the first insulating layer, and the second insulating layer; forming a patterned mask layer on the second metallic layer; and etching, by using the patterned mask layer as a mask, until the substrate is exposed. Accordingly, a capacitor and a metallic resistor are formed on a set of steps, thus processing steps for forming the metallic resistor can be reduced.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: April 19, 2016
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventor: Po Li