Making Passive Device (e.g., Resistor, Capacitor, Etc.) Patents (Class 438/381)
  • Patent number: 10535533
    Abstract: A semiconductor may include a substrate including a cell array region and a TSV region, an insulation layer disposed on the substrate and having a recess region on the TSV region, a capacitor on the insulation layer of the cell array region, a dummy support pattern disposed on the insulation layer of the TSV region and overlapping the recess region, when viewed in plan, and a TSV electrode penetrating the dummy support pattern and the substrate.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: January 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yanghee Lee, Jonghyuk Park, Choongseob Shin, Hyojin Oh, Boun Yoon, Ilyoung Yoon
  • Patent number: 10490571
    Abstract: In a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, a stacked structure including interlayer insulating layers and interlayer sacrificial layers that are alternately stacked is formed on a substrate. A trench is formed passing through the stacked structure on the substrate. A crystalline liner insulating layer is formed on a sidewall of the trench. A ferroelectric insulating layer and a channel layer are formed on the crystalline liner insulating layer. The interlayer sacrificial layers and the crystalline liner insulating layer are selectively removed to form a recess selectively exposing the ferroelectric insulating layer. The recess is filled with a conductive layer to form an electrode layer.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: November 26, 2019
    Assignee: SK hynix Inc.
    Inventors: Hyangkeun Yoo, Joong Sik Kim
  • Patent number: 10475795
    Abstract: A method of forming insulating structures in a semiconductor device is provided in the present invention, which includes the steps of forming a first mask layer with mandrels and a peripheral portion surrounding the mandrels, forming spacers on sidewalls of first mask layer, filling up the space between spacers with a second mask layer, removing the spacers to form opening patterns, performing an etch process with the first mask layer and the second mask layer as an etch mask to form trenches in the substrate, and filling up the trenches with an insulating material to form insulating structures.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: November 12, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Li-Wei Feng
  • Patent number: 10447202
    Abstract: Apparatus for communication across a capacitively coupled channel are disclosed herein. An example circuit includes a first plate substantially parallel to a substrate, thereby forming a first capacitance intermediate the first plate and the substrate. A second plate is substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate. A third plate is substantially parallel to the substrate, thereby forming a second capacitance intermediate the third plate and the substrate. A fourth plate is substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate. An inductor is connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: October 15, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Subhashish Mukherjee, Kumar Anurag Shrivastava, Sreeram Subramanyam Nasum
  • Patent number: 10381302
    Abstract: An interposer includes a first redistribution layer, an organic substrate, a capacitor, a hard mask layer, a conductive pillar, and a second redistribution layer. The organic substrate is on the first redistribution layer. The capacitor is embedded in the organic substrate and includes a first electrode layer, a second electrode layer, and a capacitor dielectric layer between the first electrode layer and the second electrode layer. The first electrode layer electrically connects with the first redistribution layer. The hard mask layer is on the organic substrate. The conductive pillar is embedded in the organic substrate and the hard mask layer and electrically connects with the first redistribution layer. The second redistribution layer is on the hard mask layer and electrically connects with the second electrode layer and the conductive pillar.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Shih-Fan Kuan, Tieh-Chiang Wu
  • Patent number: 10355070
    Abstract: Provided is an inductor structure. In embodiments of the invention, the inductor structure includes a first laminated stack. The first laminated stack includes layers of an insulating material alternating with layers of a first magnetic material. The inductor structure includes a laminated second stack formed on the first laminated stack. The second laminated stack includes layers of the insulating material alternating with layers of a second magnetic material. The second magnetic material has a greater permeability than does the first magnetic material.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • Patent number: 10283564
    Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate comprising a diffusion region, a transistor structure on the substrate, and a resistive random access memory (RRAM) on the substrate, wherein the resistive random access memory includes at least one metal silicide layer in direct contact with the diffusion region, and a lower electrode, a resistive switching layer and an upper electrode are sequentially disposed on the metal silicide layer.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: May 7, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chien Liu, Chao-Ching Hsieh, Yu-Ru Yang, Hsiao-Pang Chou
  • Patent number: 10266400
    Abstract: Micro-electromechanical (MEMS) devices and methods of forming are provided. The MEMS device includes a first substrate including a first conductive feature, a first movable element positioned over the first conductive feature, a second conductive feature, and a second movable element positioned over the second conductive feature. The MEMS device also includes a cap bonded to the first substrate, where the cap and the first substrate define a first sealed cavity and a second sealed cavity. The first conductive feature and the first movable element are disposed in the first sealed cavity and the second conductive feature and the second movable element are disposed in the second sealed cavity. A pressure of the second cavity is higher than a pressure of the first sealed cavity, and an out gas layer is disposed in a recess of the cap that partially defines the second sealed cavity.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Fung Chang, Len-Yi Leu, Lien-Yao Tsai
  • Patent number: 10211183
    Abstract: A semiconductor device is made by providing a substrate, forming a first insulation layer over the substrate, forming a first conductive layer over the first insulation layer, forming a second insulation layer over the first conductive layer, and forming a second conductive layer over the second insulation layer. A portion of the second insulation layer, first conductive layer, and second conductive layer form an integrated passive device (IPD). The IPD can be an inductor, capacitor, or resistor. A plurality of conductive pillars is formed over the second conductive layer. One conductive pillar removes heat from the semiconductor device. A third insulation layer is formed over the IPD and around the plurality of conductive pillars. A shield layer is formed over the IPD, third insulation layer, and conductive pillars. The shield layer is electrically connected to the conductive pillars to shield the IPD from electromagnetic interference.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: February 19, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Kang Chen, Haijing Cao
  • Patent number: 10109706
    Abstract: The present disclosure describes a method or forming vertical natural capacitor (VNCAP) and the resulting device. The method includes applying a patterned mask over an insulation layer. The method includes forming using the patterned mask, a dielectric trench in the insulation layer. The method includes depositing a high dielectric constant k (high k) layer in the dielectric trench. The method includes forming a first trench and a second trench in the high k dielectric layer. The high k dielectric layer is disposed between the first trench and the second trench. The method includes depositing metal in the first trench and the second trench.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Devender, Sunil K. Singh, M. Golam Faruk, Dewei Xu
  • Patent number: 9917081
    Abstract: A semiconductor device includes a semiconductor substrate having a fin-type field effect transistor (finFET) on a first region and a fin varactor on a second region. The finFET includes a first semiconductor fin that extends from an upper finFET surface thereof to the upper surface of the first region to define a first total fin height. The fin varactor includes a second semiconductor fin that extends from an upper varactor surface thereof to the upper surface of the second region to define a second total fin height that is different from the first total fin height of the finFET.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: March 13, 2018
    Assignees: GLOBALFOUNDRIES, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Junli Wang, Ruilong Xie, Tenko Yamashita
  • Patent number: 9911657
    Abstract: A semiconductor device includes a semiconductor substrate having a fin-type field effect transistor (finFET) on a first region and a fin varactor on a second region. The finFET includes a first semiconductor fin that extends from an upper finFET surface thereof to the upper surface of the first region to define a first total fin height. The fin varactor includes a second semiconductor fin that extends from an upper varactor surface thereof to the upper surface of the second region to define a second total fin height that is different from the first total fin height of the finFET.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: March 6, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Junli Wang, Ruilong Xie, Tenko Yamashita
  • Patent number: 9887155
    Abstract: A semiconductor device including a conductive element and an interface surface fabricated atop the conductive element, and a method for fabricating such a device are described. An exemplary device includes a substrate having a conductive element and a metal layer fabricated atop the conductive element. An oxide layer is fabricated atop the metal layer, thus forming an interface surface. During polishing (e.g., planarization), in which an upper portion of the interface surface is removed, the presence of the interface surface greatly reduces the loading on the conductive element. A second substrate fabricated using the same process may be stacked atop the first substrate and bonded using a hybrid bonding process.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: February 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Yin Liu, Kai-Wen Cheng, Xin-Hua Huang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 9881787
    Abstract: Methods for depositing titanium oxide films by atomic layer deposition are disclosed. Titanium oxide films may include a titanium nitride cap, an oxygen rich titanium nitride cap or a mixed oxide nitride layer. Also described are methods for self-aligned double patterning including titanium oxide spacer films.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: January 30, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chien-Teh Kao, Benjamin Schmiege, Xuesong Lu, Juno Yu-Ting Huang, Yu Lei, Yung-Hsin Lee, Srinivas Gandikota, Rajkumar Jakkaraju, Chikuang Charles Wang, Ghazal Saheli, Benjamin C. Wang, Xinliang Lu, Pingyan Lei
  • Patent number: 9847378
    Abstract: A resistive memory device includes a conductor and a resistive memory stack in contact with the conductor. The resistive memory stack includes a multi-component electrode and a switching region. The multi-component electrode includes a base electrode having a surface, and an inert material electrode on the base electrode surface in a form of i) a thin layer, or ii) discontinuous nano-islands. A switching region is in contact with the conductor and with the inert material electrode when the inert material electrode is in the form of the thin layer; or the switching region is in contact with the conductor, with the inert material electrode, and with an oxidized portion of the base electrode when the inert material electrode is in the form of the discontinuous nano-islands.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: December 19, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Xia Sheng, Yoocharn Jeon, Jianhua Yang, Hans S. Cho, Richard H. Henze
  • Patent number: 9834847
    Abstract: A cluster of non-collapsed nanowires, a template to produce the same, methods to obtain the template and to obtain the cluster by using the template, and devices having the cluster. The cluster and the template both have an interconnected region and an interconnection-free region.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: December 5, 2017
    Assignees: IMEC VZW, King Abdulaziz City of Science and Technology
    Inventors: Cedric Huyghebaert, Alaa Abd-Elnaiem, Philippe Vereecken
  • Patent number: 9764948
    Abstract: Micro-electromechanical (MEMS) devices and methods of forming are provided. An outgas layer is deposited on a surface of a cap wafer. The cap wafer is bonded to a substrate in a manner that forms a first sealed cavity including a first movable element and a second sealed cavity including a second movable element. The out gas layer is annealed to release gas from the out gas layer into the second sealed cavity and increase a pressure of the second sealed cavity so that the second sealed cavity has a higher pressure than the first sealed cavity after the annealing.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Fung Chang, Len-Yi Leu, Lien-Yao Tsai
  • Patent number: 9754934
    Abstract: A variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer overlying a substrate, a second main capacitor electrode spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode. The movable capacitor electrode can be caused to be in a first position ohmically electrically connected to the fixed main capacitor electrode such that the variable capacitor has a first capacitance value or in a second position spaced from the fixed main capacitor electrode such that the variable capacitor has a second capacitance value.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: September 5, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 9691684
    Abstract: An integrated circuit device is provided which includes a through-silicon via (TSV) structure and one or more decoupling capacitors, along with a method of manufacturing the same. The integrated circuit device may include a semiconductor structure including a semiconductor substrate, a TSV structure passing through the semiconductor substrate, and a decoupling capacitor formed in the semiconductor substrate and connected to the TSV structure. The TSV structure and the one or more decoupling capacitors may be substantially simultaneously formed. A plurality of decoupling capacitors may be disposed within a keep out zone (KOZ) of the TSV structure. The plurality of decoupling capacitors may have the same or different widths and/or depths. An isopotential conductive layer may be formed to reduce or eliminate a potential difference between different parts of the TSV structure.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: June 27, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-hwa Park, Sung-hee Kang, Kwang-jin Moon, Byung-lyul Park, Suk-chul Bang
  • Patent number: 9640608
    Abstract: A capacitor includes a bottom electrode and a top electrode positioned above the bottom electrode. The top electrode and the bottom electrode are conductively coupled to one another. A middle electrode is positioned between the bottom electrode and the top electrode. A lower dielectric layer is positioned between the bottom electrode and the middle electrode. An upper dielectric layer positioned between the middle electrode and the top electrode. A first contact is conductively coupled to the top electrode. A second contact is conductively coupled to the middle electrode.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: May 2, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ki Young Lee, Woong Lae Cho, Jae Ho Joung
  • Patent number: 9627138
    Abstract: Apparatus for integrated capacitors and associated methods are disclosed. In one embodiment, an integrated capacitor includes a first plurality of metal members that are fabricated using a first plurality of metal layers, and are oriented in a first orientation. The integrated capacitor also includes a second plurality of metal members that are fabricated using a second plurality of metal layers. The second plurality of metal members are oriented transverse to the first orientation. The integrated capacitor further includes a third plurality of metal members, which are fabricated using a third plurality of metal layers, and are oriented in the first orientation.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: April 18, 2017
    Assignee: Altera Corporation
    Inventors: Shuxian Chen, Albert Ratnakumar, Yan Cui, Jeffrey T. Watt
  • Patent number: 9576965
    Abstract: A semiconductor device includes a bit line disposed over a semiconductor substrate, a supporting film being perpendicular to the bit line, a first storage node contact disposed at a lower part of a region disposed between the bit line and the supporting film, and a second storage node contact having a line shape, disposed over the first storage node contact and the bit line, isolated by the supporting film, and patterned in a diagonal direction across the bit line.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: February 21, 2017
    Assignee: SK HYNIX INC.
    Inventors: Jae Man Yoon, Young Bog Kim, Yun Seok Chun, Woong Choi, Woo Jun Lee
  • Patent number: 9548266
    Abstract: A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: January 17, 2017
    Assignee: NXP USA, INC.
    Inventors: Sergio A. Ajuria, Phuc M. Nyugen, Douglas M. Reber
  • Patent number: 9540729
    Abstract: Processes are provided for depositing titanium nanolaminate thin films that can be used, for example, in integrated circuit fabrication, such as in forming spacers in a pitch multiplication process. In some embodiments a titanium nanolaminate film comprising titanium oxide layers and titanium nitride layers is deposited on a three-dimensional feature, such as an existing mask feature. The conformal titanium nanolaminate film may be directionally etched so that only the titanium nanolaminate deposited or formed on the sidewalls of the existing three-dimensional feature remains. The three-dimensional feature is then removed via an etching process, leaving the pitch doubled titanium nanolaminate film.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: January 10, 2017
    Assignee: ASM IP HOLDING B.V.
    Inventors: Seiji Okura, Hidemi Suemori, Viljami J. Pore
  • Patent number: 9493340
    Abstract: A MEMS device, such as an accelerometer or gyroscope, fabricated in interconnect metallization compatible with a CMOS microelectronic device. In embodiments, a proof mass has a first body region utilizing a thick metal layer that is separated from a thin metal layer. The thick metal layer has a film thickness that is significantly greater than that of the thin metal layer for increased mass. The proof mass further includes a first sensing structure comprising the thin metal layer, but lacking the thick metal layer for small feature sizes and increased capacitive coupling to a surrounding frame that includes a second sensing structure comprising the thin metal layer, but also lacking the thick metal layer. In further embodiments, the frame is released and includes regions with the thick metal layer to better match film stress-induced static deflection of the proof mass.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: November 15, 2016
    Assignee: Intel Corporation
    Inventors: Rashed Mahameed, Kristen L. Dorsey, Mamdouh O. Abdelmejeed, Mohamed A. Abdelmoneum
  • Patent number: 9373676
    Abstract: The semiconductor device has an insulation layer formed over a semiconductor substrate, a conductor plug 46 buried in the insulation layer, a capacitor formed above the insulation layer and the conductor plug and including a lower electrode formed of the first conduction film and the second conduction film formed over the first conduction film and formed of Pt, Pt alloy, Pd or Pd alloy, a capacitor dielectric film formed of a ferroelectric or a high dielectric formed over the lower electrode and an upper electrode formed over the capacitor dielectric film, the capacitor dielectric film contains a first element of Pb or Bi, and the concentration peak of the first element diffused in the lower electrode from the capacitor dielectric film positioning in the interface between the first conduction film and the second conduction film.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: June 21, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Wensheng Wang
  • Patent number: 9362168
    Abstract: According to an embodiment, a non-volatile memory device includes a first wiring provided on an underlayer, a first memory cell array provided on the first wiring and including a plurality of memory cells, a first select element including a first control electrode provided between the first wiring and the first memory cell array. The device also includes a second wiring provided at the same level as the first wiring and electrically connected to the first control electrode, and a first plug electrically connecting the first control electrode and the second wiring, one end of the first plug being in contact with the second wiring, and a side surface of the first plug being in contact with the first control electrode.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: June 7, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiharu Tanaka
  • Patent number: 9324706
    Abstract: A method is provided for forming an integrated circuit chip with a variable capacitor disposed in a metallization. A back end of line metallization is formed over the semiconductor substrate. The variable capacitor is formed within a cavity of the back end of line metallization. The variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer of the back end of line metallization, a second main capacitor electrode electrically connected to a second metal layer of the back end of line metallization and vertically spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: April 26, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 9318545
    Abstract: A metal resistor structure and a method for forming the same are provided. The method includes: providing a substrate including a first and a second metallic plugs disposed in a first and a second regions respectively; forming a first metallic layer on the substrate; forming an insulating material layer on the first metallic layer; patterning the insulating material layer to form a first and a second insulating layer above the first and the second regions respectively; forming a second metallic layer overlaying exposed part of the first metallic layer, the first insulating layer, and the second insulating layer; forming a patterned mask layer on the second metallic layer; and etching, by using the patterned mask layer as a mask, until the substrate is exposed. Accordingly, a capacitor and a metallic resistor are formed on a set of steps, thus processing steps for forming the metallic resistor can be reduced.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: April 19, 2016
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventor: Po Li
  • Patent number: 9287211
    Abstract: In sophisticated semiconductor devices, electronic fuses may be provided in the metallization system, wherein a superior two-dimensional configuration of the metal line, for instance as a helix-like configuration, may provide superior thermal conditions in a central line portion, which in turn may result in a more pronounced electromigration effect for a given programming current. Consequently, the size of the electronic fuse, at least in one lateral direction, and also the width of corresponding transistors connected to the electronic fuse, may be reduced.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: March 15, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Andreas Kurz, Jens Poppe, Matthias Kessler
  • Patent number: 9240442
    Abstract: A method for fabricating a capacitor of a semiconductor device includes forming a mold layer over a substrate, forming a plurality of preliminary openings by selectively etching the mold layer, forming a plurality of openings where each opening is formed to have a given linewidth by forming a sacrificial layer on sidewalls of the preliminary openings, and forming a plurality of storage nodes in the plurality of openings.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: January 19, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sung-Won Lim, Seung-Jin Yeom, Hyo-Seok Lee
  • Patent number: 9230907
    Abstract: An integrated circuit includes a substrate. A fixed main capacitor electrode is disposed in a metal layer overlying the substrate. A second main capacitor electrode is disposed in a metal layer and spaced from the fixed main capacitor electrode. A movable capacitor electrode is disposed adjacent the fixed main capacitor electrode. The movable capacitor electrode is switchable between a first configuration in which the movable capacitor electrode and fixed main capacitor electrode are mutually spaced out in such a manner as to form an auxiliary capacitor electrically connected to the main capacitor. In a second configuration, the movable capacitor electrode and the fixed main capacitor electrode are in electrical contact in such a manner as to give a second capacitive value.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: January 5, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 9184166
    Abstract: The instant disclosure relates to a semiconductor device which includes a semiconductor substrate, at least one patterned reinforcing layer, a plurality of lower electrodes, and a supporting layer. The at least one patterned reinforcing layer is arranged above the semiconductor substrate, wherein the at least one patterned reinforcing layer has a plurality of reinforcing structures configured to define a plurality of alignment apertures. The lower electrodes are arranged on the semiconductor substrate, wherein N of the lower electrodes pass through each of the alignment apertures, where N is an integer greater than or equal to 1. The supporting layer is arranged above the at least one patterned reinforcing layer and between the lower electrodes.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: November 10, 2015
    Assignee: Inotera Memories, Inc.
    Inventors: Tzung-Han Lee, Yaw-Wen Hu, Vishnu Kumar Agarwal
  • Patent number: 9159780
    Abstract: A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the support material. A first etching is conducted only partially into the support material using a liquid etching fluid to expose an elevationally outer portion of sidewalls of individual of the first capacitor electrodes. A second etching is conducted into the support material using a dry etching fluid to expose an elevationally inner portion of the sidewalls of the individual first capacitor electrodes. A capacitor dielectric is formed over the outer and inner portions of the sidewalls of the first capacitor electrodes. A second capacitor electrode is formed over the capacitor dielectric.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: October 13, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Joseph Neil Greeley, Prashant Raghu, Niraj B. Rana
  • Patent number: 9152254
    Abstract: In one embodiment, an active stylus includes one or more computer-readable non-transitory storage media embodying logic for wirelessly communicating with a device through a touch sensor of the device. The active stylus also includes an electrode for wirelessly receiving or transmitting signals through the touch sensor of the device to enable the communication, wherein the electrode is disposed at or near a tip of the active stylus. The active stylus further includes a conductive element providing at least a portion of a connection between the electrode and the media. The conductive element is made of a single piece of conductive material and includes a first end connected to a circuit board of the active stylus that the media is disposed on. The conductive element also includes a second end that includes a deformable ring configured to fit within an interior portion of the electrode.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: October 6, 2015
    Assignee: Atmel Corporation
    Inventor: Nigel Hinson
  • Patent number: 9096726
    Abstract: A composition for forming silica-based insulation layer includes a hydrogenated polysiloxazane including a moiety represented by the following Chemical Formula 1 and a moiety represented by the following Chemical Formula 2, and having a chlorine concentration of about 1 ppm or less:
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: August 4, 2015
    Assignee: CHEIL INDUSTRIES, INC.
    Inventors: Sang-Hak Lim, Bong-Hwan Kim, Jung-Kang Oh, Taek-Soo Kwak, Jin-Hee Bae, Hui-Chan Yun, Dong-Il Han, Sang-Kyun Kim, Jin-Wook Lee
  • Patent number: 9076663
    Abstract: A semiconductor die is described. This semiconductor die includes a driver, and a spatial alignment transducer that is electrically coupled to the driver and which is proximate to a surface of the semiconductor die. The driver establishes a spatially varying electric charge distribution in at least one direction in the spatial alignment transducer, thereby facilitating determination of a vertical spacing between a surface of the semiconductor die and a surface of another semiconductor die. In particular, a spatial alignment sensor proximate to the surface of the other semiconductor die may detect an electrical field (or an associated electrostatic potential) associated with the spatially varying electric charge distribution. This detected electric field may allow the vertical spacing between the surfaces of the semiconductor dies to be determined.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: July 7, 2015
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventor: Ivan E. Sutherland
  • Patent number: 9062390
    Abstract: Methods of forming a crystalline strontium titanate layer may include providing a substrate with a crystal enhancement surface (e.g., Pt), depositing strontium titanate by atomic layer deposition, and conducting a post-deposition anneal to crystallize the strontium titanate. Large single crystal domains may be formed, laterally extending greater distances than the thickness of the strontium titanate and demonstrating greater ordering than the underlying crystal enhancement surface provided to initiate ALD. Functional oxides, particularly perovskite complex oxides, can be heteroepitaxially deposited over the crystallized STO.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: June 23, 2015
    Assignee: ASM International N.V.
    Inventor: Tom E. Blomberg
  • Patent number: 9064719
    Abstract: An integrated circuit includes a capacitor and a non-inductive resistor. A substrate has a capacitor area and a resistor area. A patterned stacked structure including a bottom conductive layer, an insulating layer and a top conductive layer from bottom to top is sandwiched by a first dielectric layer and a second dielectric layer disposed on the substrate. A first metal plug and a second metal plug contact the top conductive layer and the bottom conductive layer of the capacitor area respectively, thereby the patterned stacked structure in the capacitor area constituting the capacitor. A third metal plug and a fourth metal plug contact the bottom conductive layer and the top conductive layer of the resistor area respectively, and a fifth metal plug contacts the bottom conductive layer and the top conductive layer of the resistor area simultaneously, thereby the patterned stacked structure in the resistor area constituting the non-inductive resistor.
    Type: Grant
    Filed: July 4, 2014
    Date of Patent: June 23, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhibiao Zhou, Shao-Hui Wu, Chi-Fa Ku
  • Patent number: 9048127
    Abstract: The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: June 2, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hsien Tsai, Hsieh-Hung Hsieh, Tzu-Jin Yeh, Chewn-Pu Jou, Sa-Lly Liu, Fu-Lung Hsueh
  • Publication number: 20150145100
    Abstract: A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 28, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai, Xiaomeng Chen, Chen-Jong Wang
  • Publication number: 20150144864
    Abstract: Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction.
    Type: Application
    Filed: January 30, 2015
    Publication date: May 28, 2015
    Inventors: Fabio Pellizzer, Roberto Bez, Lorenzo Fratin
  • Publication number: 20150145104
    Abstract: An integrated capacitor includes a substrate with a first main surface area and an opposing second main surface area. A capacitor structure with a dielectric layer is integrated in the first main surface area. A compensation structure with a compensation layer is integrated in the second main surface area. The ratio between a surface enlargement of the second main surface area effected by the compensation structure corresponds to at least 30% of the surface enlargement of the first main surface area effected by the capacitor structure.
    Type: Application
    Filed: November 21, 2014
    Publication date: May 28, 2015
    Inventors: Anton BAUER, Tobias ERLBACHER, Holger SCHWARZMANN
  • Publication number: 20150145101
    Abstract: A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region. The semiconductor arrangement includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where an electrode unit of the first electrode has a first portion and a second portion, and where the second portion is above the first portion and is wider than the first portion.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 28, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chern-Yow Hsu, Shih-Chang Liu, Chia- Shiung Tsai, Xiaomeng Chen, Chen-Jong Wang
  • Patent number: 9040948
    Abstract: A nanoscale switching device comprises a first electrode of a nanoscale width; a second electrode of a nanoscale width; an active region disposed between the first and second electrodes, the active region containing a switching material; an area within the active region that constrains current flow between the first electrode and the second electrode to a central portion of the active region; and an interlayer dielectric layer formed of a dielectric material and disposed between the first and second electrodes outside the active region. A nanoscale crossbar array and method of forming the nanoscale switching device are also disclosed.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: May 26, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Gilberto Ribeiro, Janice H Nickel, Jianhua Yang
  • Patent number: 9040381
    Abstract: A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Der-Chyang Yeh, Shuo-Mao Chen, Chiung-Han Yeh, Yi-Jou Lin
  • Patent number: 9041151
    Abstract: A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes an enhanced performance electrical fuse formed in a polysilicon fin using a trench silicide process. In one embodiment, at least one semiconductor fin is formed on a dielectric layer present on the surface of a semiconductor substrate. An isolation layer may be formed over the exposed portions of the dielectric layer and the at least one semiconductor fin. At least two contact vias may be formed through the isolation layer to expose the top surface of the semiconductor fin. A continuous silicide may be formed on and substantially below the exposed surfaces of the semiconductor fin extending laterally at least between the at least two contact vias to form an electronic fuse (eFuse). In another embodiment, the at least one semiconductor fin may be subjected to ion implantation to facilitate the formation of silicide.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Christian Lavoie, Effendi Leobandung, Dan Moy
  • Patent number: 9041157
    Abstract: An electrically actuated device comprises an active region disposed between a first electrode and a second electrode, a substantially nonrandom distribution of dopant initiators at an interface between the active region and the first electrode, and a substantially nonrandom distribution of dopants in a portion of the active region adjacent to the interface.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: May 26, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Wei Wu, Sagi Varghese Mathai, Shih-Yuan (SY) Wang, Jianhua Yang
  • Publication number: 20150140772
    Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a low band gap dielectric layer disposed between two higher band gap dielectric layers. The high band gap dielectric layers can be doped with doping materials to form traps at energy levels higher than the operating voltage of the memory device.
    Type: Application
    Filed: December 3, 2014
    Publication date: May 21, 2015
    Inventors: Venkat Ananthan, Prashant B. Phatak
  • Publication number: 20150140774
    Abstract: A method of fabricating a semiconductor device comprises forming a first etch stop layer over a first dielectric layer. The method also comprises forming a first trench in the first etch stop layer and the first dielectric layer. The method further comprises filling the first trench with a conductive material. The method additionally comprises forming a second etch stop layer over the first etch stop layer. The method also comprises forming a second dielectric layer over the second etch stop layer. The method further comprises forming a second trench to expose the conductive material. The second trench is formed having a depth less than a total thickness of the first etch stop layer, the second etch stop layer and the second dielectric layer. The method additionally comprises depositing a first metal layer over sidewalls of the second trench and in contact with the conductive material.
    Type: Application
    Filed: January 27, 2015
    Publication date: May 21, 2015
    Inventors: Chih-Yang PAI, Kuo-Chi TU, Wen-Chuan CHIANG, Chung-Yen CHOU