Resistor Patents (Class 438/382)
  • Patent number: 11101293
    Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: August 24, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryota Hodo, Motomu Kurata, Shinya Sasagawa, Satoru Okamoto, Shunpei Yamazaki
  • Patent number: 11057019
    Abstract: A non-volatile adjustable phase shifter is coupled to a transceiver in a wireless communication device. The non-volatile adjustable phase shifter includes a non-volatile radio frequency (RF) switch. In one implementation, the non-volatile RF switch is a phase-change material (PCM) RF switch. In one approach, the non-volatile adjustable phase shifter includes a selectable transmission delay arm and a selectable transmission reference arm. A phase shift caused by the non-volatile adjustable phase shifter is adjusted when the non-volatile RF switch engages with or disengages from the selectable transmission delay arm. In another approach, the non-volatile adjustable phase shifter includes a selectable impedance element. A phase shift caused by the non-volatile adjustable phase shifter is adjusted when the non-volatile RF switch engages with or disengages from the selectable impedance element. In either approach, the phase shift changes a phase of RF signals being transmitted from or received by the transceiver.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: July 6, 2021
    Assignee: Newport Fab, LLC
    Inventors: Nabil El-Hinnawy, Gregory P. Slovin, Chris Masse, David J. Howard
  • Patent number: 11050023
    Abstract: Devices with settable resistance and methods of forming the same include forming vertical dielectric structures from heterogeneous dielectric materials on a first electrode. A second electrode is formed on the vertical dielectric structures.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: June 29, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jianshi Tang, Takashi Ando, Reinaldo Vega, Praneet Adusumilli
  • Patent number: 11037991
    Abstract: A variable resistance memory device includes memory cells arranged on a substrate and an insulating structure between the memory cells. Each of the memory cells includes a variable resistance pattern and a switching pattern vertically stacked on the substrate. The insulating structure includes a first insulating pattern between the memory cells, and a second insulating pattern between the first insulating pattern and each of the memory cells. The first insulating pattern includes a material different from a material of the second insulating pattern.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: June 15, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoongoo Kang, Changwoo Seo, Dain Lee, Wook-Yeol Yi, Hoi Sung Chung
  • Patent number: 11031412
    Abstract: A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Chi Wu, Yu-Wen Tseng
  • Patent number: 11004478
    Abstract: A semiconductor memory device according to an embodiment includes: a substrate having a substrate plane extending in a first direction and a second direction intersecting with the first direction; a first wiring provided above the substrate, the first wiring being provided so that a longitudinal direction extends along the first direction; a second wiring provided above the substrate, the second wiring being separated from the first wiring in the first direction, the second wiring being passed by the same virtual line together with the first wiring, the second wiring being provided so that a longitudinal direction extends along the first direction; a third wiring provided between the first wiring and the second wiring, the third wiring being separated from the first wiring and the second wiring, the third wiring being passed by the same virtual line together with the first wiring and the second wiring, the third wiring being provided so that a longitudinal direction extends along the first direction; a fourth
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: May 11, 2021
    Assignee: Kioxia Corporation
    Inventors: Hiroyuki Hara, Atsushi Kawasumi
  • Patent number: 10978558
    Abstract: A semiconductor device includes a first stacked structure including word lines and dielectric layers alternately stacked over a substrate. The semiconductor device also includes a plurality of first vertical channel structures formed through the first stacked structure and a second stacked structure including gate electrodes and dielectric layers alternately stacked over the first stacked structure. The semiconductor device further includes a plurality of second vertical channel structures formed through the second stacked structure, wherein the plurality of second vertical channel structures are respectively connected to the plurality of first vertical channel structures. The semiconductor device additionally includes an isolating layer for isolating the plurality of second vertical channel structures into first and second regions.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: April 13, 2021
    Assignee: SK hynix Inc.
    Inventor: In-Su Park
  • Patent number: 10930661
    Abstract: Embodiments of 3D memory devices and fabricating methods thereof are disclosed. The device comprises an array device semiconductor structure comprising an array interconnect layer disposed on the alternating conductor/dielectric stack and including a first interconnect structure. The device further comprises a peripheral device semiconductor structure comprising a peripheral interconnect layer disposed on a peripheral device and including a second interconnect structure. The device further comprises a pad embedded in the array device semiconductor structure or the peripheral interconnect layer, and a pad opening exposing a surface of the pad. The array interconnect layer is bonded with the peripheral interconnect layer, and the pad is electrically connected with the peripheral device through the first interconnect structure or the second interconnect structure.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: February 23, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jun Chen, Zhiliang Xia, Li Hong Xiao
  • Patent number: 10923572
    Abstract: A layout of a semiconductor device is stored on a non-transitory computer-readable medium. The layout includes a first transistor in an active device region and a second transistor in a guard ring region. The first transistor includes a first channel region, a first gate structure across the first channel region, and a first source region and a first drain region on opposite sides of the first channel region. The second transistor includes a second channel region, a second gate structure across the second channel region, a second source region and a second drain region on opposite sides of the second channel region. The second channel region includes a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Amit Kundu, Jaw-Juinn Horng
  • Patent number: 10923654
    Abstract: A variable resistance memory device includes a word line extending in a first direction, a bit line on the word line and extending in a second direction intersecting the first direction, a switching pattern between the bit line and the word line, a phase change pattern between the switching pattern and the word line, and a bottom electrode between the phase change pattern and the word line, wherein the phase change pattern has a bottom area greater than a top area of the bottom electrode, a thickness of the phase change pattern being greater than a thickness of the bottom electrode, and wherein the bottom and top areas are defined in the first and second directions, and the thicknesses are defined in a third direction intersecting the first and second directions.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ilmok Park, Kyusul Park, Seulji Song, Kwang-Woo Lee
  • Patent number: 10839899
    Abstract: A power on reset method for a resistive memory storage device is provided and includes performing a forming procedure on a memory cell of the resistive memory storage device. The forming procedure includes applying at least one forming voltage and at least one reset voltage to the memory cell. The forming procedure further includes a thermal step. The step of applying at least one reset voltage to the memory cell may be preformed before or after the thermal step. After one forming voltage is applied, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. After the thermal step, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. In addition, after one reset voltage is applied, if the memory cell passes verification, the next reset voltage is not applied to the memory cell.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 17, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Ping-Kun Wang, Shao-Ching Liao, Yu-Ting Chen, Ming-Che Lin, Chien-Min Wu, Chia-Hua Ho
  • Patent number: 10816589
    Abstract: A structure for testing a semiconductor device.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: October 27, 2020
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Xiaobing Ren, Qun Liu
  • Patent number: 10804466
    Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Hyun Jeong, Jin-Woo Lee, Gwan-Hyeob Koh, Dae-Hwan Kang
  • Patent number: 10749110
    Abstract: Two-terminal memory devices can be formed in dielectric material that is electrically insulating and operates as a blocking layer to mitigate diffusion of material from a metal layer. A stack of layers of the two-terminal memory device can be covered with a liner layer that can comprise the dielectric material. Thus, in some implementations, the liner layer and the blocking layer can have a similar etch rate.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: August 18, 2020
    Assignee: Crossbar, Inc.
    Inventors: Sundar Narayanan, Zhen Gu, Natividad Vasquez
  • Patent number: 10741756
    Abstract: A method of forming a phase change memory device is provided. The method includes depositing an electrode layer on a phase change material core, and forming a sacrificial layer on the electrode layer. The method further includes depositing a planarization layer on the sacrificial layer, and depositing an anti-reflective coating on the planarization layer. The method further includes forming a template on the anti-reflective coating, and removing a portion of the anti-reflective coating, a portion of the planarization layer, and a portion of the sacrificial layer to form a reduced height sacrificial layer and a sacrificial layer section beneath the planarization layer section. The method further includes removing the anti-reflective coating section and planarization layer section to expose the sacrificial layer section, and removing the reduced height sacrificial layer and a portion of the electrode layer to form a top electrode on the phase change material core.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Injo Ok, Nicole Saulnier, Iqbal R. Saraf, Kevin W. Brew
  • Patent number: 10741487
    Abstract: Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: August 11, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Mark Griswold
  • Patent number: 10679938
    Abstract: An electronic device comprises a first semiconductor die; a power transistor integrated in the first semiconductor die, the power transistor comprising a first gate, a first terminal, and a second terminal; a first sense transistor integrated in the first semiconductor die, the first sense transistor comprising a second gate and third and fourth terminals, the second gate coupled to the first gate and the fourth terminal coupled to the second terminal; a first resistor integrated in the first semiconductor die, the first resistor has a first temperature coefficient; a second sense transistor integrated in the first semiconductor die, the second sense transistor comprising a third gate and seventh and eighth terminals, the third gate coupled to the first gate and the eighth terminal coupled to the second terminal; and a second resistor integrated in the first semiconductor die, the second resistor has a second temperature coefficient.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: June 9, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kuntal Joardar, Min Chu, Vijay Krishnamurthy, Tikno Harjono, Ankur Chauhan, Vinayak Hegde, Manish Srivastava
  • Patent number: 10608178
    Abstract: The present disclosure includes memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode, a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode, and a storage element between the first electrode and the electrode contact portion of the second electrode.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Sills
  • Patent number: 10559654
    Abstract: A semiconductor structure is provided that includes a semiconductor substrate including a first device region and a second device region. First trench isolation structures surround the first and second device regions and extend below first and second pedestal portions of the semiconductor substrate. A first semiconductor material fin stack is located above the first pedestal portion of the semiconductor substrate, and a second semiconductor material fin stack is located above the second pedestal portion of the semiconductor substrate. Second trench isolation structures are located at ends of each first and second semiconductor material fin stacks. A portion of each second trench isolation structure is located directly between a bottommost surface of the first or second semiconductor material fin stack and the first or second pedestal portion of the semiconductor substrate.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Balasubramanian Pranatharthiharan, Injo Ok, Soon-Cheon Seo, Charan Veera Venkata Satya Surisetty
  • Patent number: 10497751
    Abstract: The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyu-Rie Sim, Gwan-Hyeob Koh, Dae-Hwan Kang
  • Patent number: 10490738
    Abstract: In one aspect, a resistive switching memory device includes a first electrode and a second electrode having interposed therebetween a first inner region and a second inner region, where the first and second inner regions contacting each other. The first inner region includes one or more metal oxide layers and the second inner region consists of a plurality of layers, where each of the layers of the second inner region is an insulating, a semi-insulating or a semiconducting layer. The second inner region comprises one or more layers having a stoichiometric or off-stoichiometric composition of a material selected from the group consisting of SiGex, SiNx, AlOx, MgOx, AINx, HfOx, HfSiOx, ZrOx, ZrSiOx, GdAlOx, DyScOx, TaOx and combinations thereof. The second inner region comprises one or more silicon-containing layers, such that one of the one or more silicon-containing layers contacts the first inner region.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: November 26, 2019
    Assignee: IMEC vzw
    Inventor: Bogdan Govoreanu
  • Patent number: 10332956
    Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Baozhen Li, Kirk Peterson, John Sheets, Lawrence A. Clevenger, Junli Wang, Chih-Chao Yang
  • Patent number: 10312438
    Abstract: A method for manufacturing a semiconductor memory device includes forming a first silicon layer on a bottom conductive layer, transforming the first silicon layer into a first polysilicon layer, forming a second silicon layer stacked on the first polysilicon layer, and a third silicon layer stacked on the second silicon layer, transforming the second and third silicon layers into second and third polysilicon layers, wherein the first and third polysilicon layers have a first doping type, and the second polysilicon layer has a second doping type different from the first doping type, forming an amorphous silicon layer on the third polysilicon layer, and forming a top conductive layer on the amorphous silicon layer.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari
  • Patent number: 10297669
    Abstract: A semiconductor structure can include a resistor on a substrate formed simultaneously with other devices, such as transistors. A diffusion barrier layer formed on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor at the same manner and time as the gate of the transistor. The filler material is removed to form a resistor on a substrate.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hua Feng Chen, Shu-Hui Wang, Mu-Chi Chiang
  • Patent number: 10256316
    Abstract: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, a trench contact formed on and in contact with the source/drain, and a source/drain contact formed on an in contact with the trench contact. A recess is formed in a portion of the source/drain contact using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the source/drain contact. A metallization layer is formed in contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng
  • Patent number: 10079355
    Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Ching-Tzu Chen, Joel D. Chudow
  • Patent number: 10056753
    Abstract: This document discusses, among other things, an electro-static discharge (EDS) filtering circuit and method, a reset circuit, and an electronic device. The ESD filtering circuit comprises a first current dividing circuit and a second current dividing circuit which respectively share a current of a first power source signal and aggregate the shared currents to form a second power source signal upon filtering, wherein a voltage drop of the first current dividing circuit is constant and the second current dividing circuit is a pure resistor element circuit.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: August 21, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Peng Zhu, Lei Huang, Yongliang Li
  • Patent number: 10049738
    Abstract: A memristor includes a bottom electrode, a top electrode, and an active region disposed therebetween. The active region has an electrically conducting filament in an electrically insulating medium, extending between the bottom electrode and the top electrode. The memristor further includes a temperature gradient element for controlling switching.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: August 14, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gary Gibson, R. Stanley Williams
  • Patent number: 10026686
    Abstract: Various embodiments of transistor assemblies, integrated circuit devices, and related methods are disclosed herein. In some embodiments, a transistor assembly may include a base layer in which a transistor is disposed, a first metal layer, and a second metal layer disposed between the base layer and the first metal layer. The transistor assembly may also include a capacitor, including a sheet of conductive material with a channel therein, disposed in the base layer or the second metal layer and coupled to a supply line of the transistor. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Silvio E. Bou-Ghazale, Rany T. Elsayed, Niti Goel
  • Patent number: 9997293
    Abstract: A ceramic electronic component that includes a ceramic main body, a coating film and external electrodes on the surface of the ceramic main body. The coating film is selectively formed on the surface of the ceramic main body by applying, to the surface of the ceramic main body, a resin-containing solution that etches the surface of the ceramic main body so as to ionize constituent elements of the ceramic main body. The coating film includes a resin and the constituent elements of the ceramic main body, which were ionized and deposited from the ceramic main body.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: June 12, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Mitsunori Inoue, Tomohiko Mori
  • Patent number: 9887354
    Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: February 6, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Hyun Jeong, Jin-Woo Lee, Gwan-Hyeob Koh, Dae-Hwan Kang
  • Patent number: 9871099
    Abstract: A semiconductor structure is provided that includes a semiconductor substrate including a first device region and a second device region. First trench isolation structures surround the first and second device regions and extend below first and second pedestal portions of the semiconductor substrate. A first semiconductor material fin stack is located above the first pedestal portion of the semiconductor substrate, and a second semiconductor material fin stack is located above the second pedestal portion of the semiconductor substrate. Second trench isolation structures are located at ends of each first and second semiconductor material fin stacks. A portion of each second trench isolation structure is located directly between a bottommost surface of the first or second semiconductor material fin stack and the first or second pedestal portion of the semiconductor substrate.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Balasubramanian Pranatharthiharan, Injo Ok, Soon-Cheon Seo, Charan Veera Venkata Satya Surisetty
  • Patent number: 9728733
    Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: August 8, 2017
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Ching-Tzu Chen, Joel D. Chudow
  • Patent number: 9698346
    Abstract: A thermally optimized phase change memory cell includes a phase change material element disposed between first and second electrodes. The second electrode includes a thermally insulating region having a first thermal resistivity over the first electrode and a metallic contact region interposed between the phase change material element and the thermally insulating region, where the metallic contact layer has a second thermal resistivity lower than the first thermal resistivity.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: July 4, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Mattia Boniardi, Andrea Redaelli
  • Patent number: 9685530
    Abstract: A method for manufacturing a field effect transistor includes chelating a molecular mask to a replacement metal gate in a field effect transistor. The method may further include forming a patterned dielectric layer on a bulk dielectric material and a gate dielectric barrier in one or more deposition steps. The method may include removing the molecular mask and exposing part of the gate dielectric barrier before depositing a dielectric cap that touches the gate dielectric barrier and the replacement metal gate.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: June 20, 2017
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Michael A. Guillorn, Balasubramanian Pranatharthiharan, George S. Tulevski
  • Patent number: 9536983
    Abstract: A method of forming a semiconductor device includes forming a gate electrode on a substrate, forming a first spacer on a sidewall of the gate electrode, forming a second spacer on the first spacer, and forming a capping pattern on top surfaces of the gate electrode, the first spacer and the second spacer. An outer sidewall of the second spacer is vertically aligned with a sidewall of the capping pattern.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: January 3, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doo-Young Lee, Dohyoung Kim, Johnsoo Kim, Heungsik Park, Hongsik Shin, Younghun Choi
  • Patent number: 9537010
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a doped region in an upper portion of the substrate. The doped region is doped with first dopants of a first conduction type. The semiconductor device structure includes one fin structure over the substrate. A first dopant concentration of the doped region exposed by the fin structure is greater than a second dopant concentration of the doped region covered by the fin structure. The semiconductor device structure includes an isolation layer over the substrate and at two opposite sides of the fin structure. The semiconductor device structure includes a gate over the isolation layer and the fin structure.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsan-Chun Wang, Ziwei Fang, Chien-Tai Chan, Da-Wen Lin, Huicheng Chang
  • Patent number: 9429967
    Abstract: An embodiment of an electrically trimmable electronic device, wherein a resistor of electrically modifiable material is formed by a first generally strip-shaped portion and by a second generally strip-shaped portion, which extend transversely with respect to one another and are in direct electrical contact in a crossing area. The first and second portions have respective ends connected to own contact regions, coupled to a current pulse source and are made of the same material or of the same composition of materials starting from a same resistive layer of the material having electrically modifiable resistivity, for example, a phase-change material, such as a Ge—Sb—Te alloy, or polycrystalline silicon, or a metal material used for thin-film resistors. The trimming is performed by supplying a trimming current to the second portion so as to heat the crossing area and modify the resistivity thereof, without flowing longitudinally in the first portion.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: August 30, 2016
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Stefania Maria Serena Privitera, Antonello Santangelo
  • Patent number: 9385127
    Abstract: An inverter includes: a PMOS comprising: a p-type source region, a p-type drain region, a p-channel region between the p-type source region and the p-type drain region, and a PMOS metal gate region; a NMOS, comprising: an n-type source region, an n-type drain region, an n-channel region between the n-type source region and the n-type drain region, and a NMOS metal gate region; an insulating layer above the p-channel region and the n-channel region, wherein the PMOS metal gate region and the NMOS metal gate region are above the insulating layer; and a gate contact between the NMOS metal gate region and the PMOS metal gate region.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: July 5, 2016
    Assignee: XILINX, INC.
    Inventors: Qi Lin, Hong-Tsz Pan, Yun Wu, Bang-Thu Nguyen
  • Patent number: 9362498
    Abstract: A method of forming a memory includes forming a first electrode and a second electrode within a first layer over a semiconductor substrate, forming a resistive-switching memory element and an antifuse element over the first layer, wherein the resistive-switching memory element includes a metal oxide layer and is electrically contacting the first electrode, wherein the metal oxide layer has a first thickness and a forming voltage that corresponds to the first thickness, wherein the antifuse element includes a dielectric layer and is electrically contacting the second electrode, and wherein the dielectric layer has a second thickness that is less than the first thickness and a dielectric breakdown voltage that is less than the forming voltage, and forming a third electrode and a fourth electrode within a second layer over the resistive-switching memory element and the antifuse element, wherein the third electrode is electrically contacting the resistive-switching memory element and the fourth electrode is elect
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: June 7, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Klaus Knobloch, Robert Strenz
  • Patent number: 9231069
    Abstract: A method comprises forming a gate trench between a plurality of gate spacers over a substrate, forming a resistor trench over the substrate, depositing a first layer on a bottom of the gate trench, a bottom of the resistor trench, sidewalls of the gate trench and sidewalls of the resistor trench, depositing a second layer over the first layer, depositing a gate electrode layer over the second layer and applying a chemical mechanical polish process to the gate electrode layer until the gate electrode layer is removed from the resistor trench.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Jung Yen, Jen-Pan Wang
  • Patent number: 9202827
    Abstract: The silicon nitride layer 910 formed by plasma CVD using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3) is provided on and in direct contact with the oxide semiconductor layer 905 used for the resistor 354, and the silicon nitride layer 910 is provided over the oxide semiconductor layer 906 used for the thin film transistor 355 with the silicon oxide layer 909 serving as a barrier layer interposed therebetween. Therefore, a higher concentration of hydrogen is introduced into the oxide semiconductor layer 905 than into the oxide semiconductor layer 906. As a result, the resistance of the oxide semiconductor layer 905 used for the resistor 354 is made lower than that of the oxide semiconductor layer 906 used for the thin film transistor 355.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: December 1, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Junichiro Sakata, Tetsunori Maruyama, Yuki Imoto, Yuji Asano, Junichi Koezuka
  • Patent number: 9190455
    Abstract: A semiconductor memory device according to an embodiment has a memory cell array including: a plurality of lower wirings extending in the first direction; a plurality of upper wirings extending in the second direction, the upper wirings placed above the plurality of lower wirings; a plurality of memory cells provided at respective crossings of the plurality of lower wirings and the plurality of upper wirings; and an interlayer insulating film provided between the plurality of memory cells adjacent in the second direction, and the device is characterized in that the upper wiring includes: an upper firing first section deposited on the memory cell; and an upper wiring second section deposited on the interlayer insulating film, the upper wiring second section larger in crystal grain size than the upper wiring first section, and an upper surface of the memory cell is lower than an upper surface of the interlayer insulating film.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: November 17, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kotaro Noda
  • Patent number: 9082966
    Abstract: Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may include memory cells coupled to conductive lines. Methods of forming such semiconductor devices and structures include removing memory cell material from a peripheral region and, thereafter, selectively removing portions of the memory cell material from the array region to define individual memory cells in the array region. Additional methods include planarizing the structure using peripheral conductive pads and/or spacer material over the peripheral conductive pads as a planarization stop material. Yet further methods include partially defining memory cells in the array region, thereafter forming peripheral conductive contacts, and thereafter fully defining the memory cells.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: July 14, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Giulio Albini
  • Patent number: 9082679
    Abstract: The present invention provides a manufacturing technique of a semiconductor device and a display device using a peeling process, in which a transfer process can be conducted with a good state in which a shape and property of an element before peeling are kept. Further, the present invention provides a manufacturing technique of more highly reliable semiconductor devices and display devices with high yield without complicating the apparatus and the process for manufacturing. According to the present invention, an organic compound layer including a photocatalyst substance is formed over a first substrate having a light-transmitting property, an element layer is formed over the organic compound layer including a photocatalyst substance, the organic compound layer including a photocatalyst substance is irradiated with light which has passed through the first substrate, and the element layer is peeled from the first substrate.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: July 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiro Jinbo, Masafumi Morisue, Hajime Kimura, Shunpei Yamazaki
  • Patent number: 9076963
    Abstract: A phase change memory cell includes a first electrode having a cylindrical portion. A dielectric material having a cylindrical portion is longitudinally over the cylindrical portion of the first electrode. Heater material is radially inward of and electrically coupled to the cylindrical portion of the first electrode. Phase change material is over the heater material and a second electrode is electrically coupled to the phase change material. Other embodiments are disclosed, including methods of forming memory cells which include first and second electrodes having phase change material and heater material in electrical series there-between.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: July 7, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Damon E. Van Gerpen
  • Patent number: 9059090
    Abstract: A method of fabricating a semiconductor device includes forming a first gate pattern and a dummy gate pattern on a first active area and a second active area of a substrate, respectively, the first gate pattern including a first gate insulating layer and a silicon gate electrode, removing the dummy gate pattern to expose a surface of the substrate in the second active area, forming a second gate pattern including a second gate insulating layer and a metal gate electrode on the exposed surface of the substrate, the first gate insulating layer having a thickness larger than a thickness of the second gate insulating layer, and forming a gate silicide on the silicon gate electrode after forming the second gate pattern.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: June 16, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Youn Kim, Hyun-Min Choi, Sung-Kee Han, Je-Don Kim
  • Publication number: 20150147866
    Abstract: A resistive-switching memory element is described. The memory element includes a first electrode, a porous layer over the first electrode including a point defect embedded in a plurality of pores of the porous layer, and a second electrode over the porous layer, wherein the nonvolatile memory element is configured to switch between a high resistive state and a low resistive state.
    Type: Application
    Filed: February 4, 2015
    Publication date: May 28, 2015
    Inventors: Tony P. Chiang, Chi-I Lang, Prashant B. Phatak
  • Publication number: 20150144861
    Abstract: Embodiments of the present invention disclose a resistive memory and a method for fabricating the same. The resistive memory comprises a bottom electrode, a resistive layer and a top electrode. The resistive layer is located over the bottom electrode. The top electrode is located over the resistive layer. A conductive protrusion is provided on the bottom electrode. The conductive protrusion is embedded in the resistive layer, and has a top width smaller than a bottom width. Embodiments of the present invention further disclose a method for fabricating a resistive memory. According to the resistive memory and the method for fabricating the same provided by the embodiments of the present invention, by means of providing the conductive protrusion on the bottom electrode, a “lightning rod” effect may be occurred so that an electric field in the resistive layer is intensively distributed near the conductive protrusion.
    Type: Application
    Filed: July 8, 2013
    Publication date: May 28, 2015
    Inventors: Yimao Cai, Shihui Yin, Ru Huang, Yichen Fang
  • Publication number: 20150147865
    Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode, the switching layer comprising a first metal oxide having a first bandgap greater than 4 electron volts (eV), the switching layer having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a second metal oxide having a second bandgap greater the first bandgap, the coupling layer having a second thickness that is less than 25 percent of the first thickness.
    Type: Application
    Filed: February 3, 2015
    Publication date: May 28, 2015
    Inventors: Ronald John Kuse, Tony Chiang, Michael Miller, Prashant Phatak, Jinhong Tong